| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 22248000 # Number of ticks simulated 5final_tick 22248000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 23776000 # Number of ticks simulated 5final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 114507 # Simulator instruction rate (inst/s) 8host_op_rate 114481 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 398824007 # Simulator tick rate (ticks/s) 10host_mem_usage 254412 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 93889 # Simulator instruction rate (inst/s) 8host_op_rate 93856 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 349385939 # Simulator tick rate (ticks/s) 10host_mem_usage 252568 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host |
| 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 19system.physmem.bytes_read::total 31040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 485 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 19system.physmem.bytes_read::total 31040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 485 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 897518878 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 497662711 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1395181589 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 897518878 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 897518878 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 897518878 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 497662711 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1395181589 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 485 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 485 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 22109000 # Total gap between requests | 79system.physmem.totGap 23381000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 485 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 485 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 352.842105 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 230.159600 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 321.021248 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 19 25.00% 48.68% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 9 11.84% 60.53% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 11 14.47% 75.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 6 7.89% 82.89% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 1 1.32% 84.21% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.63% 86.84% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation 203system.physmem.totQLat 4498250 # Total ticks spent queuing 204system.physmem.totMemAccLat 13592000 # Total ticks spent from burst creation until serviced by the DRAM | 190system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation 204system.physmem.totQLat 8009750 # Total ticks spent queuing 205system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 9274.74 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 28024.74 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1395.18 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1395.18 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.physmem.busUtil 10.90 # Data bus utilization in percentage 215system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 10.20 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads |
| 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing | 218system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 394 # Number of row buffer hits during reads | 220system.physmem.readRowHits 395 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 81.24 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 45585.57 # Average gap between requests 224system.physmem.pageHitRate 81.24 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 1645800 # Energy for read commands per rank (pJ) | 224system.physmem.avgGap 48208.25 # Average gap between requests 225system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 13790805 # Total energy per rank (pJ) 233system.physmem_0.averagePower 871.044055 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) | 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) 237system.physmem_0.averagePower 621.784975 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states 245system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 10074465 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 662250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 13465350 # Total energy per rank (pJ) 247system.physmem_1.averagePower 850.487920 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 1034500 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 14291750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 254system.cpu.branchPred.lookups 2853 # Number of BP lookups 255system.cpu.branchPred.condPredicted 1680 # Number of conditional branches predicted 256system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect 257system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups | 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ) 256system.physmem_1.averagePower 629.216130 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2854 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups |
| 258system.cpu.branchPred.BTBHits 713 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 269system.cpu.branchPred.BTBHits 713 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 260system.cpu.branchPred.BTBHitPct 32.394366 # BTB Hit Percentage 261system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. 262system.cpu.branchPred.RASInCorrect 41 # Number of incorrect RAS predictions. 263system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. | 271system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups. |
| 264system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. | 275system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. |
| 265system.cpu.branchPred.indirectMisses 436 # Number of indirect misses. | 276system.cpu.branchPred.indirectMisses 437 # Number of indirect misses. |
| 266system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. 267system.cpu_clk_domain.clock 500 # Clock period in ticks 268system.cpu.dtb.fetch_hits 0 # ITB hits 269system.cpu.dtb.fetch_misses 0 # ITB misses 270system.cpu.dtb.fetch_acv 0 # ITB acv 271system.cpu.dtb.fetch_accesses 0 # ITB accesses | 277system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.fetch_hits 0 # ITB hits 280system.cpu.dtb.fetch_misses 0 # ITB misses 281system.cpu.dtb.fetch_acv 0 # ITB acv 282system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 272system.cpu.dtb.read_hits 2261 # DTB read hits | 283system.cpu.dtb.read_hits 2252 # DTB read hits |
| 273system.cpu.dtb.read_misses 48 # DTB read misses 274system.cpu.dtb.read_acv 0 # DTB read access violations | 284system.cpu.dtb.read_misses 48 # DTB read misses 285system.cpu.dtb.read_acv 0 # DTB read access violations |
| 275system.cpu.dtb.read_accesses 2309 # DTB read accesses 276system.cpu.dtb.write_hits 1039 # DTB write hits | 286system.cpu.dtb.read_accesses 2300 # DTB read accesses 287system.cpu.dtb.write_hits 1038 # DTB write hits |
| 277system.cpu.dtb.write_misses 28 # DTB write misses 278system.cpu.dtb.write_acv 0 # DTB write access violations | 288system.cpu.dtb.write_misses 28 # DTB write misses 289system.cpu.dtb.write_acv 0 # DTB write access violations |
| 279system.cpu.dtb.write_accesses 1067 # DTB write accesses 280system.cpu.dtb.data_hits 3300 # DTB hits | 290system.cpu.dtb.write_accesses 1066 # DTB write accesses 291system.cpu.dtb.data_hits 3290 # DTB hits |
| 281system.cpu.dtb.data_misses 76 # DTB misses 282system.cpu.dtb.data_acv 0 # DTB access violations | 292system.cpu.dtb.data_misses 76 # DTB misses 293system.cpu.dtb.data_acv 0 # DTB access violations |
| 283system.cpu.dtb.data_accesses 3376 # DTB accesses 284system.cpu.itb.fetch_hits 2294 # ITB hits | 294system.cpu.dtb.data_accesses 3366 # DTB accesses 295system.cpu.itb.fetch_hits 2295 # ITB hits |
| 285system.cpu.itb.fetch_misses 27 # ITB misses 286system.cpu.itb.fetch_acv 0 # ITB acv | 296system.cpu.itb.fetch_misses 27 # ITB misses 297system.cpu.itb.fetch_acv 0 # ITB acv |
| 287system.cpu.itb.fetch_accesses 2321 # ITB accesses | 298system.cpu.itb.fetch_accesses 2322 # ITB accesses |
| 288system.cpu.itb.read_hits 0 # DTB read hits 289system.cpu.itb.read_misses 0 # DTB read misses 290system.cpu.itb.read_acv 0 # DTB read access violations 291system.cpu.itb.read_accesses 0 # DTB read accesses 292system.cpu.itb.write_hits 0 # DTB write hits 293system.cpu.itb.write_misses 0 # DTB write misses 294system.cpu.itb.write_acv 0 # DTB write access violations 295system.cpu.itb.write_accesses 0 # DTB write accesses 296system.cpu.itb.data_hits 0 # DTB hits 297system.cpu.itb.data_misses 0 # DTB misses 298system.cpu.itb.data_acv 0 # DTB access violations 299system.cpu.itb.data_accesses 0 # DTB accesses 300system.cpu.workload.num_syscalls 17 # Number of system calls | 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.read_acv 0 # DTB read access violations 302system.cpu.itb.read_accesses 0 # DTB read accesses 303system.cpu.itb.write_hits 0 # DTB write hits 304system.cpu.itb.write_misses 0 # DTB write misses 305system.cpu.itb.write_acv 0 # DTB write access violations 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.data_hits 0 # DTB hits 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses 311system.cpu.workload.num_syscalls 17 # Number of system calls |
| 301system.cpu.pwrStateResidencyTicks::ON 22248000 # Cumulative time (in ticks) in various power states 302system.cpu.numCycles 44497 # number of cpu cycles simulated | 312system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states 313system.cpu.numCycles 47553 # number of cpu cycles simulated |
| 303system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 304system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 305system.cpu.fetch.icacheStallCycles 8475 # Number of cycles fetch is stalled on an Icache miss 306system.cpu.fetch.Insts 16557 # Number of instructions fetch has processed 307system.cpu.fetch.Branches 2853 # Number of branches that fetch encountered 308system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken 309system.cpu.fetch.Cycles 5121 # Number of cycles fetch has run and was not squashing or blocked 310system.cpu.fetch.SquashCycles 1044 # Number of cycles fetch has spent squashing | 316system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss 317system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed 318system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered 319system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken 320system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked 321system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing |
| 311system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 312system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps | 322system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 323system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps |
| 313system.cpu.fetch.CacheLines 2294 # Number of cache lines fetched 314system.cpu.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed 315system.cpu.fetch.rateDist::samples 14796 # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::mean 1.119019 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::stdev 2.502117 # Number of instructions fetched each cycle (Total) | 324system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed 326system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total) |
| 318system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 319system.cpu.fetch.rateDist::0 11808 79.81% 79.81% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::1 299 2.02% 81.83% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::2 232 1.57% 83.39% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::3 257 1.74% 85.13% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::4 292 1.97% 87.10% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::5 233 1.57% 88.68% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::6 283 1.91% 90.59% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::7 144 0.97% 91.57% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::8 1248 8.43% 100.00% # Number of instructions fetched each cycle (Total) | 330system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total) |
| 328system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 331system.cpu.fetch.rateDist::total 14796 # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.branchRate 0.064117 # Number of branch fetches per cycle 333system.cpu.fetch.rate 0.372093 # Number of inst fetches per cycle 334system.cpu.decode.IdleCycles 8328 # Number of cycles decode is idle 335system.cpu.decode.BlockedCycles 3356 # Number of cycles decode is blocked 336system.cpu.decode.RunCycles 2449 # Number of cycles decode is running 337system.cpu.decode.UnblockCycles 215 # Number of cycles decode is unblocking 338system.cpu.decode.SquashCycles 448 # Number of cycles decode is squashing | 342system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle 344system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle 345system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle 346system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 2446 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing |
| 339system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch 340system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction | 350system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch 351system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction |
| 341system.cpu.decode.DecodedInsts 15018 # Number of instructions handled by decode | 352system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode |
| 342system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode | 353system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode |
| 343system.cpu.rename.SquashCycles 448 # Number of cycles rename is squashing 344system.cpu.rename.IdleCycles 8488 # Number of cycles rename is idle 345system.cpu.rename.BlockCycles 1745 # Number of cycles rename is blocking 346system.cpu.rename.serializeStallCycles 620 # count of cycles rename stalled for serializing inst 347system.cpu.rename.RunCycles 2480 # Number of cycles rename is running 348system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking 349system.cpu.rename.RenamedInsts 14460 # Number of instructions processed by rename | 354system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing 355system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle 356system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking 357system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst 358system.cpu.rename.RunCycles 2476 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename |
| 350system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 351system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 352system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full | 361system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full |
| 353system.cpu.rename.SQFullEvents 949 # Number of times rename has blocked due to SQ full 354system.cpu.rename.RenamedOperands 10938 # Number of destination operands rename has renamed 355system.cpu.rename.RenameLookups 17913 # Number of register rename lookups that rename has made 356system.cpu.rename.int_rename_lookups 17904 # Number of integer rename lookups | 364system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full 365system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed 366system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made 367system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups |
| 357system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 358system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed | 368system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 369system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed |
| 359system.cpu.rename.UndoneMaps 6361 # Number of HB maps that are undone due to squashing | 370system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing |
| 360system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 361system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 362system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer | 371system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 373system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer |
| 363system.cpu.memDep0.insertedLoads 2839 # Number of loads inserted to the mem dependence unit. 364system.cpu.memDep0.insertedStores 1293 # Number of stores inserted to the mem dependence unit. | 374system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit. |
| 365system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. 366system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. | 376system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. 377system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. |
| 367system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) | 378system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec) |
| 368system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ | 379system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ |
| 369system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued | 380system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued |
| 370system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued | 381system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued |
| 371system.cpu.iq.iqSquashedInstsExamined 6710 # Number of squashed instructions iterated over during squash; mainly for profiling 372system.cpu.iq.iqSquashedOperandsExamined 3679 # Number of squashed operands that are examined and possibly removed from graph | 382system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling 383system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph |
| 373system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed | 384system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed |
| 374system.cpu.iq.issued_per_cycle::samples 14796 # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::mean 0.729048 # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::stdev 1.467428 # Number of insts issued each cycle | 385system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle |
| 377system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 388system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 378system.cpu.iq.issued_per_cycle::0 10757 72.70% 72.70% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::1 1291 8.73% 81.43% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::2 918 6.20% 87.63% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::3 680 4.60% 92.23% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::4 521 3.52% 95.75% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::5 349 2.36% 98.11% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::6 197 1.33% 99.44% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::7 55 0.37% 99.81% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle | 389system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle |
| 387system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 398system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 390system.cpu.iq.issued_per_cycle::total 14796 # Number of insts issued each cycle | 401system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle |
| 391system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 402system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 392system.cpu.iq.fu_full::IntAlu 21 15.00% 15.00% # attempts to use FU when none available 393system.cpu.iq.fu_full::IntMult 0 0.00% 15.00% # attempts to use FU when none available 394system.cpu.iq.fu_full::IntDiv 0 0.00% 15.00% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.00% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.00% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.00% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatMult 0 0.00% 15.00% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.00% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.00% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.00% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.00% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.00% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdMult 0 0.00% 15.00% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.00% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdShift 0 0.00% 15.00% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.00% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.00% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.00% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.00% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.00% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.00% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.00% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.00% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.00% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.00% # attempts to use FU when none available 421system.cpu.iq.fu_full::MemRead 82 58.57% 73.57% # attempts to use FU when none available 422system.cpu.iq.fu_full::MemWrite 37 26.43% 100.00% # attempts to use FU when none available | 403system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available 432system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available 433system.cpu.iq.fu_full::MemWrite 37 26.24% 100.00% # attempts to use FU when none available |
| 423system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 424system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 425system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued | 434system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 436system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| 426system.cpu.iq.FU_type_0::IntAlu 7188 66.64% 66.65% # Type of FU issued 427system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued 428system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued 455system.cpu.iq.FU_type_0::MemRead 2482 23.01% 89.69% # Type of FU issued 456system.cpu.iq.FU_type_0::MemWrite 1112 10.31% 100.00% # Type of FU issued | 437system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued 438system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued 439system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued 445system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued 466system.cpu.iq.FU_type_0::MemRead 2475 22.97% 89.69% # Type of FU issued 467system.cpu.iq.FU_type_0::MemWrite 1111 10.31% 100.00% # Type of FU issued |
| 457system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 458system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 468system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 469system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 459system.cpu.iq.FU_type_0::total 10787 # Type of FU issued 460system.cpu.iq.rate 0.242421 # Inst issue rate 461system.cpu.iq.fu_busy_cnt 140 # FU busy when requested 462system.cpu.iq.fu_busy_rate 0.012979 # FU busy rate (busy events/executed inst) 463system.cpu.iq.int_inst_queue_reads 36506 # Number of integer instruction queue reads 464system.cpu.iq.int_inst_queue_writes 19817 # Number of integer instruction queue writes 465system.cpu.iq.int_inst_queue_wakeup_accesses 9751 # Number of integer instruction queue wakeup accesses | 470system.cpu.iq.FU_type_0::total 10776 # Type of FU issued 471system.cpu.iq.rate 0.226610 # Inst issue rate 472system.cpu.iq.fu_busy_cnt 141 # FU busy when requested 473system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) 474system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads 475system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes 476system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses |
| 466system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 467system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 468system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses | 477system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 478system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 479system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses |
| 469system.cpu.iq.int_alu_accesses 10914 # Number of integer alu accesses | 480system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses |
| 470system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 471system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores 472system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 481system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 482system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores 483system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 473system.cpu.iew.lsq.thread0.squashedLoads 1654 # Number of loads squashed | 484system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed |
| 474system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 475system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations | 485system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 486system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations |
| 476system.cpu.iew.lsq.thread0.squashedStores 428 # Number of stores squashed | 487system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed |
| 477system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 478system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 479system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 488system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 489system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 490system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
| 480system.cpu.iew.lsq.thread0.cacheBlocked 89 # Number of times an access to memory failed due to the cache being blocked | 491system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked |
| 481system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 492system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 482system.cpu.iew.iewSquashCycles 448 # Number of cycles IEW is squashing 483system.cpu.iew.iewBlockCycles 1381 # Number of cycles IEW is blocking 484system.cpu.iew.iewUnblockCycles 302 # Number of cycles IEW is unblocking 485system.cpu.iew.iewDispatchedInsts 13180 # Number of instructions dispatched to IQ | 493system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing 494system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking 495system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking 496system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ |
| 486system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch | 497system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch |
| 487system.cpu.iew.iewDispLoadInsts 2839 # Number of dispatched load instructions 488system.cpu.iew.iewDispStoreInsts 1293 # Number of dispatched store instructions | 498system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions 499system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions |
| 489system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 490system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall | 500system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 501system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall |
| 491system.cpu.iew.iewLSQFullEvents 295 # Number of times the LSQ has become full, causing a stall | 502system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall |
| 492system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations 493system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly 494system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly 495system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute | 503system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations 504system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly 505system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly 506system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute |
| 496system.cpu.iew.iewExecutedInsts 10303 # Number of executed instructions 497system.cpu.iew.iewExecLoadInsts 2309 # Number of load instructions executed 498system.cpu.iew.iewExecSquashedInsts 484 # Number of squashed instructions skipped in execute | 507system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions 508system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed 509system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute |
| 499system.cpu.iew.exec_swp 0 # number of swp insts executed 500system.cpu.iew.exec_nop 84 # number of nop insts executed | 510system.cpu.iew.exec_swp 0 # number of swp insts executed 511system.cpu.iew.exec_nop 84 # number of nop insts executed |
| 501system.cpu.iew.exec_refs 3386 # number of memory reference insts executed 502system.cpu.iew.exec_branches 1643 # Number of branches executed 503system.cpu.iew.exec_stores 1077 # Number of stores executed 504system.cpu.iew.exec_rate 0.231544 # Inst execution rate 505system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit 506system.cpu.iew.wb_count 9761 # cumulative count of insts written-back 507system.cpu.iew.wb_producers 5150 # num instructions producing a value 508system.cpu.iew.wb_consumers 7013 # num instructions consuming a value 509system.cpu.iew.wb_rate 0.219363 # insts written-back per cycle 510system.cpu.iew.wb_fanout 0.734350 # average fanout of values written-back 511system.cpu.commit.commitSquashedInsts 6727 # The number of squashed insts skipped by commit | 512system.cpu.iew.exec_refs 3376 # number of memory reference insts executed 513system.cpu.iew.exec_branches 1642 # Number of branches executed 514system.cpu.iew.exec_stores 1076 # Number of stores executed 515system.cpu.iew.exec_rate 0.216390 # Inst execution rate 516system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit 517system.cpu.iew.wb_count 9755 # cumulative count of insts written-back 518system.cpu.iew.wb_producers 5155 # num instructions producing a value 519system.cpu.iew.wb_consumers 7025 # num instructions consuming a value 520system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle 521system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back 522system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit |
| 512system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards | 523system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards |
| 513system.cpu.commit.branchMispredicts 407 # The number of times a branch was mispredicted 514system.cpu.commit.committed_per_cycle::samples 13560 # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::mean 0.472124 # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::stdev 1.390428 # Number of insts commited each cycle | 524system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted 525system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle |
| 517system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 528system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 518system.cpu.commit.committed_per_cycle::0 11134 82.11% 82.11% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::1 1157 8.53% 90.64% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::2 469 3.46% 94.10% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::3 205 1.51% 95.61% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::4 133 0.98% 96.59% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::5 85 0.63% 97.22% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::6 96 0.71% 97.93% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::7 89 0.66% 98.58% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::8 192 1.42% 100.00% # Number of insts commited each cycle | 529system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle |
| 527system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 538system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 530system.cpu.commit.committed_per_cycle::total 13560 # Number of insts commited each cycle | 541system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle |
| 531system.cpu.commit.committedInsts 6402 # Number of instructions committed 532system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 533system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 534system.cpu.commit.refs 2050 # Number of memory references committed 535system.cpu.commit.loads 1185 # Number of loads committed 536system.cpu.commit.membars 0 # Number of memory barriers committed 537system.cpu.commit.branches 1056 # Number of branches committed 538system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 569system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 570system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 571system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction 572system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction 573system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 574system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 575system.cpu.commit.op_class_0::total 6402 # Class of committed instruction 576system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached | 542system.cpu.commit.committedInsts 6402 # Number of instructions committed 543system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 544system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 545system.cpu.commit.refs 2050 # Number of memory references committed 546system.cpu.commit.loads 1185 # Number of loads committed 547system.cpu.commit.membars 0 # Number of memory barriers committed 548system.cpu.commit.branches 1056 # Number of branches committed 549system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 580system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 581system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 582system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction 583system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction 584system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 585system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 586system.cpu.commit.op_class_0::total 6402 # Class of committed instruction 587system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached |
| 577system.cpu.rob.rob_reads 26146 # The number of ROB reads 578system.cpu.rob.rob_writes 27511 # The number of ROB writes | 588system.cpu.rob.rob_reads 26790 # The number of ROB reads 589system.cpu.rob.rob_writes 27482 # The number of ROB writes |
| 579system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself | 590system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 580system.cpu.idleCycles 29701 # Total number of cycles that the CPU has spent unscheduled due to idling | 591system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 581system.cpu.committedInsts 6385 # Number of Instructions Simulated 582system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated | 592system.cpu.committedInsts 6385 # Number of Instructions Simulated 593system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated |
| 583system.cpu.cpi 6.968990 # CPI: Cycles Per Instruction 584system.cpu.cpi_total 6.968990 # CPI: Total CPI of All Threads 585system.cpu.ipc 0.143493 # IPC: Instructions Per Cycle 586system.cpu.ipc_total 0.143493 # IPC: Total IPC of All Threads 587system.cpu.int_regfile_reads 12938 # number of integer regfile reads 588system.cpu.int_regfile_writes 7444 # number of integer regfile writes | 594system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction 595system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads 596system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle 597system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads 598system.cpu.int_regfile_reads 12923 # number of integer regfile reads 599system.cpu.int_regfile_writes 7437 # number of integer regfile writes |
| 589system.cpu.fp_regfile_reads 8 # number of floating regfile reads 590system.cpu.fp_regfile_writes 2 # number of floating regfile writes 591system.cpu.misc_regfile_reads 1 # number of misc regfile reads 592system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 600system.cpu.fp_regfile_reads 8 # number of floating regfile reads 601system.cpu.fp_regfile_writes 2 # number of floating regfile writes 602system.cpu.misc_regfile_reads 1 # number of misc regfile reads 603system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 593system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states | 604system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 594system.cpu.dcache.tags.replacements 0 # number of replacements | 605system.cpu.dcache.tags.replacements 0 # number of replacements |
| 595system.cpu.dcache.tags.tagsinuse 109.756228 # Cycle average of tags in use 596system.cpu.dcache.tags.total_refs 2407 # Total number of references to valid blocks. | 606system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use 607system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks. |
| 597system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. | 608system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. |
| 598system.cpu.dcache.tags.avg_refs 13.913295 # Average number of references to valid blocks. | 609system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks. |
| 599system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 610system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 600system.cpu.dcache.tags.occ_blocks::cpu.data 109.756228 # Average occupied blocks per requestor 601system.cpu.dcache.tags.occ_percent::cpu.data 0.026796 # Average percentage of cache occupancy 602system.cpu.dcache.tags.occ_percent::total 0.026796 # Average percentage of cache occupancy | 611system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor 612system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy 613system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy |
| 603system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id | 614system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id |
| 604system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 605system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id | 615system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 616system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id |
| 606system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id | 617system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id |
| 607system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses 608system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses 609system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 610system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits 611system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits | 618system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses 619system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses 620system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 621system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits 622system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits |
| 612system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits 613system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits | 623system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits 624system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits |
| 614system.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits 615system.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits 616system.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits 617system.cpu.dcache.overall_hits::total 2407 # number of overall hits | 625system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits 626system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits 627system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits 628system.cpu.dcache.overall_hits::total 2402 # number of overall hits |
| 618system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses 619system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses 620system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses 621system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses 622system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses 623system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses 624system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses 625system.cpu.dcache.overall_misses::total 537 # number of overall misses | 629system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses 630system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses 631system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses 632system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses 633system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses 634system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses 635system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses 636system.cpu.dcache.overall_misses::total 537 # number of overall misses |
| 626system.cpu.dcache.ReadReq_miss_latency::cpu.data 12910000 # number of ReadReq miss cycles 627system.cpu.dcache.ReadReq_miss_latency::total 12910000 # number of ReadReq miss cycles 628system.cpu.dcache.WriteReq_miss_latency::cpu.data 24562475 # number of WriteReq miss cycles 629system.cpu.dcache.WriteReq_miss_latency::total 24562475 # number of WriteReq miss cycles 630system.cpu.dcache.demand_miss_latency::cpu.data 37472475 # number of demand (read+write) miss cycles 631system.cpu.dcache.demand_miss_latency::total 37472475 # number of demand (read+write) miss cycles 632system.cpu.dcache.overall_miss_latency::cpu.data 37472475 # number of overall miss cycles 633system.cpu.dcache.overall_miss_latency::total 37472475 # number of overall miss cycles 634system.cpu.dcache.ReadReq_accesses::cpu.data 2079 # number of ReadReq accesses(hits+misses) 635system.cpu.dcache.ReadReq_accesses::total 2079 # number of ReadReq accesses(hits+misses) | 637system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles 638system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles 639system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles 640system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles 641system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles 642system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles 643system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles 644system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles 645system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses) 646system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses) |
| 636system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 637system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) | 647system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 648system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) |
| 638system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses 639system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses 640system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses 641system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses 642system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086580 # miss rate for ReadReq accesses 643system.cpu.dcache.ReadReq_miss_rate::total 0.086580 # miss rate for ReadReq accesses | 649system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses 650system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses 651system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses 652system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses 653system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses 654system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses |
| 644system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses 645system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses | 655system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses 656system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses |
| 646system.cpu.dcache.demand_miss_rate::cpu.data 0.182405 # miss rate for demand accesses 647system.cpu.dcache.demand_miss_rate::total 0.182405 # miss rate for demand accesses 648system.cpu.dcache.overall_miss_rate::cpu.data 0.182405 # miss rate for overall accesses 649system.cpu.dcache.overall_miss_rate::total 0.182405 # miss rate for overall accesses 650system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71722.222222 # average ReadReq miss latency 651system.cpu.dcache.ReadReq_avg_miss_latency::total 71722.222222 # average ReadReq miss latency 652system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68802.450980 # average WriteReq miss latency 653system.cpu.dcache.WriteReq_avg_miss_latency::total 68802.450980 # average WriteReq miss latency 654system.cpu.dcache.demand_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency 655system.cpu.dcache.demand_avg_miss_latency::total 69781.145251 # average overall miss latency 656system.cpu.dcache.overall_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency 657system.cpu.dcache.overall_avg_miss_latency::total 69781.145251 # average overall miss latency 658system.cpu.dcache.blocked_cycles::no_mshrs 2459 # number of cycles access was blocked | 657system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses 658system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses 659system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses 660system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses 661system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency 662system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency 663system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency 664system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency 665system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency 666system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency 667system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency 668system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency 669system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked |
| 659system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 670system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 660system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked | 671system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked |
| 661system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 672system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 662system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.186047 # average number of cycles each access was blocked | 673system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked |
| 663system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 664system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 665system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 666system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits 667system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits 668system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits 669system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 670system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits 671system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits 672system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 673system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 674system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 675system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 676system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 677system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 678system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 679system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses | 674system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 675system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 676system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits 678system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits 679system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits 680system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 681system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits 682system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits 683system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 684system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 687system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 688system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 689system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 690system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses |
| 680system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8568000 # number of ReadReq MSHR miss cycles 681system.cpu.dcache.ReadReq_mshr_miss_latency::total 8568000 # number of ReadReq MSHR miss cycles 682system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6031500 # number of WriteReq MSHR miss cycles 683system.cpu.dcache.WriteReq_mshr_miss_latency::total 6031500 # number of WriteReq MSHR miss cycles 684system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14599500 # number of demand (read+write) MSHR miss cycles 685system.cpu.dcache.demand_mshr_miss_latency::total 14599500 # number of demand (read+write) MSHR miss cycles 686system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14599500 # number of overall MSHR miss cycles 687system.cpu.dcache.overall_mshr_miss_latency::total 14599500 # number of overall MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048581 # mshr miss rate for ReadReq accesses 689system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048581 # mshr miss rate for ReadReq accesses | 691system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9401500 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.ReadReq_mshr_miss_latency::total 9401500 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7013500 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::total 7013500 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16415000 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::total 16415000 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16415000 # number of overall MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::total 16415000 # number of overall MSHR miss cycles 699system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048698 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048698 # mshr miss rate for ReadReq accesses |
| 690system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 691system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses | 701system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses |
| 692system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for demand accesses 693system.cpu.dcache.demand_mshr_miss_rate::total 0.058764 # mshr miss rate for demand accesses 694system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for overall accesses 695system.cpu.dcache.overall_mshr_miss_rate::total 0.058764 # mshr miss rate for overall accesses 696system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84831.683168 # average ReadReq mshr miss latency 697system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84831.683168 # average ReadReq mshr miss latency 698system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83770.833333 # average WriteReq mshr miss latency 699system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83770.833333 # average WriteReq mshr miss latency 700system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency 701system.cpu.dcache.demand_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency 702system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency 703system.cpu.dcache.overall_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency 704system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states | 703system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for demand accesses 704system.cpu.dcache.demand_mshr_miss_rate::total 0.058864 # mshr miss rate for demand accesses 705system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for overall accesses 706system.cpu.dcache.overall_mshr_miss_rate::total 0.058864 # mshr miss rate for overall accesses 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416 # average ReadReq mshr miss latency 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416 # average ReadReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222 # average WriteReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222 # average WriteReq mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency 715system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 705system.cpu.icache.tags.replacements 0 # number of replacements | 716system.cpu.icache.tags.replacements 0 # number of replacements |
| 706system.cpu.icache.tags.tagsinuse 159.084059 # Cycle average of tags in use 707system.cpu.icache.tags.total_refs 1838 # Total number of references to valid blocks. | 717system.cpu.icache.tags.tagsinuse 160.538154 # Cycle average of tags in use 718system.cpu.icache.tags.total_refs 1837 # Total number of references to valid blocks. |
| 708system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. | 719system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. |
| 709system.cpu.icache.tags.avg_refs 5.872204 # Average number of references to valid blocks. | 720system.cpu.icache.tags.avg_refs 5.869010 # Average number of references to valid blocks. |
| 710system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 721system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 711system.cpu.icache.tags.occ_blocks::cpu.inst 159.084059 # Average occupied blocks per requestor 712system.cpu.icache.tags.occ_percent::cpu.inst 0.077678 # Average percentage of cache occupancy 713system.cpu.icache.tags.occ_percent::total 0.077678 # Average percentage of cache occupancy | 722system.cpu.icache.tags.occ_blocks::cpu.inst 160.538154 # Average occupied blocks per requestor 723system.cpu.icache.tags.occ_percent::cpu.inst 0.078388 # Average percentage of cache occupancy 724system.cpu.icache.tags.occ_percent::total 0.078388 # Average percentage of cache occupancy |
| 714system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id | 725system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id |
| 715system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id 716system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id | 726system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id |
| 717system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id | 728system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id |
| 718system.cpu.icache.tags.tag_accesses 4901 # Number of tag accesses 719system.cpu.icache.tags.data_accesses 4901 # Number of data accesses 720system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 721system.cpu.icache.ReadReq_hits::cpu.inst 1838 # number of ReadReq hits 722system.cpu.icache.ReadReq_hits::total 1838 # number of ReadReq hits 723system.cpu.icache.demand_hits::cpu.inst 1838 # number of demand (read+write) hits 724system.cpu.icache.demand_hits::total 1838 # number of demand (read+write) hits 725system.cpu.icache.overall_hits::cpu.inst 1838 # number of overall hits 726system.cpu.icache.overall_hits::total 1838 # number of overall hits 727system.cpu.icache.ReadReq_misses::cpu.inst 456 # number of ReadReq misses 728system.cpu.icache.ReadReq_misses::total 456 # number of ReadReq misses 729system.cpu.icache.demand_misses::cpu.inst 456 # number of demand (read+write) misses 730system.cpu.icache.demand_misses::total 456 # number of demand (read+write) misses 731system.cpu.icache.overall_misses::cpu.inst 456 # number of overall misses 732system.cpu.icache.overall_misses::total 456 # number of overall misses 733system.cpu.icache.ReadReq_miss_latency::cpu.inst 32999500 # number of ReadReq miss cycles 734system.cpu.icache.ReadReq_miss_latency::total 32999500 # number of ReadReq miss cycles 735system.cpu.icache.demand_miss_latency::cpu.inst 32999500 # number of demand (read+write) miss cycles 736system.cpu.icache.demand_miss_latency::total 32999500 # number of demand (read+write) miss cycles 737system.cpu.icache.overall_miss_latency::cpu.inst 32999500 # number of overall miss cycles 738system.cpu.icache.overall_miss_latency::total 32999500 # number of overall miss cycles 739system.cpu.icache.ReadReq_accesses::cpu.inst 2294 # number of ReadReq accesses(hits+misses) 740system.cpu.icache.ReadReq_accesses::total 2294 # number of ReadReq accesses(hits+misses) 741system.cpu.icache.demand_accesses::cpu.inst 2294 # number of demand (read+write) accesses 742system.cpu.icache.demand_accesses::total 2294 # number of demand (read+write) accesses 743system.cpu.icache.overall_accesses::cpu.inst 2294 # number of overall (read+write) accesses 744system.cpu.icache.overall_accesses::total 2294 # number of overall (read+write) accesses 745system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198779 # miss rate for ReadReq accesses 746system.cpu.icache.ReadReq_miss_rate::total 0.198779 # miss rate for ReadReq accesses 747system.cpu.icache.demand_miss_rate::cpu.inst 0.198779 # miss rate for demand accesses 748system.cpu.icache.demand_miss_rate::total 0.198779 # miss rate for demand accesses 749system.cpu.icache.overall_miss_rate::cpu.inst 0.198779 # miss rate for overall accesses 750system.cpu.icache.overall_miss_rate::total 0.198779 # miss rate for overall accesses 751system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72367.324561 # average ReadReq miss latency 752system.cpu.icache.ReadReq_avg_miss_latency::total 72367.324561 # average ReadReq miss latency 753system.cpu.icache.demand_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency 754system.cpu.icache.demand_avg_miss_latency::total 72367.324561 # average overall miss latency 755system.cpu.icache.overall_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency 756system.cpu.icache.overall_avg_miss_latency::total 72367.324561 # average overall miss latency 757system.cpu.icache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked | 729system.cpu.icache.tags.tag_accesses 4903 # Number of tag accesses 730system.cpu.icache.tags.data_accesses 4903 # Number of data accesses 731system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 732system.cpu.icache.ReadReq_hits::cpu.inst 1837 # number of ReadReq hits 733system.cpu.icache.ReadReq_hits::total 1837 # number of ReadReq hits 734system.cpu.icache.demand_hits::cpu.inst 1837 # number of demand (read+write) hits 735system.cpu.icache.demand_hits::total 1837 # number of demand (read+write) hits 736system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits 737system.cpu.icache.overall_hits::total 1837 # number of overall hits 738system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses 739system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses 740system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses 741system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses 742system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses 743system.cpu.icache.overall_misses::total 458 # number of overall misses 744system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles 745system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles 746system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles 747system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles 748system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles 749system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles 750system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) 751system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) 752system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses 753system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses 754system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses 755system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses 756system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses 757system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses 758system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses 759system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses 760system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses 761system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses 762system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency 763system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency 764system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency 765system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency 766system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency 767system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency 768system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked |
| 758system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 759system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 760system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 769system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 770system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 771system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 761system.cpu.icache.avg_blocked_cycles::no_mshrs 56 # average number of cycles each access was blocked | 772system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked |
| 762system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 773system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 763system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits 764system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits 765system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits 766system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits 767system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits 768system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits | 774system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits 775system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits 776system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits 777system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits 778system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits 779system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits |
| 769system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 770system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 771system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 772system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 773system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 774system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses | 780system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 781system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 782system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 783system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 784system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 785system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses |
| 775system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24573000 # number of ReadReq MSHR miss cycles 776system.cpu.icache.ReadReq_mshr_miss_latency::total 24573000 # number of ReadReq MSHR miss cycles 777system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24573000 # number of demand (read+write) MSHR miss cycles 778system.cpu.icache.demand_mshr_miss_latency::total 24573000 # number of demand (read+write) MSHR miss cycles 779system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24573000 # number of overall MSHR miss cycles 780system.cpu.icache.overall_mshr_miss_latency::total 24573000 # number of overall MSHR miss cycles 781system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for ReadReq accesses 782system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136443 # mshr miss rate for ReadReq accesses 783system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for demand accesses 784system.cpu.icache.demand_mshr_miss_rate::total 0.136443 # mshr miss rate for demand accesses 785system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for overall accesses 786system.cpu.icache.overall_mshr_miss_rate::total 0.136443 # mshr miss rate for overall accesses 787system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78507.987220 # average ReadReq mshr miss latency 788system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78507.987220 # average ReadReq mshr miss latency 789system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency 790system.cpu.icache.demand_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency 791system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency 792system.cpu.icache.overall_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency 793system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states | 786system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles 787system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles 788system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles 789system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles 790system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles 791system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles 792system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses 793system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses 794system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses 795system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses 796system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses 797system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses 798system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency 799system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency 800system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency 801system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency 802system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency 803system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency 804system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 794system.cpu.l2cache.tags.replacements 0 # number of replacements | 805system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 795system.cpu.l2cache.tags.tagsinuse 268.962928 # Cycle average of tags in use | 806system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use |
| 796system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 797system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. 798system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. 799system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 807system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 808system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. 809system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. 810system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 800system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.125052 # Average occupied blocks per requestor 801system.cpu.l2cache.tags.occ_blocks::cpu.data 109.837876 # Average occupied blocks per requestor 802system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004856 # Average percentage of cache occupancy 803system.cpu.l2cache.tags.occ_percent::cpu.data 0.003352 # Average percentage of cache occupancy 804system.cpu.l2cache.tags.occ_percent::total 0.008208 # Average percentage of cache occupancy | 811system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor 812system.cpu.l2cache.tags.occ_blocks::cpu.data 110.259003 # Average occupied blocks per requestor 813system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004900 # Average percentage of cache occupancy 814system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy 815system.cpu.l2cache.tags.occ_percent::total 0.008265 # Average percentage of cache occupancy |
| 805system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id | 816system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id |
| 806system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id 807system.cpu.l2cache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id | 817system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id 818system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id |
| 808system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id 809system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses 810system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses | 819system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id 820system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses 821system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses |
| 811system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states | 822system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 812system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 813system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 814system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 815system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 816system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 817system.cpu.l2cache.overall_hits::total 1 # number of overall hits 818system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 819system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 820system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 312 # number of ReadCleanReq misses 821system.cpu.l2cache.ReadCleanReq_misses::total 312 # number of ReadCleanReq misses 822system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 823system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses 824system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 825system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 826system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses 827system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 828system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 829system.cpu.l2cache.overall_misses::total 485 # number of overall misses | 823system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 824system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 825system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 826system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 827system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 828system.cpu.l2cache.overall_hits::total 1 # number of overall hits 829system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 830system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 831system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 312 # number of ReadCleanReq misses 832system.cpu.l2cache.ReadCleanReq_misses::total 312 # number of ReadCleanReq misses 833system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 834system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses 835system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 836system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 837system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses 838system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 839system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 840system.cpu.l2cache.overall_misses::total 485 # number of overall misses |
| 830system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5920500 # number of ReadExReq miss cycles 831system.cpu.l2cache.ReadExReq_miss_latency::total 5920500 # number of ReadExReq miss cycles 832system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24090000 # number of ReadCleanReq miss cycles 833system.cpu.l2cache.ReadCleanReq_miss_latency::total 24090000 # number of ReadCleanReq miss cycles 834system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8408000 # number of ReadSharedReq miss cycles 835system.cpu.l2cache.ReadSharedReq_miss_latency::total 8408000 # number of ReadSharedReq miss cycles 836system.cpu.l2cache.demand_miss_latency::cpu.inst 24090000 # number of demand (read+write) miss cycles 837system.cpu.l2cache.demand_miss_latency::cpu.data 14328500 # number of demand (read+write) miss cycles 838system.cpu.l2cache.demand_miss_latency::total 38418500 # number of demand (read+write) miss cycles 839system.cpu.l2cache.overall_miss_latency::cpu.inst 24090000 # number of overall miss cycles 840system.cpu.l2cache.overall_miss_latency::cpu.data 14328500 # number of overall miss cycles 841system.cpu.l2cache.overall_miss_latency::total 38418500 # number of overall miss cycles | 841system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles 843system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles 844system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles 845system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles 846system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles 847system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles 848system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles 849system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles 852system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles |
| 842system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 843system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 844system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) 845system.cpu.l2cache.ReadCleanReq_accesses::total 313 # number of ReadCleanReq accesses(hits+misses) 846system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 847system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 848system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses 849system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 858system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 859system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 860system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 861system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 862system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses 863system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 864system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 865system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses | 853system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) 856system.cpu.l2cache.ReadCleanReq_accesses::total 313 # number of ReadCleanReq accesses(hits+misses) 857system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 858system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 859system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses 860system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 869system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 870system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 871system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 872system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 873system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses 874system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 875system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 876system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses |
| 866system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82229.166667 # average ReadExReq miss latency 867system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82229.166667 # average ReadExReq miss latency 868system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77211.538462 # average ReadCleanReq miss latency 869system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77211.538462 # average ReadCleanReq miss latency 870system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83247.524752 # average ReadSharedReq miss latency 871system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83247.524752 # average ReadSharedReq miss latency 872system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency 873system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency 874system.cpu.l2cache.demand_avg_miss_latency::total 79213.402062 # average overall miss latency 875system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency 876system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency 877system.cpu.l2cache.overall_avg_miss_latency::total 79213.402062 # average overall miss latency | 877system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency 878system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency 879system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency 880system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency 881system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency 882system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency 883system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency 884system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency 885system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency 887system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency |
| 878system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 879system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 880system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 882system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 883system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 884system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 885system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 886system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses 887system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses 888system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 889system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses 890system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 891system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 892system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses 893system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 894system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 895system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses | 889system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 890system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 894system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 896system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 897system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses 898system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses 899system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 900system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses 901system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 902system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 903system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses 904system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 905system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 906system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses |
| 896system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200500 # number of ReadExReq MSHR miss cycles 897system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200500 # number of ReadExReq MSHR miss cycles 898system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20970000 # number of ReadCleanReq MSHR miss cycles 899system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20970000 # number of ReadCleanReq MSHR miss cycles 900system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7398000 # number of ReadSharedReq MSHR miss cycles 901system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7398000 # number of ReadSharedReq MSHR miss cycles 902system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20970000 # number of demand (read+write) MSHR miss cycles 903system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12598500 # number of demand (read+write) MSHR miss cycles 904system.cpu.l2cache.demand_mshr_miss_latency::total 33568500 # number of demand (read+write) MSHR miss cycles 905system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20970000 # number of overall MSHR miss cycles 906system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12598500 # number of overall MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::total 33568500 # number of overall MSHR miss cycles | 907system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles 908system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles 909system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles 910system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles 911system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles 912system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles 913system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles 914system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles 915system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles 916system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles 917system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles 918system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles |
| 908system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 909system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 910system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses 911system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses 912system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 913system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 914system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 915system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 916system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses 917system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 918system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 919system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses | 919system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 920system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 921system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses 922system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses 923system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 924system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 925system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 926system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 927system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses 928system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 929system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 930system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses |
| 920system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72229.166667 # average ReadExReq mshr miss latency 921system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72229.166667 # average ReadExReq mshr miss latency 922system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67211.538462 # average ReadCleanReq mshr miss latency 923system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67211.538462 # average ReadCleanReq mshr miss latency 924system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73247.524752 # average ReadSharedReq mshr miss latency 925system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73247.524752 # average ReadSharedReq mshr miss latency 926system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency 928system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency 929system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency 931system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency | 931system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency 932system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency 933system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency 934system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency 935system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency 936system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency 937system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency 938system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency 939system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency 940system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency 941system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency 942system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency |
| 932system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 933system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 934system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 935system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 936system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 937system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 943system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 944system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 945system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 946system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 947system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 948system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 938system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states | 949system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 939system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 941system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 942system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution 943system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution 944system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) 945system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) 946system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) --- 9 unchanged lines hidden (view full) --- 956system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 959system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 960system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 961system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 962system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram 963system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) | 950system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution 955system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) 956system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) 957system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) --- 9 unchanged lines hidden (view full) --- 967system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram 968system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 969system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 970system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 971system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 972system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 973system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram 974system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) |
| 964system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) | 975system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| 965system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) | 976system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) |
| 966system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) | 977system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) |
| 967system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) | 978system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) |
| 968system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) | 979system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) |
| 969system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. 970system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 971system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 972system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 973system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 974system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 980system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. 981system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 982system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 983system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 984system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 985system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 975system.membus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states | 986system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 976system.membus.trans_dist::ReadResp 413 # Transaction distribution 977system.membus.trans_dist::ReadExReq 72 # Transaction distribution 978system.membus.trans_dist::ReadExResp 72 # Transaction distribution 979system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 980system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) 981system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 982system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) 983system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 988system.membus.snoop_fanout::stdev 0 # Request fanout histogram 989system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 990system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram 991system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 992system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 993system.membus.snoop_fanout::min_value 0 # Request fanout histogram 994system.membus.snoop_fanout::max_value 0 # Request fanout histogram 995system.membus.snoop_fanout::total 485 # Request fanout histogram | 987system.membus.trans_dist::ReadResp 413 # Transaction distribution 988system.membus.trans_dist::ReadExReq 72 # Transaction distribution 989system.membus.trans_dist::ReadExResp 72 # Transaction distribution 990system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 991system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) 992system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 993system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) 994system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 999system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1000system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1001system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram 1002system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1003system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1004system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1005system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1006system.membus.snoop_fanout::total 485 # Request fanout histogram |
| 996system.membus.reqLayer0.occupancy 591500 # Layer occupancy (ticks) 997system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) 998system.membus.respLayer1.occupancy 2578750 # Layer occupancy (ticks) 999system.membus.respLayer1.utilization 11.6 # Layer utilization (%) | 1007system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks) 1008system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) 1009system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks) 1010system.membus.respLayer1.utilization 10.8 # Layer utilization (%) |
| 1000 1001---------- End Simulation Statistics ---------- | 1011 1012---------- End Simulation Statistics ---------- |