| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 22019000 # Number of ticks simulated 5final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 22019000 # Number of ticks simulated 5final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 115969 # Simulator instruction rate (inst/s) 8host_op_rate 115940 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 399737091 # Simulator tick rate (ticks/s) 10host_mem_usage 249288 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 117755 # Simulator instruction rate (inst/s) 8host_op_rate 117735 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 405950936 # Simulator tick rate (ticks/s) 10host_mem_usage 294524 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 485 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 244system.physmem_1.preBackEnergy 657000 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 13486815 # Total energy per rank (pJ) 246system.physmem_1.averagePower 851.440341 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 1024500 # Time in different power states 248system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem_1.memoryStateTime::ACT 14308250 # Time in different power states 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 19system.physmem.bytes_read::total 31040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 485 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 657000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 13486815 # Total energy per rank (pJ) 247system.physmem_1.averagePower 851.440341 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 1024500 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 14308250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
|
| 252system.cpu.branchPred.lookups 2849 # Number of BP lookups 253system.cpu.branchPred.condPredicted 1676 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 2197 # Number of BTB lookups 256system.cpu.branchPred.BTBHits 713 # Number of BTB hits 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 258system.cpu.branchPred.BTBHitPct 32.453345 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. --- 31 unchanged lines hidden (view full) --- 291system.cpu.itb.write_misses 0 # DTB write misses 292system.cpu.itb.write_acv 0 # DTB write access violations 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.data_hits 0 # DTB hits 295system.cpu.itb.data_misses 0 # DTB misses 296system.cpu.itb.data_acv 0 # DTB access violations 297system.cpu.itb.data_accesses 0 # DTB accesses 298system.cpu.workload.num_syscalls 17 # Number of system calls | 254system.cpu.branchPred.lookups 2849 # Number of BP lookups 255system.cpu.branchPred.condPredicted 1676 # Number of conditional branches predicted 256system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect 257system.cpu.branchPred.BTBLookups 2197 # Number of BTB lookups 258system.cpu.branchPred.BTBHits 713 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 260system.cpu.branchPred.BTBHitPct 32.453345 # BTB Hit Percentage 261system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. --- 31 unchanged lines hidden (view full) --- 293system.cpu.itb.write_misses 0 # DTB write misses 294system.cpu.itb.write_acv 0 # DTB write access violations 295system.cpu.itb.write_accesses 0 # DTB write accesses 296system.cpu.itb.data_hits 0 # DTB hits 297system.cpu.itb.data_misses 0 # DTB misses 298system.cpu.itb.data_acv 0 # DTB access violations 299system.cpu.itb.data_accesses 0 # DTB accesses 300system.cpu.workload.num_syscalls 17 # Number of system calls |
| 301system.cpu.pwrStateResidencyTicks::ON 22019000 # Cumulative time (in ticks) in various power states |
|
| 299system.cpu.numCycles 44039 # number of cpu cycles simulated 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.fetch.icacheStallCycles 8533 # Number of cycles fetch is stalled on an Icache miss 303system.cpu.fetch.Insts 16533 # Number of instructions fetch has processed 304system.cpu.fetch.Branches 2849 # Number of branches that fetch encountered 305system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken 306system.cpu.fetch.Cycles 5068 # Number of cycles fetch has run and was not squashing or blocked --- 275 unchanged lines hidden (view full) --- 582system.cpu.ipc 0.144985 # IPC: Instructions Per Cycle 583system.cpu.ipc_total 0.144985 # IPC: Total IPC of All Threads 584system.cpu.int_regfile_reads 12924 # number of integer regfile reads 585system.cpu.int_regfile_writes 7434 # number of integer regfile writes 586system.cpu.fp_regfile_reads 8 # number of floating regfile reads 587system.cpu.fp_regfile_writes 2 # number of floating regfile writes 588system.cpu.misc_regfile_reads 1 # number of misc regfile reads 589system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 302system.cpu.numCycles 44039 # number of cpu cycles simulated 303system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 304system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 305system.cpu.fetch.icacheStallCycles 8533 # Number of cycles fetch is stalled on an Icache miss 306system.cpu.fetch.Insts 16533 # Number of instructions fetch has processed 307system.cpu.fetch.Branches 2849 # Number of branches that fetch encountered 308system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken 309system.cpu.fetch.Cycles 5068 # Number of cycles fetch has run and was not squashing or blocked --- 275 unchanged lines hidden (view full) --- 585system.cpu.ipc 0.144985 # IPC: Instructions Per Cycle 586system.cpu.ipc_total 0.144985 # IPC: Total IPC of All Threads 587system.cpu.int_regfile_reads 12924 # number of integer regfile reads 588system.cpu.int_regfile_writes 7434 # number of integer regfile writes 589system.cpu.fp_regfile_reads 8 # number of floating regfile reads 590system.cpu.fp_regfile_writes 2 # number of floating regfile writes 591system.cpu.misc_regfile_reads 1 # number of misc regfile reads 592system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 593system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
|
| 590system.cpu.dcache.tags.replacements 0 # number of replacements 591system.cpu.dcache.tags.tagsinuse 109.409218 # Cycle average of tags in use 592system.cpu.dcache.tags.total_refs 2405 # Total number of references to valid blocks. 593system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. 594system.cpu.dcache.tags.avg_refs 13.901734 # Average number of references to valid blocks. 595system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 596system.cpu.dcache.tags.occ_blocks::cpu.data 109.409218 # Average occupied blocks per requestor 597system.cpu.dcache.tags.occ_percent::cpu.data 0.026711 # Average percentage of cache occupancy 598system.cpu.dcache.tags.occ_percent::total 0.026711 # Average percentage of cache occupancy 599system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 600system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 601system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id 602system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id 603system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses 604system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses | 594system.cpu.dcache.tags.replacements 0 # number of replacements 595system.cpu.dcache.tags.tagsinuse 109.409218 # Cycle average of tags in use 596system.cpu.dcache.tags.total_refs 2405 # Total number of references to valid blocks. 597system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. 598system.cpu.dcache.tags.avg_refs 13.901734 # Average number of references to valid blocks. 599system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 600system.cpu.dcache.tags.occ_blocks::cpu.data 109.409218 # Average occupied blocks per requestor 601system.cpu.dcache.tags.occ_percent::cpu.data 0.026711 # Average percentage of cache occupancy 602system.cpu.dcache.tags.occ_percent::total 0.026711 # Average percentage of cache occupancy 603system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 604system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 605system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id 606system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id 607system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses 608system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses |
| 609system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
|
| 605system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits 606system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits 607system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 608system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 609system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits 610system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits 611system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits 612system.cpu.dcache.overall_hits::total 2405 # number of overall hits --- 78 unchanged lines hidden (view full) --- 691system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83821.782178 # average ReadReq mshr miss latency 692system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83821.782178 # average ReadReq mshr miss latency 693system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79104.166667 # average WriteReq mshr miss latency 694system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79104.166667 # average WriteReq mshr miss latency 695system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 696system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency 697system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 698system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency | 610system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits 611system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits 612system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 613system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 614system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits 615system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits 616system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits 617system.cpu.dcache.overall_hits::total 2405 # number of overall hits --- 78 unchanged lines hidden (view full) --- 696system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83821.782178 # average ReadReq mshr miss latency 697system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83821.782178 # average ReadReq mshr miss latency 698system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79104.166667 # average WriteReq mshr miss latency 699system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79104.166667 # average WriteReq mshr miss latency 700system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 701system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency 702system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 703system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency |
| 704system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
|
| 699system.cpu.icache.tags.replacements 0 # number of replacements 700system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use 701system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks. 702system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. 703system.cpu.icache.tags.avg_refs 5.865815 # Average number of references to valid blocks. 704system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 705system.cpu.icache.tags.occ_blocks::cpu.inst 158.432951 # Average occupied blocks per requestor 706system.cpu.icache.tags.occ_percent::cpu.inst 0.077360 # Average percentage of cache occupancy 707system.cpu.icache.tags.occ_percent::total 0.077360 # Average percentage of cache occupancy 708system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id 709system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id 710system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id 711system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id 712system.cpu.icache.tags.tag_accesses 4899 # Number of tag accesses 713system.cpu.icache.tags.data_accesses 4899 # Number of data accesses | 705system.cpu.icache.tags.replacements 0 # number of replacements 706system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use 707system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks. 708system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. 709system.cpu.icache.tags.avg_refs 5.865815 # Average number of references to valid blocks. 710system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 711system.cpu.icache.tags.occ_blocks::cpu.inst 158.432951 # Average occupied blocks per requestor 712system.cpu.icache.tags.occ_percent::cpu.inst 0.077360 # Average percentage of cache occupancy 713system.cpu.icache.tags.occ_percent::total 0.077360 # Average percentage of cache occupancy 714system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id 715system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id 716system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id 717system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id 718system.cpu.icache.tags.tag_accesses 4899 # Number of tag accesses 719system.cpu.icache.tags.data_accesses 4899 # Number of data accesses |
| 720system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
|
| 714system.cpu.icache.ReadReq_hits::cpu.inst 1836 # number of ReadReq hits 715system.cpu.icache.ReadReq_hits::total 1836 # number of ReadReq hits 716system.cpu.icache.demand_hits::cpu.inst 1836 # number of demand (read+write) hits 717system.cpu.icache.demand_hits::total 1836 # number of demand (read+write) hits 718system.cpu.icache.overall_hits::cpu.inst 1836 # number of overall hits 719system.cpu.icache.overall_hits::total 1836 # number of overall hits 720system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses 721system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 778system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for overall accesses 779system.cpu.icache.overall_mshr_miss_rate::total 0.136502 # mshr miss rate for overall accesses 780system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78180.511182 # average ReadReq mshr miss latency 781system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78180.511182 # average ReadReq mshr miss latency 782system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 783system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency 784system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 785system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency | 721system.cpu.icache.ReadReq_hits::cpu.inst 1836 # number of ReadReq hits 722system.cpu.icache.ReadReq_hits::total 1836 # number of ReadReq hits 723system.cpu.icache.demand_hits::cpu.inst 1836 # number of demand (read+write) hits 724system.cpu.icache.demand_hits::total 1836 # number of demand (read+write) hits 725system.cpu.icache.overall_hits::cpu.inst 1836 # number of overall hits 726system.cpu.icache.overall_hits::total 1836 # number of overall hits 727system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses 728system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 785system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for overall accesses 786system.cpu.icache.overall_mshr_miss_rate::total 0.136502 # mshr miss rate for overall accesses 787system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78180.511182 # average ReadReq mshr miss latency 788system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78180.511182 # average ReadReq mshr miss latency 789system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 790system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency 791system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 792system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency |
| 793system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
|
| 786system.cpu.l2cache.tags.replacements 0 # number of replacements 787system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use 788system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 789system.cpu.l2cache.tags.sampled_refs 413 # Sample count of references to valid blocks. 790system.cpu.l2cache.tags.avg_refs 0.002421 # Average number of references to valid blocks. 791system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 792system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.475596 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_blocks::cpu.data 62.519281 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy 795system.cpu.l2cache.tags.occ_percent::cpu.data 0.001908 # Average percentage of cache occupancy 796system.cpu.l2cache.tags.occ_percent::total 0.006744 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id 798system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id 799system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id 800system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012604 # Percentage of cache occupancy per task id 801system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses 802system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses | 794system.cpu.l2cache.tags.replacements 0 # number of replacements 795system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use 796system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 797system.cpu.l2cache.tags.sampled_refs 413 # Sample count of references to valid blocks. 798system.cpu.l2cache.tags.avg_refs 0.002421 # Average number of references to valid blocks. 799system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 800system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.475596 # Average occupied blocks per requestor 801system.cpu.l2cache.tags.occ_blocks::cpu.data 62.519281 # Average occupied blocks per requestor 802system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy 803system.cpu.l2cache.tags.occ_percent::cpu.data 0.001908 # Average percentage of cache occupancy 804system.cpu.l2cache.tags.occ_percent::total 0.006744 # Average percentage of cache occupancy 805system.cpu.l2cache.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id 806system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id 807system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id 808system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012604 # Percentage of cache occupancy per task id 809system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses 810system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses |
| 811system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
|
| 803system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 804system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 805system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 806system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 807system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 808system.cpu.l2cache.overall_hits::total 1 # number of overall hits 809system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 810system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency 922system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency 923system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 924system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 925system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 926system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 927system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 928system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 812system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 813system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 814system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 815system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 816system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 817system.cpu.l2cache.overall_hits::total 1 # number of overall hits 818system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 819system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 930system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency 931system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency 932system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 933system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 934system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 935system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 936system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 937system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 938system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
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| 929system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution 934system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) 935system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) 936system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 950system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram 952system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) 953system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 954system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) 955system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 956system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 957system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) | 939system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 941system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 942system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution 943system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution 944system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) 945system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) 946system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 960system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 961system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram 962system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) 963system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 964system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) 965system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 966system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 967system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) |
| 968system.membus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states |
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| 958system.membus.trans_dist::ReadResp 413 # Transaction distribution 959system.membus.trans_dist::ReadExReq 72 # Transaction distribution 960system.membus.trans_dist::ReadExResp 72 # Transaction distribution 961system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 962system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) 963system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 964system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) 965system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 969system.membus.trans_dist::ReadResp 413 # Transaction distribution 970system.membus.trans_dist::ReadExReq 72 # Transaction distribution 971system.membus.trans_dist::ReadExResp 72 # Transaction distribution 972system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 973system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) 974system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 975system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) 976system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |