| stats.txt (11440:76b5639162af) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 22019000 # Number of ticks simulated 5final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 22019000 # Number of ticks simulated 5final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 66596 # Simulator instruction rate (inst/s) 8host_op_rate 66584 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 229093695 # Simulator tick rate (ticks/s) 10host_mem_usage 228860 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host | 7host_inst_rate 140516 # Simulator instruction rate (inst/s) 8host_op_rate 140486 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 484379589 # Simulator tick rate (ticks/s) 10host_mem_usage 253664 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory --- 631 unchanged lines hidden (view full) --- 651system.cpu.dcache.overall_avg_miss_latency::cpu.data 67742.068646 # average overall miss latency 652system.cpu.dcache.overall_avg_miss_latency::total 67742.068646 # average overall miss latency 653system.cpu.dcache.blocked_cycles::no_mshrs 2423 # number of cycles access was blocked 654system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked 656system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.348837 # average number of cycles each access was blocked 658system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory --- 631 unchanged lines hidden (view full) --- 651system.cpu.dcache.overall_avg_miss_latency::cpu.data 67742.068646 # average overall miss latency 652system.cpu.dcache.overall_avg_miss_latency::total 67742.068646 # average overall miss latency 653system.cpu.dcache.blocked_cycles::no_mshrs 2423 # number of cycles access was blocked 654system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked 656system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.348837 # average number of cycles each access was blocked 658system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 659system.cpu.dcache.fast_writes 0 # number of fast writes performed 660system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 661system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 662system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 663system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 664system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 665system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits 666system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits 667system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits 668system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 693system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83821.782178 # average ReadReq mshr miss latency 694system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83821.782178 # average ReadReq mshr miss latency 695system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79104.166667 # average WriteReq mshr miss latency 696system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79104.166667 # average WriteReq mshr miss latency 697system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 698system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency 699system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 700system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency | 659system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 660system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 661system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 662system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 663system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits 664system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits 665system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits 666system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 691system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83821.782178 # average ReadReq mshr miss latency 692system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83821.782178 # average ReadReq mshr miss latency 693system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79104.166667 # average WriteReq mshr miss latency 694system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79104.166667 # average WriteReq mshr miss latency 695system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 696system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency 697system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 698system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency |
| 701system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 702system.cpu.icache.tags.replacements 0 # number of replacements 703system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use 704system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks. 705system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. 706system.cpu.icache.tags.avg_refs 5.865815 # Average number of references to valid blocks. 707system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 708system.cpu.icache.tags.occ_blocks::cpu.inst 158.432951 # Average occupied blocks per requestor 709system.cpu.icache.tags.occ_percent::cpu.inst 0.077360 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 751system.cpu.icache.overall_avg_miss_latency::cpu.inst 71856.673961 # average overall miss latency 752system.cpu.icache.overall_avg_miss_latency::total 71856.673961 # average overall miss latency 753system.cpu.icache.blocked_cycles::no_mshrs 54 # number of cycles access was blocked 754system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 756system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu.icache.avg_blocked_cycles::no_mshrs 54 # average number of cycles each access was blocked 758system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 699system.cpu.icache.tags.replacements 0 # number of replacements 700system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use 701system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks. 702system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. 703system.cpu.icache.tags.avg_refs 5.865815 # Average number of references to valid blocks. 704system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 705system.cpu.icache.tags.occ_blocks::cpu.inst 158.432951 # Average occupied blocks per requestor 706system.cpu.icache.tags.occ_percent::cpu.inst 0.077360 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 748system.cpu.icache.overall_avg_miss_latency::cpu.inst 71856.673961 # average overall miss latency 749system.cpu.icache.overall_avg_miss_latency::total 71856.673961 # average overall miss latency 750system.cpu.icache.blocked_cycles::no_mshrs 54 # number of cycles access was blocked 751system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 753system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu.icache.avg_blocked_cycles::no_mshrs 54 # average number of cycles each access was blocked 755system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 759system.cpu.icache.fast_writes 0 # number of fast writes performed 760system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 761system.cpu.icache.ReadReq_mshr_hits::cpu.inst 144 # number of ReadReq MSHR hits 762system.cpu.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits 763system.cpu.icache.demand_mshr_hits::cpu.inst 144 # number of demand (read+write) MSHR hits 764system.cpu.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits 765system.cpu.icache.overall_mshr_hits::cpu.inst 144 # number of overall MSHR hits 766system.cpu.icache.overall_mshr_hits::total 144 # number of overall MSHR hits 767system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 768system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses --- 14 unchanged lines hidden (view full) --- 783system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for overall accesses 784system.cpu.icache.overall_mshr_miss_rate::total 0.136502 # mshr miss rate for overall accesses 785system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78180.511182 # average ReadReq mshr miss latency 786system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78180.511182 # average ReadReq mshr miss latency 787system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 788system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency 789system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 790system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency | 756system.cpu.icache.ReadReq_mshr_hits::cpu.inst 144 # number of ReadReq MSHR hits 757system.cpu.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits 758system.cpu.icache.demand_mshr_hits::cpu.inst 144 # number of demand (read+write) MSHR hits 759system.cpu.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits 760system.cpu.icache.overall_mshr_hits::cpu.inst 144 # number of overall MSHR hits 761system.cpu.icache.overall_mshr_hits::total 144 # number of overall MSHR hits 762system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 763system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses --- 14 unchanged lines hidden (view full) --- 778system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for overall accesses 779system.cpu.icache.overall_mshr_miss_rate::total 0.136502 # mshr miss rate for overall accesses 780system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78180.511182 # average ReadReq mshr miss latency 781system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78180.511182 # average ReadReq mshr miss latency 782system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 783system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency 784system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 785system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency |
| 791system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 792system.cpu.l2cache.tags.replacements 0 # number of replacements 793system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use 794system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 795system.cpu.l2cache.tags.sampled_refs 413 # Sample count of references to valid blocks. 796system.cpu.l2cache.tags.avg_refs 0.002421 # Average number of references to valid blocks. 797system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 798system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.475596 # Average occupied blocks per requestor 799system.cpu.l2cache.tags.occ_blocks::cpu.data 62.519281 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 873system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80291.907514 # average overall miss latency 874system.cpu.l2cache.overall_avg_miss_latency::total 78098.969072 # average overall miss latency 875system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 876system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 877system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 878system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 879system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 880system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 786system.cpu.l2cache.tags.replacements 0 # number of replacements 787system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use 788system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 789system.cpu.l2cache.tags.sampled_refs 413 # Sample count of references to valid blocks. 790system.cpu.l2cache.tags.avg_refs 0.002421 # Average number of references to valid blocks. 791system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 792system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.475596 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_blocks::cpu.data 62.519281 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 867system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80291.907514 # average overall miss latency 868system.cpu.l2cache.overall_avg_miss_latency::total 78098.969072 # average overall miss latency 869system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 870system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 871system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 872system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 873system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 874system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 881system.cpu.l2cache.fast_writes 0 # number of fast writes performed 882system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 883system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 884system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 885system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses 886system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses 887system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 888system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses 889system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 890system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 923system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72237.623762 # average ReadSharedReq mshr miss latency 924system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72237.623762 # average ReadSharedReq mshr miss latency 925system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency 926system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency 928system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency 929system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency | 875system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 876system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 877system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses 878system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses 879system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 880system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses 881system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 882system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 915system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72237.623762 # average ReadSharedReq mshr miss latency 916system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72237.623762 # average ReadSharedReq mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency 919system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency 922system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency |
| 931system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 932system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 933system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 934system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 935system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 936system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 937system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 938system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution 939system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution --- 52 unchanged lines hidden --- | 923system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 924system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 925system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 926system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 927system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 928system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 929system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution --- 52 unchanged lines hidden --- |