| stats.txt (11390:f40859930028) | stats.txt (11440:76b5639162af) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated |
| 4sim_ticks 21972500 # Number of ticks simulated 5final_tick 21972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 22019000 # Number of ticks simulated 5final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 66596 # Simulator instruction rate (inst/s) 8host_op_rate 66584 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 229093695 # Simulator tick rate (ticks/s) 10host_mem_usage 228860 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 66596 # Simulator instruction rate (inst/s) 8host_op_rate 66584 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 229093695 # Simulator tick rate (ticks/s) 10host_mem_usage 228860 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::total 30912 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory | 18system.physmem.bytes_read::total 31040 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory |
| 22system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory | 22system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::total 483 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 902946865 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 503902606 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1406849471 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 902946865 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 902946865 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 902946865 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 503902606 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1406849471 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 483 # Number of read requests accepted | 23system.physmem.num_reads::total 485 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 906853172 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 502838458 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1409691630 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 906853172 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 906853172 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 906853172 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 502838458 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1409691630 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 485 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 483 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 30912 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 30912 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 44system.physmem.perBankRdBursts::0 68 # Per bank write bursts | 44system.physmem.perBankRdBursts::0 69 # Per bank write bursts |
| 45system.physmem.perBankRdBursts::1 32 # Per bank write bursts | 45system.physmem.perBankRdBursts::1 32 # Per bank write bursts |
| 46system.physmem.perBankRdBursts::2 32 # Per bank write bursts | 46system.physmem.perBankRdBursts::2 33 # Per bank write bursts |
| 47system.physmem.perBankRdBursts::3 47 # Per bank write bursts 48system.physmem.perBankRdBursts::4 42 # Per bank write bursts 49system.physmem.perBankRdBursts::5 20 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1 # Per bank write bursts 51system.physmem.perBankRdBursts::7 3 # Per bank write bursts 52system.physmem.perBankRdBursts::8 0 # Per bank write bursts 53system.physmem.perBankRdBursts::9 1 # Per bank write bursts 54system.physmem.perBankRdBursts::10 22 # Per bank write bursts --- 15 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 47system.physmem.perBankRdBursts::3 47 # Per bank write bursts 48system.physmem.perBankRdBursts::4 42 # Per bank write bursts 49system.physmem.perBankRdBursts::5 20 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1 # Per bank write bursts 51system.physmem.perBankRdBursts::7 3 # Per bank write bursts 52system.physmem.perBankRdBursts::8 0 # Per bank write bursts 53system.physmem.perBankRdBursts::9 1 # Per bank write bursts 54system.physmem.perBankRdBursts::10 22 # Per bank write bursts --- 15 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 21835000 # Total gap between requests | 78system.physmem.totGap 21881000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 483 # Read request sizes (log2) | 85system.physmem.readPktSize::6 485 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see |
| 94system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see |
| 97system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation | 97system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation |
| 190system.physmem.bytesPerActivate::mean 352 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 228.419611 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 324.406987 # Bytes accessed per row activation | 190system.physmem.bytesPerActivate::mean 353.684211 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 230.878571 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 321.867393 # Bytes accessed per row activation |
| 193system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation | 193system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation |
| 194system.physmem.bytesPerActivate::128-255 20 26.32% 50.00% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 9 11.84% 61.84% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 11 14.47% 76.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.26% 81.58% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 1.32% 82.89% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 3.95% 86.84% # Bytes accessed per row activation | 194system.physmem.bytesPerActivate::128-255 19 25.00% 48.68% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 10 13.16% 61.84% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 10 13.16% 75.00% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 5 6.58% 81.58% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.63% 84.21% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 2.63% 86.84% # Bytes accessed per row activation |
| 200system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation | 200system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation |
| 202system.physmem.totQLat 3936250 # Total ticks spent queuing 203system.physmem.totMemAccLat 12992500 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 2415000 # Total ticks spent in databus transfers 205system.physmem.avgQLat 8149.59 # Average queueing delay per DRAM burst | 202system.physmem.totQLat 4444750 # Total ticks spent queuing 203system.physmem.totMemAccLat 13538500 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers 205system.physmem.avgQLat 9164.43 # Average queueing delay per DRAM burst |
| 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 207system.physmem.avgMemAccLat 26899.59 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 1406.85 # Average DRAM read bandwidth in MiByte/s | 207system.physmem.avgMemAccLat 27914.43 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 1409.69 # Average DRAM read bandwidth in MiByte/s |
| 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 210system.physmem.avgRdBWSys 1406.85 # Average system read bandwidth in MiByte/s | 210system.physmem.avgRdBWSys 1409.69 # Average system read bandwidth in MiByte/s |
| 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 213system.physmem.busUtil 10.99 # Data bus utilization in percentage 214system.physmem.busUtilRead 10.99 # Data bus utilization in percentage for reads | 213system.physmem.busUtil 11.01 # Data bus utilization in percentage 214system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads |
| 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 216system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing | 216system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing |
| 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 218system.physmem.readRowHits 392 # Number of row buffer hits during reads | 218system.physmem.readRowHits 394 # Number of row buffer hits during reads |
| 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 220system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads | 220system.physmem.readRowHitRate 81.24 # Row buffer hit rate for reads |
| 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 222system.physmem.avgGap 45207.04 # Average gap between requests 223system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined | 222system.physmem.avgGap 45115.46 # Average gap between requests 223system.physmem.pageHitRate 81.24 # Row buffer hit rate, read and write combined |
| 224system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) 225system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) | 224system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) 225system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) |
| 226system.physmem_0.readEnergy 1638000 # Energy for read commands per rank (pJ) | 226system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) |
| 227system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 229system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) 230system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) | 227system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 229system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) 230system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) |
| 231system.physmem_0.totalEnergy 13783005 # Total energy per rank (pJ) 232system.physmem_0.averagePower 870.551397 # Core power per rank (mW) 233system.physmem_0.memoryStateTime::IDLE 281750 # Time in different power states | 231system.physmem_0.totalEnergy 13798605 # Total energy per rank (pJ) 232system.physmem_0.averagePower 871.536712 # Core power per rank (mW) 233system.physmem_0.memoryStateTime::IDLE 297750 # Time in different power states |
| 234system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 235system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 236system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states 237system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ) 239system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ) | 234system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 235system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 236system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states 237system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ) 239system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ) |
| 240system.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ) | 240system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ) |
| 241system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 241system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 243system.physmem_1.actBackEnergy 10134315 # Energy for active background per rank (pJ) 244system.physmem_1.preBackEnergy 609750 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 13503900 # Total energy per rank (pJ) 246system.physmem_1.averagePower 852.922785 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 945500 # Time in different power states | 243system.physmem_1.actBackEnergy 10085580 # Energy for active background per rank (pJ) 244system.physmem_1.preBackEnergy 657000 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 13486815 # Total energy per rank (pJ) 246system.physmem_1.averagePower 851.440341 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 1024500 # Time in different power states |
| 248system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 248system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 250system.physmem_1.memoryStateTime::ACT 14380750 # Time in different power states | 250system.physmem_1.memoryStateTime::ACT 14308250 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 252system.cpu.branchPred.lookups 2618 # Number of BP lookups 253system.cpu.branchPred.condPredicted 1561 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 431 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 2031 # Number of BTB lookups 256system.cpu.branchPred.BTBHits 757 # Number of BTB hits | 252system.cpu.branchPred.lookups 2849 # Number of BP lookups 253system.cpu.branchPred.condPredicted 1676 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 2197 # Number of BTB lookups 256system.cpu.branchPred.BTBHits 713 # Number of BTB hits |
| 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 258system.cpu.branchPred.BTBHitPct 37.272280 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 391 # Number of times the RAS was used to get a target. 260system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions. | 258system.cpu.branchPred.BTBHitPct 32.453345 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. 260system.cpu.branchPred.RASInCorrect 41 # Number of incorrect RAS predictions. 261system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. 262system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. 263system.cpu.branchPred.indirectMisses 436 # Number of indirect misses. 264system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. |
| 261system.cpu_clk_domain.clock 500 # Clock period in ticks 262system.cpu.dtb.fetch_hits 0 # ITB hits 263system.cpu.dtb.fetch_misses 0 # ITB misses 264system.cpu.dtb.fetch_acv 0 # ITB acv 265system.cpu.dtb.fetch_accesses 0 # ITB accesses | 265system.cpu_clk_domain.clock 500 # Clock period in ticks 266system.cpu.dtb.fetch_hits 0 # ITB hits 267system.cpu.dtb.fetch_misses 0 # ITB misses 268system.cpu.dtb.fetch_acv 0 # ITB acv 269system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 266system.cpu.dtb.read_hits 2066 # DTB read hits 267system.cpu.dtb.read_misses 43 # DTB read misses | 270system.cpu.dtb.read_hits 2261 # DTB read hits 271system.cpu.dtb.read_misses 48 # DTB read misses |
| 268system.cpu.dtb.read_acv 0 # DTB read access violations | 272system.cpu.dtb.read_acv 0 # DTB read access violations |
| 269system.cpu.dtb.read_accesses 2109 # DTB read accesses 270system.cpu.dtb.write_hits 1060 # DTB write hits | 273system.cpu.dtb.read_accesses 2309 # DTB read accesses 274system.cpu.dtb.write_hits 1039 # DTB write hits |
| 271system.cpu.dtb.write_misses 28 # DTB write misses 272system.cpu.dtb.write_acv 0 # DTB write access violations | 275system.cpu.dtb.write_misses 28 # DTB write misses 276system.cpu.dtb.write_acv 0 # DTB write access violations |
| 273system.cpu.dtb.write_accesses 1088 # DTB write accesses 274system.cpu.dtb.data_hits 3126 # DTB hits 275system.cpu.dtb.data_misses 71 # DTB misses | 277system.cpu.dtb.write_accesses 1067 # DTB write accesses 278system.cpu.dtb.data_hits 3300 # DTB hits 279system.cpu.dtb.data_misses 76 # DTB misses |
| 276system.cpu.dtb.data_acv 0 # DTB access violations | 280system.cpu.dtb.data_acv 0 # DTB access violations |
| 277system.cpu.dtb.data_accesses 3197 # DTB accesses 278system.cpu.itb.fetch_hits 2136 # ITB hits 279system.cpu.itb.fetch_misses 29 # ITB misses | 281system.cpu.dtb.data_accesses 3376 # DTB accesses 282system.cpu.itb.fetch_hits 2293 # ITB hits 283system.cpu.itb.fetch_misses 27 # ITB misses |
| 280system.cpu.itb.fetch_acv 0 # ITB acv | 284system.cpu.itb.fetch_acv 0 # ITB acv |
| 281system.cpu.itb.fetch_accesses 2165 # ITB accesses | 285system.cpu.itb.fetch_accesses 2320 # ITB accesses |
| 282system.cpu.itb.read_hits 0 # DTB read hits 283system.cpu.itb.read_misses 0 # DTB read misses 284system.cpu.itb.read_acv 0 # DTB read access violations 285system.cpu.itb.read_accesses 0 # DTB read accesses 286system.cpu.itb.write_hits 0 # DTB write hits 287system.cpu.itb.write_misses 0 # DTB write misses 288system.cpu.itb.write_acv 0 # DTB write access violations 289system.cpu.itb.write_accesses 0 # DTB write accesses 290system.cpu.itb.data_hits 0 # DTB hits 291system.cpu.itb.data_misses 0 # DTB misses 292system.cpu.itb.data_acv 0 # DTB access violations 293system.cpu.itb.data_accesses 0 # DTB accesses 294system.cpu.workload.num_syscalls 17 # Number of system calls | 286system.cpu.itb.read_hits 0 # DTB read hits 287system.cpu.itb.read_misses 0 # DTB read misses 288system.cpu.itb.read_acv 0 # DTB read access violations 289system.cpu.itb.read_accesses 0 # DTB read accesses 290system.cpu.itb.write_hits 0 # DTB write hits 291system.cpu.itb.write_misses 0 # DTB write misses 292system.cpu.itb.write_acv 0 # DTB write access violations 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.data_hits 0 # DTB hits 295system.cpu.itb.data_misses 0 # DTB misses 296system.cpu.itb.data_acv 0 # DTB access violations 297system.cpu.itb.data_accesses 0 # DTB accesses 298system.cpu.workload.num_syscalls 17 # Number of system calls |
| 295system.cpu.numCycles 43946 # number of cpu cycles simulated | 299system.cpu.numCycles 44039 # number of cpu cycles simulated |
| 296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 298system.cpu.fetch.icacheStallCycles 8425 # Number of cycles fetch is stalled on an Icache miss 299system.cpu.fetch.Insts 15219 # Number of instructions fetch has processed 300system.cpu.fetch.Branches 2618 # Number of branches that fetch encountered 301system.cpu.fetch.predictedBranches 1148 # Number of branches that fetch has predicted taken 302system.cpu.fetch.Cycles 4748 # Number of cycles fetch has run and was not squashing or blocked 303system.cpu.fetch.SquashCycles 944 # Number of cycles fetch has spent squashing 304system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 305system.cpu.fetch.PendingTrapStallCycles 705 # Number of stall cycles due to pending traps 306system.cpu.fetch.CacheLines 2136 # Number of cache lines fetched 307system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed 308system.cpu.fetch.rateDist::samples 14373 # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::mean 1.058860 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::stdev 2.441925 # Number of instructions fetched each cycle (Total) | 302system.cpu.fetch.icacheStallCycles 8533 # Number of cycles fetch is stalled on an Icache miss 303system.cpu.fetch.Insts 16533 # Number of instructions fetch has processed 304system.cpu.fetch.Branches 2849 # Number of branches that fetch encountered 305system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken 306system.cpu.fetch.Cycles 5068 # Number of cycles fetch has run and was not squashing or blocked 307system.cpu.fetch.SquashCycles 1044 # Number of cycles fetch has spent squashing 308system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 309system.cpu.fetch.PendingTrapStallCycles 654 # Number of stall cycles due to pending traps 310system.cpu.fetch.CacheLines 2293 # Number of cache lines fetched 311system.cpu.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed 312system.cpu.fetch.rateDist::samples 14799 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::mean 1.117170 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::stdev 2.500450 # Number of instructions fetched each cycle (Total) |
| 311system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 315system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 312system.cpu.fetch.rateDist::0 11578 80.55% 80.55% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::1 318 2.21% 82.77% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::2 240 1.67% 84.44% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::3 228 1.59% 86.02% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::4 264 1.84% 87.86% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::5 210 1.46% 89.32% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::6 253 1.76% 91.08% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::7 143 0.99% 92.08% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::8 1139 7.92% 100.00% # Number of instructions fetched each cycle (Total) | 316system.cpu.fetch.rateDist::0 11815 79.84% 79.84% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::1 299 2.02% 81.86% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::2 232 1.57% 83.42% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::3 256 1.73% 85.15% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::4 292 1.97% 87.13% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::5 232 1.57% 88.70% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::6 283 1.91% 90.61% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::7 144 0.97% 91.58% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::8 1246 8.42% 100.00% # Number of instructions fetched each cycle (Total) |
| 321system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 325system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 324system.cpu.fetch.rateDist::total 14373 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.branchRate 0.059573 # Number of branch fetches per cycle 326system.cpu.fetch.rate 0.346311 # Number of inst fetches per cycle 327system.cpu.decode.IdleCycles 8351 # Number of cycles decode is idle 328system.cpu.decode.BlockedCycles 3116 # Number of cycles decode is blocked 329system.cpu.decode.RunCycles 2327 # Number of cycles decode is running 330system.cpu.decode.UnblockCycles 180 # Number of cycles decode is unblocking 331system.cpu.decode.SquashCycles 399 # Number of cycles decode is squashing 332system.cpu.decode.BranchResolved 208 # Number of times decode resolved a branch 333system.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction 334system.cpu.decode.DecodedInsts 13836 # Number of instructions handled by decode 335system.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode 336system.cpu.rename.SquashCycles 399 # Number of cycles rename is squashing 337system.cpu.rename.IdleCycles 8502 # Number of cycles rename is idle 338system.cpu.rename.BlockCycles 1476 # Number of cycles rename is blocking 339system.cpu.rename.serializeStallCycles 647 # count of cycles rename stalled for serializing inst 340system.cpu.rename.RunCycles 2338 # Number of cycles rename is running 341system.cpu.rename.UnblockCycles 1011 # Number of cycles rename is unblocking 342system.cpu.rename.RenamedInsts 13352 # Number of instructions processed by rename 343system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 344system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full 345system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full | 328system.cpu.fetch.rateDist::total 14799 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.branchRate 0.064693 # Number of branch fetches per cycle 330system.cpu.fetch.rate 0.375417 # Number of inst fetches per cycle 331system.cpu.decode.IdleCycles 8370 # Number of cycles decode is idle 332system.cpu.decode.BlockedCycles 3320 # Number of cycles decode is blocked 333system.cpu.decode.RunCycles 2446 # Number of cycles decode is running 334system.cpu.decode.UnblockCycles 215 # Number of cycles decode is unblocking 335system.cpu.decode.SquashCycles 448 # Number of cycles decode is squashing 336system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch 337system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction 338system.cpu.decode.DecodedInsts 14994 # Number of instructions handled by decode 339system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode 340system.cpu.rename.SquashCycles 448 # Number of cycles rename is squashing 341system.cpu.rename.IdleCycles 8529 # Number of cycles rename is idle 342system.cpu.rename.BlockCycles 1727 # Number of cycles rename is blocking 343system.cpu.rename.serializeStallCycles 614 # count of cycles rename stalled for serializing inst 344system.cpu.rename.RunCycles 2478 # Number of cycles rename is running 345system.cpu.rename.UnblockCycles 1003 # Number of cycles rename is unblocking 346system.cpu.rename.RenamedInsts 14444 # Number of instructions processed by rename 347system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 348system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 349system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full |
| 346system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full | 350system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full |
| 347system.cpu.rename.RenamedOperands 10012 # Number of destination operands rename has renamed 348system.cpu.rename.RenameLookups 16699 # Number of register rename lookups that rename has made 349system.cpu.rename.int_rename_lookups 16690 # Number of integer rename lookups | 351system.cpu.rename.RenamedOperands 10925 # Number of destination operands rename has renamed 352system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made 353system.cpu.rename.int_rename_lookups 17884 # Number of integer rename lookups |
| 350system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 351system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed | 354system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 355system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed |
| 352system.cpu.rename.UndoneMaps 5435 # Number of HB maps that are undone due to squashing 353system.cpu.rename.serializingInsts 32 # count of serializing insts renamed 354system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed 355system.cpu.rename.skidInsts 599 # count of insts added to the skid buffer 356system.cpu.memDep0.insertedLoads 2560 # Number of loads inserted to the mem dependence unit. 357system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. 358system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 359system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 360system.cpu.iq.iqInstsAdded 12265 # Number of instructions added to the IQ (excludes non-spec) 361system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ 362system.cpu.iq.iqInstsIssued 10237 # Number of instructions issued 363system.cpu.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued 364system.cpu.iq.iqSquashedInstsExamined 5909 # Number of squashed instructions iterated over during squash; mainly for profiling 365system.cpu.iq.iqSquashedOperandsExamined 3249 # Number of squashed operands that are examined and possibly removed from graph 366system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed 367system.cpu.iq.issued_per_cycle::samples 14373 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::mean 0.712238 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::stdev 1.437631 # Number of insts issued each cycle | 356system.cpu.rename.UndoneMaps 6348 # Number of HB maps that are undone due to squashing 357system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 358system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 359system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer 360system.cpu.memDep0.insertedLoads 2839 # Number of loads inserted to the mem dependence unit. 361system.cpu.memDep0.insertedStores 1293 # Number of stores inserted to the mem dependence unit. 362system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. 363system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. 364system.cpu.iq.iqInstsAdded 13053 # Number of instructions added to the IQ (excludes non-spec) 365system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ 366system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued 367system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued 368system.cpu.iq.iqSquashedInstsExamined 6694 # Number of squashed instructions iterated over during squash; mainly for profiling 369system.cpu.iq.iqSquashedOperandsExamined 3672 # Number of squashed operands that are examined and possibly removed from graph 370system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed 371system.cpu.iq.issued_per_cycle::samples 14799 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::mean 0.728157 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::stdev 1.465404 # Number of insts issued each cycle |
| 370system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 374system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 371system.cpu.iq.issued_per_cycle::0 10470 72.84% 72.84% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::1 1281 8.91% 81.76% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::2 885 6.16% 87.91% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::3 672 4.68% 92.59% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::4 490 3.41% 96.00% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::5 330 2.30% 98.30% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::6 178 1.24% 99.53% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle | 375system.cpu.iq.issued_per_cycle::0 10757 72.69% 72.69% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::1 1297 8.76% 81.45% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::2 917 6.20% 87.65% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::3 680 4.59% 92.24% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::4 523 3.53% 95.78% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::5 348 2.35% 98.13% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::6 194 1.31% 99.44% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::7 55 0.37% 99.81% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle |
| 380system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 384system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 383system.cpu.iq.issued_per_cycle::total 14373 # Number of insts issued each cycle | 387system.cpu.iq.issued_per_cycle::total 14799 # Number of insts issued each cycle |
| 384system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 388system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 385system.cpu.iq.fu_full::IntAlu 20 14.93% 14.93% # attempts to use FU when none available 386system.cpu.iq.fu_full::IntMult 0 0.00% 14.93% # attempts to use FU when none available 387system.cpu.iq.fu_full::IntDiv 0 0.00% 14.93% # attempts to use FU when none available 388system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.93% # attempts to use FU when none available 389system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.93% # attempts to use FU when none available 390system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.93% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatMult 0 0.00% 14.93% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.93% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.93% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.93% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.93% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.93% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.93% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.93% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.93% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdMult 0 0.00% 14.93% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.93% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdShift 0 0.00% 14.93% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.93% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.93% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.93% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.93% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.93% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.93% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.93% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.93% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.93% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.93% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.93% # attempts to use FU when none available 414system.cpu.iq.fu_full::MemRead 73 54.48% 69.40% # attempts to use FU when none available 415system.cpu.iq.fu_full::MemWrite 41 30.60% 100.00% # attempts to use FU when none available | 389system.cpu.iq.fu_full::IntAlu 19 13.77% 13.77% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntMult 0 0.00% 13.77% # attempts to use FU when none available 391system.cpu.iq.fu_full::IntDiv 0 0.00% 13.77% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.77% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available 418system.cpu.iq.fu_full::MemRead 82 59.42% 73.19% # attempts to use FU when none available 419system.cpu.iq.fu_full::MemWrite 37 26.81% 100.00% # attempts to use FU when none available |
| 416system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 418system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued | 420system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 421system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 422system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| 419system.cpu.iq.FU_type_0::IntAlu 6864 67.05% 67.07% # Type of FU issued 420system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.08% # Type of FU issued 421system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.08% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.10% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.10% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued 448system.cpu.iq.FU_type_0::MemRead 2247 21.95% 89.05% # Type of FU issued 449system.cpu.iq.FU_type_0::MemWrite 1121 10.95% 100.00% # Type of FU issued | 423system.cpu.iq.FU_type_0::IntAlu 7177 66.60% 66.62% # Type of FU issued 424system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.63% # Type of FU issued 425system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.63% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.65% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.65% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.65% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.65% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.65% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.65% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.65% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.65% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.65% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.65% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.65% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.65% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.65% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.65% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.65% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.65% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.65% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.65% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.65% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.65% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.65% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.65% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.65% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.65% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.65% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.65% # Type of FU issued 452system.cpu.iq.FU_type_0::MemRead 2482 23.03% 89.68% # Type of FU issued 453system.cpu.iq.FU_type_0::MemWrite 1112 10.32% 100.00% # Type of FU issued |
| 450system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 451system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 454system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 455system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 452system.cpu.iq.FU_type_0::total 10237 # Type of FU issued 453system.cpu.iq.rate 0.232945 # Inst issue rate 454system.cpu.iq.fu_busy_cnt 134 # FU busy when requested 455system.cpu.iq.fu_busy_rate 0.013090 # FU busy rate (busy events/executed inst) 456system.cpu.iq.int_inst_queue_reads 34976 # Number of integer instruction queue reads 457system.cpu.iq.int_inst_queue_writes 18212 # Number of integer instruction queue writes 458system.cpu.iq.int_inst_queue_wakeup_accesses 9377 # Number of integer instruction queue wakeup accesses | 456system.cpu.iq.FU_type_0::total 10776 # Type of FU issued 457system.cpu.iq.rate 0.244692 # Inst issue rate 458system.cpu.iq.fu_busy_cnt 138 # FU busy when requested 459system.cpu.iq.fu_busy_rate 0.012806 # FU busy rate (busy events/executed inst) 460system.cpu.iq.int_inst_queue_reads 36485 # Number of integer instruction queue reads 461system.cpu.iq.int_inst_queue_writes 19785 # Number of integer instruction queue writes 462system.cpu.iq.int_inst_queue_wakeup_accesses 9739 # Number of integer instruction queue wakeup accesses |
| 459system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 460system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 461system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses | 463system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 464system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 465system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses |
| 462system.cpu.iq.int_alu_accesses 10358 # Number of integer alu accesses | 466system.cpu.iq.int_alu_accesses 10901 # Number of integer alu accesses |
| 463system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses | 467system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses |
| 464system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores | 468system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores |
| 465system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 469system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 466system.cpu.iew.lsq.thread0.squashedLoads 1375 # Number of loads squashed 467system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 468system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 469system.cpu.iew.lsq.thread0.squashedStores 419 # Number of stores squashed | 470system.cpu.iew.lsq.thread0.squashedLoads 1654 # Number of loads squashed 471system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 472system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations 473system.cpu.iew.lsq.thread0.squashedStores 428 # Number of stores squashed |
| 470system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 471system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 472system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 474system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 475system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 476system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
| 473system.cpu.iew.lsq.thread0.cacheBlocked 75 # Number of times an access to memory failed due to the cache being blocked | 477system.cpu.iew.lsq.thread0.cacheBlocked 89 # Number of times an access to memory failed due to the cache being blocked |
| 474system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 478system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 475system.cpu.iew.iewSquashCycles 399 # Number of cycles IEW is squashing 476system.cpu.iew.iewBlockCycles 1377 # Number of cycles IEW is blocking 477system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking 478system.cpu.iew.iewDispatchedInsts 12377 # Number of instructions dispatched to IQ 479system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch 480system.cpu.iew.iewDispLoadInsts 2560 # Number of dispatched load instructions 481system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions 482system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions 483system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall 484system.cpu.iew.iewLSQFullEvents 21 # Number of times the LSQ has become full, causing a stall 485system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 486system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly 487system.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly 488system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute 489system.cpu.iew.iewExecutedInsts 9833 # Number of executed instructions 490system.cpu.iew.iewExecLoadInsts 2109 # Number of load instructions executed 491system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute | 479system.cpu.iew.iewSquashCycles 448 # Number of cycles IEW is squashing 480system.cpu.iew.iewBlockCycles 1371 # Number of cycles IEW is blocking 481system.cpu.iew.iewUnblockCycles 296 # Number of cycles IEW is unblocking 482system.cpu.iew.iewDispatchedInsts 13164 # Number of instructions dispatched to IQ 483system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch 484system.cpu.iew.iewDispLoadInsts 2839 # Number of dispatched load instructions 485system.cpu.iew.iewDispStoreInsts 1293 # Number of dispatched store instructions 486system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 487system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 488system.cpu.iew.iewLSQFullEvents 289 # Number of times the LSQ has become full, causing a stall 489system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations 490system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly 491system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly 492system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute 493system.cpu.iew.iewExecutedInsts 10291 # Number of executed instructions 494system.cpu.iew.iewExecLoadInsts 2309 # Number of load instructions executed 495system.cpu.iew.iewExecSquashedInsts 485 # Number of squashed instructions skipped in execute |
| 492system.cpu.iew.exec_swp 0 # number of swp insts executed | 496system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 493system.cpu.iew.exec_nop 82 # number of nop insts executed 494system.cpu.iew.exec_refs 3199 # number of memory reference insts executed 495system.cpu.iew.exec_branches 1559 # Number of branches executed 496system.cpu.iew.exec_stores 1090 # Number of stores executed 497system.cpu.iew.exec_rate 0.223752 # Inst execution rate 498system.cpu.iew.wb_sent 9541 # cumulative count of insts sent to commit 499system.cpu.iew.wb_count 9387 # cumulative count of insts written-back 500system.cpu.iew.wb_producers 5006 # num instructions producing a value 501system.cpu.iew.wb_consumers 6861 # num instructions consuming a value 502system.cpu.iew.wb_rate 0.213603 # insts written-back per cycle 503system.cpu.iew.wb_fanout 0.729631 # average fanout of values written-back 504system.cpu.commit.commitSquashedInsts 5982 # The number of squashed insts skipped by commit | 497system.cpu.iew.exec_nop 84 # number of nop insts executed 498system.cpu.iew.exec_refs 3386 # number of memory reference insts executed 499system.cpu.iew.exec_branches 1641 # Number of branches executed 500system.cpu.iew.exec_stores 1077 # Number of stores executed 501system.cpu.iew.exec_rate 0.233679 # Inst execution rate 502system.cpu.iew.wb_sent 9945 # cumulative count of insts sent to commit 503system.cpu.iew.wb_count 9749 # cumulative count of insts written-back 504system.cpu.iew.wb_producers 5139 # num instructions producing a value 505system.cpu.iew.wb_consumers 7002 # num instructions consuming a value 506system.cpu.iew.wb_rate 0.221372 # insts written-back per cycle 507system.cpu.iew.wb_fanout 0.733933 # average fanout of values written-back 508system.cpu.commit.commitSquashedInsts 6711 # The number of squashed insts skipped by commit |
| 505system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards | 509system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards |
| 506system.cpu.commit.branchMispredicts 358 # The number of times a branch was mispredicted 507system.cpu.commit.committed_per_cycle::samples 13303 # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::mean 0.481245 # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::stdev 1.398957 # Number of insts commited each cycle | 510system.cpu.commit.branchMispredicts 407 # The number of times a branch was mispredicted 511system.cpu.commit.committed_per_cycle::samples 13565 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::mean 0.471950 # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::stdev 1.389989 # Number of insts commited each cycle |
| 510system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 514system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 511system.cpu.commit.committed_per_cycle::0 10861 81.64% 81.64% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::1 1165 8.76% 90.40% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::2 487 3.66% 94.06% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::3 203 1.53% 95.59% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::4 129 0.97% 96.56% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::5 82 0.62% 97.17% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::6 98 0.74% 97.91% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::7 84 0.63% 98.54% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::8 194 1.46% 100.00% # Number of insts commited each cycle | 515system.cpu.commit.committed_per_cycle::0 11138 82.11% 82.11% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::1 1158 8.54% 90.65% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::2 469 3.46% 94.10% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::3 205 1.51% 95.61% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::4 134 0.99% 96.60% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::5 84 0.62% 97.22% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::6 96 0.71% 97.93% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::7 89 0.66% 98.58% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::8 192 1.42% 100.00% # Number of insts commited each cycle |
| 520system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 524system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 523system.cpu.commit.committed_per_cycle::total 13303 # Number of insts commited each cycle | 527system.cpu.commit.committed_per_cycle::total 13565 # Number of insts commited each cycle |
| 524system.cpu.commit.committedInsts 6402 # Number of instructions committed 525system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 526system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 527system.cpu.commit.refs 2050 # Number of memory references committed 528system.cpu.commit.loads 1185 # Number of loads committed 529system.cpu.commit.membars 0 # Number of memory barriers committed 530system.cpu.commit.branches 1056 # Number of branches committed 531system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 561system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 564system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction 565system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction 566system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 567system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 568system.cpu.commit.op_class_0::total 6402 # Class of committed instruction | 528system.cpu.commit.committedInsts 6402 # Number of instructions committed 529system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 530system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 531system.cpu.commit.refs 2050 # Number of memory references committed 532system.cpu.commit.loads 1185 # Number of loads committed 533system.cpu.commit.membars 0 # Number of memory barriers committed 534system.cpu.commit.branches 1056 # Number of branches committed 535system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 565system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 568system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction 569system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 571system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 572system.cpu.commit.op_class_0::total 6402 # Class of committed instruction |
| 569system.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached 570system.cpu.rob.rob_reads 25142 # The number of ROB reads 571system.cpu.rob.rob_writes 25845 # The number of ROB writes 572system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself 573system.cpu.idleCycles 29573 # Total number of cycles that the CPU has spent unscheduled due to idling | 573system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached 574system.cpu.rob.rob_reads 26135 # The number of ROB reads 575system.cpu.rob.rob_writes 27477 # The number of ROB writes 576system.cpu.timesIdled 253 # Number of times that the entire CPU went into an idle state and unscheduled itself 577system.cpu.idleCycles 29240 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 574system.cpu.committedInsts 6385 # Number of Instructions Simulated 575system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated | 578system.cpu.committedInsts 6385 # Number of Instructions Simulated 579system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated |
| 576system.cpu.cpi 6.882694 # CPI: Cycles Per Instruction 577system.cpu.cpi_total 6.882694 # CPI: Total CPI of All Threads 578system.cpu.ipc 0.145292 # IPC: Instructions Per Cycle 579system.cpu.ipc_total 0.145292 # IPC: Total IPC of All Threads 580system.cpu.int_regfile_reads 12434 # number of integer regfile reads 581system.cpu.int_regfile_writes 7099 # number of integer regfile writes | 580system.cpu.cpi 6.897259 # CPI: Cycles Per Instruction 581system.cpu.cpi_total 6.897259 # CPI: Total CPI of All Threads 582system.cpu.ipc 0.144985 # IPC: Instructions Per Cycle 583system.cpu.ipc_total 0.144985 # IPC: Total IPC of All Threads 584system.cpu.int_regfile_reads 12924 # number of integer regfile reads 585system.cpu.int_regfile_writes 7434 # number of integer regfile writes |
| 582system.cpu.fp_regfile_reads 8 # number of floating regfile reads 583system.cpu.fp_regfile_writes 2 # number of floating regfile writes 584system.cpu.misc_regfile_reads 1 # number of misc regfile reads 585system.cpu.misc_regfile_writes 1 # number of misc regfile writes 586system.cpu.dcache.tags.replacements 0 # number of replacements | 586system.cpu.fp_regfile_reads 8 # number of floating regfile reads 587system.cpu.fp_regfile_writes 2 # number of floating regfile writes 588system.cpu.misc_regfile_reads 1 # number of misc regfile reads 589system.cpu.misc_regfile_writes 1 # number of misc regfile writes 590system.cpu.dcache.tags.replacements 0 # number of replacements |
| 587system.cpu.dcache.tags.tagsinuse 109.593222 # Cycle average of tags in use 588system.cpu.dcache.tags.total_refs 2292 # Total number of references to valid blocks. | 591system.cpu.dcache.tags.tagsinuse 109.409218 # Cycle average of tags in use 592system.cpu.dcache.tags.total_refs 2405 # Total number of references to valid blocks. |
| 589system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. | 593system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. |
| 590system.cpu.dcache.tags.avg_refs 13.248555 # Average number of references to valid blocks. | 594system.cpu.dcache.tags.avg_refs 13.901734 # Average number of references to valid blocks. |
| 591system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 595system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 592system.cpu.dcache.tags.occ_blocks::cpu.data 109.593222 # Average occupied blocks per requestor 593system.cpu.dcache.tags.occ_percent::cpu.data 0.026756 # Average percentage of cache occupancy 594system.cpu.dcache.tags.occ_percent::total 0.026756 # Average percentage of cache occupancy | 596system.cpu.dcache.tags.occ_blocks::cpu.data 109.409218 # Average occupied blocks per requestor 597system.cpu.dcache.tags.occ_percent::cpu.data 0.026711 # Average percentage of cache occupancy 598system.cpu.dcache.tags.occ_percent::total 0.026711 # Average percentage of cache occupancy |
| 595system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 596system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 597system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id 598system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id | 599system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 600system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 601system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id 602system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id |
| 599system.cpu.dcache.tags.tag_accesses 5805 # Number of tag accesses 600system.cpu.dcache.tags.data_accesses 5805 # Number of data accesses 601system.cpu.dcache.ReadReq_hits::cpu.data 1786 # number of ReadReq hits 602system.cpu.dcache.ReadReq_hits::total 1786 # number of ReadReq hits | 603system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses 604system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses 605system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits 606system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits |
| 603system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 604system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits | 607system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 608system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits |
| 605system.cpu.dcache.demand_hits::cpu.data 2292 # number of demand (read+write) hits 606system.cpu.dcache.demand_hits::total 2292 # number of demand (read+write) hits 607system.cpu.dcache.overall_hits::cpu.data 2292 # number of overall hits 608system.cpu.dcache.overall_hits::total 2292 # number of overall hits 609system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses 610system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses | 609system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits 610system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits 611system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits 612system.cpu.dcache.overall_hits::total 2405 # number of overall hits 613system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses 614system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses |
| 611system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 612system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses | 615system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 616system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses |
| 613system.cpu.dcache.demand_misses::cpu.data 524 # number of demand (read+write) misses 614system.cpu.dcache.demand_misses::total 524 # number of demand (read+write) misses 615system.cpu.dcache.overall_misses::cpu.data 524 # number of overall misses 616system.cpu.dcache.overall_misses::total 524 # number of overall misses 617system.cpu.dcache.ReadReq_miss_latency::cpu.data 12170500 # number of ReadReq miss cycles 618system.cpu.dcache.ReadReq_miss_latency::total 12170500 # number of ReadReq miss cycles 619system.cpu.dcache.WriteReq_miss_latency::cpu.data 23651475 # number of WriteReq miss cycles 620system.cpu.dcache.WriteReq_miss_latency::total 23651475 # number of WriteReq miss cycles 621system.cpu.dcache.demand_miss_latency::cpu.data 35821975 # number of demand (read+write) miss cycles 622system.cpu.dcache.demand_miss_latency::total 35821975 # number of demand (read+write) miss cycles 623system.cpu.dcache.overall_miss_latency::cpu.data 35821975 # number of overall miss cycles 624system.cpu.dcache.overall_miss_latency::total 35821975 # number of overall miss cycles 625system.cpu.dcache.ReadReq_accesses::cpu.data 1951 # number of ReadReq accesses(hits+misses) 626system.cpu.dcache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses) | 617system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses 618system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses 619system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses 620system.cpu.dcache.overall_misses::total 539 # number of overall misses 621system.cpu.dcache.ReadReq_miss_latency::cpu.data 12774500 # number of ReadReq miss cycles 622system.cpu.dcache.ReadReq_miss_latency::total 12774500 # number of ReadReq miss cycles 623system.cpu.dcache.WriteReq_miss_latency::cpu.data 23738475 # number of WriteReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::total 23738475 # number of WriteReq miss cycles 625system.cpu.dcache.demand_miss_latency::cpu.data 36512975 # number of demand (read+write) miss cycles 626system.cpu.dcache.demand_miss_latency::total 36512975 # number of demand (read+write) miss cycles 627system.cpu.dcache.overall_miss_latency::cpu.data 36512975 # number of overall miss cycles 628system.cpu.dcache.overall_miss_latency::total 36512975 # number of overall miss cycles 629system.cpu.dcache.ReadReq_accesses::cpu.data 2079 # number of ReadReq accesses(hits+misses) 630system.cpu.dcache.ReadReq_accesses::total 2079 # number of ReadReq accesses(hits+misses) |
| 627system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 628system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) | 631system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 632system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) |
| 629system.cpu.dcache.demand_accesses::cpu.data 2816 # number of demand (read+write) accesses 630system.cpu.dcache.demand_accesses::total 2816 # number of demand (read+write) accesses 631system.cpu.dcache.overall_accesses::cpu.data 2816 # number of overall (read+write) accesses 632system.cpu.dcache.overall_accesses::total 2816 # number of overall (read+write) accesses 633system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084572 # miss rate for ReadReq accesses 634system.cpu.dcache.ReadReq_miss_rate::total 0.084572 # miss rate for ReadReq accesses | 633system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses 634system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses 635system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses 636system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses 637system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086580 # miss rate for ReadReq accesses 638system.cpu.dcache.ReadReq_miss_rate::total 0.086580 # miss rate for ReadReq accesses |
| 635system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 636system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses | 639system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 640system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses |
| 637system.cpu.dcache.demand_miss_rate::cpu.data 0.186080 # miss rate for demand accesses 638system.cpu.dcache.demand_miss_rate::total 0.186080 # miss rate for demand accesses 639system.cpu.dcache.overall_miss_rate::cpu.data 0.186080 # miss rate for overall accesses 640system.cpu.dcache.overall_miss_rate::total 0.186080 # miss rate for overall accesses 641system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73760.606061 # average ReadReq miss latency 642system.cpu.dcache.ReadReq_avg_miss_latency::total 73760.606061 # average ReadReq miss latency 643system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65881.545961 # average WriteReq miss latency 644system.cpu.dcache.WriteReq_avg_miss_latency::total 65881.545961 # average WriteReq miss latency 645system.cpu.dcache.demand_avg_miss_latency::cpu.data 68362.547710 # average overall miss latency 646system.cpu.dcache.demand_avg_miss_latency::total 68362.547710 # average overall miss latency 647system.cpu.dcache.overall_avg_miss_latency::cpu.data 68362.547710 # average overall miss latency 648system.cpu.dcache.overall_avg_miss_latency::total 68362.547710 # average overall miss latency 649system.cpu.dcache.blocked_cycles::no_mshrs 2432 # number of cycles access was blocked | 641system.cpu.dcache.demand_miss_rate::cpu.data 0.183084 # miss rate for demand accesses 642system.cpu.dcache.demand_miss_rate::total 0.183084 # miss rate for demand accesses 643system.cpu.dcache.overall_miss_rate::cpu.data 0.183084 # miss rate for overall accesses 644system.cpu.dcache.overall_miss_rate::total 0.183084 # miss rate for overall accesses 645system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70969.444444 # average ReadReq miss latency 646system.cpu.dcache.ReadReq_avg_miss_latency::total 70969.444444 # average ReadReq miss latency 647system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66123.885794 # average WriteReq miss latency 648system.cpu.dcache.WriteReq_avg_miss_latency::total 66123.885794 # average WriteReq miss latency 649system.cpu.dcache.demand_avg_miss_latency::cpu.data 67742.068646 # average overall miss latency 650system.cpu.dcache.demand_avg_miss_latency::total 67742.068646 # average overall miss latency 651system.cpu.dcache.overall_avg_miss_latency::cpu.data 67742.068646 # average overall miss latency 652system.cpu.dcache.overall_avg_miss_latency::total 67742.068646 # average overall miss latency 653system.cpu.dcache.blocked_cycles::no_mshrs 2423 # number of cycles access was blocked |
| 650system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked 652system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 654system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked 656system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 653system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.558140 # average number of cycles each access was blocked | 657system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.348837 # average number of cycles each access was blocked |
| 654system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.cpu.dcache.fast_writes 0 # number of fast writes performed 656system.cpu.dcache.cache_copies 0 # number of cache copies performed | 658system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.dcache.fast_writes 0 # number of fast writes performed 660system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 657system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits 658system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits | 661system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 662system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits |
| 659system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 660system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits | 663system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 664system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits |
| 661system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits 662system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits 663system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits 664system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits | 665system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits 666system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits 667system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits 668system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits |
| 665system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 666system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 668system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 669system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 670system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 671system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 672system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses | 669system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 670system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 671system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 672system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 673system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 674system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 675system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 676system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses |
| 673system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8462500 # number of ReadReq MSHR miss cycles 674system.cpu.dcache.ReadReq_mshr_miss_latency::total 8462500 # number of ReadReq MSHR miss cycles 675system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5669500 # number of WriteReq MSHR miss cycles 676system.cpu.dcache.WriteReq_mshr_miss_latency::total 5669500 # number of WriteReq MSHR miss cycles 677system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14132000 # number of demand (read+write) MSHR miss cycles 678system.cpu.dcache.demand_mshr_miss_latency::total 14132000 # number of demand (read+write) MSHR miss cycles 679system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14132000 # number of overall MSHR miss cycles 680system.cpu.dcache.overall_mshr_miss_latency::total 14132000 # number of overall MSHR miss cycles 681system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051768 # mshr miss rate for ReadReq accesses 682system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051768 # mshr miss rate for ReadReq accesses | 677system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8466000 # number of ReadReq MSHR miss cycles 678system.cpu.dcache.ReadReq_mshr_miss_latency::total 8466000 # number of ReadReq MSHR miss cycles 679system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5695500 # number of WriteReq MSHR miss cycles 680system.cpu.dcache.WriteReq_mshr_miss_latency::total 5695500 # number of WriteReq MSHR miss cycles 681system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14161500 # number of demand (read+write) MSHR miss cycles 682system.cpu.dcache.demand_mshr_miss_latency::total 14161500 # number of demand (read+write) MSHR miss cycles 683system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14161500 # number of overall MSHR miss cycles 684system.cpu.dcache.overall_mshr_miss_latency::total 14161500 # number of overall MSHR miss cycles 685system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048581 # mshr miss rate for ReadReq accesses 686system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048581 # mshr miss rate for ReadReq accesses |
| 683system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 684system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses | 687system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 688system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses |
| 685system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061435 # mshr miss rate for demand accesses 686system.cpu.dcache.demand_mshr_miss_rate::total 0.061435 # mshr miss rate for demand accesses 687system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061435 # mshr miss rate for overall accesses 688system.cpu.dcache.overall_mshr_miss_rate::total 0.061435 # mshr miss rate for overall accesses 689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83787.128713 # average ReadReq mshr miss latency 690system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83787.128713 # average ReadReq mshr miss latency 691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556 # average WriteReq mshr miss latency 692system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556 # average WriteReq mshr miss latency 693system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81687.861272 # average overall mshr miss latency 694system.cpu.dcache.demand_avg_mshr_miss_latency::total 81687.861272 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81687.861272 # average overall mshr miss latency 696system.cpu.dcache.overall_avg_mshr_miss_latency::total 81687.861272 # average overall mshr miss latency | 689system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for demand accesses 690system.cpu.dcache.demand_mshr_miss_rate::total 0.058764 # mshr miss rate for demand accesses 691system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for overall accesses 692system.cpu.dcache.overall_mshr_miss_rate::total 0.058764 # mshr miss rate for overall accesses 693system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83821.782178 # average ReadReq mshr miss latency 694system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83821.782178 # average ReadReq mshr miss latency 695system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79104.166667 # average WriteReq mshr miss latency 696system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79104.166667 # average WriteReq mshr miss latency 697system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 698system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency 699system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency 700system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency |
| 697system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 698system.cpu.icache.tags.replacements 0 # number of replacements | 701system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 702system.cpu.icache.tags.replacements 0 # number of replacements |
| 699system.cpu.icache.tags.tagsinuse 157.288732 # Cycle average of tags in use 700system.cpu.icache.tags.total_refs 1677 # Total number of references to valid blocks. 701system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. 702system.cpu.icache.tags.avg_refs 5.392283 # Average number of references to valid blocks. | 703system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use 704system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks. 705system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. 706system.cpu.icache.tags.avg_refs 5.865815 # Average number of references to valid blocks. |
| 703system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 707system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 704system.cpu.icache.tags.occ_blocks::cpu.inst 157.288732 # Average occupied blocks per requestor 705system.cpu.icache.tags.occ_percent::cpu.inst 0.076801 # Average percentage of cache occupancy 706system.cpu.icache.tags.occ_percent::total 0.076801 # Average percentage of cache occupancy 707system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id 708system.cpu.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 709system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 710system.cpu.icache.tags.occ_task_id_percent::1024 0.151855 # Percentage of cache occupancy per task id 711system.cpu.icache.tags.tag_accesses 4583 # Number of tag accesses 712system.cpu.icache.tags.data_accesses 4583 # Number of data accesses 713system.cpu.icache.ReadReq_hits::cpu.inst 1677 # number of ReadReq hits 714system.cpu.icache.ReadReq_hits::total 1677 # number of ReadReq hits 715system.cpu.icache.demand_hits::cpu.inst 1677 # number of demand (read+write) hits 716system.cpu.icache.demand_hits::total 1677 # number of demand (read+write) hits 717system.cpu.icache.overall_hits::cpu.inst 1677 # number of overall hits 718system.cpu.icache.overall_hits::total 1677 # number of overall hits 719system.cpu.icache.ReadReq_misses::cpu.inst 459 # number of ReadReq misses 720system.cpu.icache.ReadReq_misses::total 459 # number of ReadReq misses 721system.cpu.icache.demand_misses::cpu.inst 459 # number of demand (read+write) misses 722system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses 723system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses 724system.cpu.icache.overall_misses::total 459 # number of overall misses 725system.cpu.icache.ReadReq_miss_latency::cpu.inst 32358000 # number of ReadReq miss cycles 726system.cpu.icache.ReadReq_miss_latency::total 32358000 # number of ReadReq miss cycles 727system.cpu.icache.demand_miss_latency::cpu.inst 32358000 # number of demand (read+write) miss cycles 728system.cpu.icache.demand_miss_latency::total 32358000 # number of demand (read+write) miss cycles 729system.cpu.icache.overall_miss_latency::cpu.inst 32358000 # number of overall miss cycles 730system.cpu.icache.overall_miss_latency::total 32358000 # number of overall miss cycles 731system.cpu.icache.ReadReq_accesses::cpu.inst 2136 # number of ReadReq accesses(hits+misses) 732system.cpu.icache.ReadReq_accesses::total 2136 # number of ReadReq accesses(hits+misses) 733system.cpu.icache.demand_accesses::cpu.inst 2136 # number of demand (read+write) accesses 734system.cpu.icache.demand_accesses::total 2136 # number of demand (read+write) accesses 735system.cpu.icache.overall_accesses::cpu.inst 2136 # number of overall (read+write) accesses 736system.cpu.icache.overall_accesses::total 2136 # number of overall (read+write) accesses 737system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.214888 # miss rate for ReadReq accesses 738system.cpu.icache.ReadReq_miss_rate::total 0.214888 # miss rate for ReadReq accesses 739system.cpu.icache.demand_miss_rate::cpu.inst 0.214888 # miss rate for demand accesses 740system.cpu.icache.demand_miss_rate::total 0.214888 # miss rate for demand accesses 741system.cpu.icache.overall_miss_rate::cpu.inst 0.214888 # miss rate for overall accesses 742system.cpu.icache.overall_miss_rate::total 0.214888 # miss rate for overall accesses 743system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70496.732026 # average ReadReq miss latency 744system.cpu.icache.ReadReq_avg_miss_latency::total 70496.732026 # average ReadReq miss latency 745system.cpu.icache.demand_avg_miss_latency::cpu.inst 70496.732026 # average overall miss latency 746system.cpu.icache.demand_avg_miss_latency::total 70496.732026 # average overall miss latency 747system.cpu.icache.overall_avg_miss_latency::cpu.inst 70496.732026 # average overall miss latency 748system.cpu.icache.overall_avg_miss_latency::total 70496.732026 # average overall miss latency 749system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 708system.cpu.icache.tags.occ_blocks::cpu.inst 158.432951 # Average occupied blocks per requestor 709system.cpu.icache.tags.occ_percent::cpu.inst 0.077360 # Average percentage of cache occupancy 710system.cpu.icache.tags.occ_percent::total 0.077360 # Average percentage of cache occupancy 711system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id 712system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id 713system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id 714system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id 715system.cpu.icache.tags.tag_accesses 4899 # Number of tag accesses 716system.cpu.icache.tags.data_accesses 4899 # Number of data accesses 717system.cpu.icache.ReadReq_hits::cpu.inst 1836 # number of ReadReq hits 718system.cpu.icache.ReadReq_hits::total 1836 # number of ReadReq hits 719system.cpu.icache.demand_hits::cpu.inst 1836 # number of demand (read+write) hits 720system.cpu.icache.demand_hits::total 1836 # number of demand (read+write) hits 721system.cpu.icache.overall_hits::cpu.inst 1836 # number of overall hits 722system.cpu.icache.overall_hits::total 1836 # number of overall hits 723system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses 724system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses 725system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses 726system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses 727system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses 728system.cpu.icache.overall_misses::total 457 # number of overall misses 729system.cpu.icache.ReadReq_miss_latency::cpu.inst 32838500 # number of ReadReq miss cycles 730system.cpu.icache.ReadReq_miss_latency::total 32838500 # number of ReadReq miss cycles 731system.cpu.icache.demand_miss_latency::cpu.inst 32838500 # number of demand (read+write) miss cycles 732system.cpu.icache.demand_miss_latency::total 32838500 # number of demand (read+write) miss cycles 733system.cpu.icache.overall_miss_latency::cpu.inst 32838500 # number of overall miss cycles 734system.cpu.icache.overall_miss_latency::total 32838500 # number of overall miss cycles 735system.cpu.icache.ReadReq_accesses::cpu.inst 2293 # number of ReadReq accesses(hits+misses) 736system.cpu.icache.ReadReq_accesses::total 2293 # number of ReadReq accesses(hits+misses) 737system.cpu.icache.demand_accesses::cpu.inst 2293 # number of demand (read+write) accesses 738system.cpu.icache.demand_accesses::total 2293 # number of demand (read+write) accesses 739system.cpu.icache.overall_accesses::cpu.inst 2293 # number of overall (read+write) accesses 740system.cpu.icache.overall_accesses::total 2293 # number of overall (read+write) accesses 741system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199302 # miss rate for ReadReq accesses 742system.cpu.icache.ReadReq_miss_rate::total 0.199302 # miss rate for ReadReq accesses 743system.cpu.icache.demand_miss_rate::cpu.inst 0.199302 # miss rate for demand accesses 744system.cpu.icache.demand_miss_rate::total 0.199302 # miss rate for demand accesses 745system.cpu.icache.overall_miss_rate::cpu.inst 0.199302 # miss rate for overall accesses 746system.cpu.icache.overall_miss_rate::total 0.199302 # miss rate for overall accesses 747system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71856.673961 # average ReadReq miss latency 748system.cpu.icache.ReadReq_avg_miss_latency::total 71856.673961 # average ReadReq miss latency 749system.cpu.icache.demand_avg_miss_latency::cpu.inst 71856.673961 # average overall miss latency 750system.cpu.icache.demand_avg_miss_latency::total 71856.673961 # average overall miss latency 751system.cpu.icache.overall_avg_miss_latency::cpu.inst 71856.673961 # average overall miss latency 752system.cpu.icache.overall_avg_miss_latency::total 71856.673961 # average overall miss latency 753system.cpu.icache.blocked_cycles::no_mshrs 54 # number of cycles access was blocked |
| 750system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 754system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 751system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked | 755system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked |
| 752system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 756system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 753system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 757system.cpu.icache.avg_blocked_cycles::no_mshrs 54 # average number of cycles each access was blocked |
| 754system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 755system.cpu.icache.fast_writes 0 # number of fast writes performed 756system.cpu.icache.cache_copies 0 # number of cache copies performed | 758system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu.icache.fast_writes 0 # number of fast writes performed 760system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 757system.cpu.icache.ReadReq_mshr_hits::cpu.inst 148 # number of ReadReq MSHR hits 758system.cpu.icache.ReadReq_mshr_hits::total 148 # number of ReadReq MSHR hits 759system.cpu.icache.demand_mshr_hits::cpu.inst 148 # number of demand (read+write) MSHR hits 760system.cpu.icache.demand_mshr_hits::total 148 # number of demand (read+write) MSHR hits 761system.cpu.icache.overall_mshr_hits::cpu.inst 148 # number of overall MSHR hits 762system.cpu.icache.overall_mshr_hits::total 148 # number of overall MSHR hits 763system.cpu.icache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses 764system.cpu.icache.ReadReq_mshr_misses::total 311 # number of ReadReq MSHR misses 765system.cpu.icache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses 766system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses 767system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses 768system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses 769system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23850000 # number of ReadReq MSHR miss cycles 770system.cpu.icache.ReadReq_mshr_miss_latency::total 23850000 # number of ReadReq MSHR miss cycles 771system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23850000 # number of demand (read+write) MSHR miss cycles 772system.cpu.icache.demand_mshr_miss_latency::total 23850000 # number of demand (read+write) MSHR miss cycles 773system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23850000 # number of overall MSHR miss cycles 774system.cpu.icache.overall_mshr_miss_latency::total 23850000 # number of overall MSHR miss cycles 775system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145599 # mshr miss rate for ReadReq accesses 776system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145599 # mshr miss rate for ReadReq accesses 777system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145599 # mshr miss rate for demand accesses 778system.cpu.icache.demand_mshr_miss_rate::total 0.145599 # mshr miss rate for demand accesses 779system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145599 # mshr miss rate for overall accesses 780system.cpu.icache.overall_mshr_miss_rate::total 0.145599 # mshr miss rate for overall accesses 781system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76688.102894 # average ReadReq mshr miss latency 782system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76688.102894 # average ReadReq mshr miss latency 783system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76688.102894 # average overall mshr miss latency 784system.cpu.icache.demand_avg_mshr_miss_latency::total 76688.102894 # average overall mshr miss latency 785system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76688.102894 # average overall mshr miss latency 786system.cpu.icache.overall_avg_mshr_miss_latency::total 76688.102894 # average overall mshr miss latency | 761system.cpu.icache.ReadReq_mshr_hits::cpu.inst 144 # number of ReadReq MSHR hits 762system.cpu.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits 763system.cpu.icache.demand_mshr_hits::cpu.inst 144 # number of demand (read+write) MSHR hits 764system.cpu.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits 765system.cpu.icache.overall_mshr_hits::cpu.inst 144 # number of overall MSHR hits 766system.cpu.icache.overall_mshr_hits::total 144 # number of overall MSHR hits 767system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 768system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 769system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 770system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 771system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 772system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses 773system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24470500 # number of ReadReq MSHR miss cycles 774system.cpu.icache.ReadReq_mshr_miss_latency::total 24470500 # number of ReadReq MSHR miss cycles 775system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24470500 # number of demand (read+write) MSHR miss cycles 776system.cpu.icache.demand_mshr_miss_latency::total 24470500 # number of demand (read+write) MSHR miss cycles 777system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24470500 # number of overall MSHR miss cycles 778system.cpu.icache.overall_mshr_miss_latency::total 24470500 # number of overall MSHR miss cycles 779system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for ReadReq accesses 780system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136502 # mshr miss rate for ReadReq accesses 781system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for demand accesses 782system.cpu.icache.demand_mshr_miss_rate::total 0.136502 # mshr miss rate for demand accesses 783system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for overall accesses 784system.cpu.icache.overall_mshr_miss_rate::total 0.136502 # mshr miss rate for overall accesses 785system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78180.511182 # average ReadReq mshr miss latency 786system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78180.511182 # average ReadReq mshr miss latency 787system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 788system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency 789system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency 790system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency |
| 787system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 788system.cpu.l2cache.tags.replacements 0 # number of replacements | 791system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 792system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 789system.cpu.l2cache.tags.tagsinuse 219.942323 # Cycle average of tags in use | 793system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use |
| 790system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. | 794system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. |
| 791system.cpu.l2cache.tags.sampled_refs 411 # Sample count of references to valid blocks. 792system.cpu.l2cache.tags.avg_refs 0.002433 # Average number of references to valid blocks. | 795system.cpu.l2cache.tags.sampled_refs 413 # Sample count of references to valid blocks. 796system.cpu.l2cache.tags.avg_refs 0.002421 # Average number of references to valid blocks. |
| 793system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 797system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 794system.cpu.l2cache.tags.occ_blocks::cpu.inst 157.331171 # Average occupied blocks per requestor 795system.cpu.l2cache.tags.occ_blocks::cpu.data 62.611152 # Average occupied blocks per requestor 796system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004801 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::cpu.data 0.001911 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_percent::total 0.006712 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id 802system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012543 # Percentage of cache occupancy per task id 803system.cpu.l2cache.tags.tag_accesses 4355 # Number of tag accesses 804system.cpu.l2cache.tags.data_accesses 4355 # Number of data accesses | 798system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.475596 # Average occupied blocks per requestor 799system.cpu.l2cache.tags.occ_blocks::cpu.data 62.519281 # Average occupied blocks per requestor 800system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy 801system.cpu.l2cache.tags.occ_percent::cpu.data 0.001908 # Average percentage of cache occupancy 802system.cpu.l2cache.tags.occ_percent::total 0.006744 # Average percentage of cache occupancy 803system.cpu.l2cache.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id 805system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id 806system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012604 # Percentage of cache occupancy per task id 807system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses 808system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses |
| 805system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 806system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 807system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 808system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 809system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 810system.cpu.l2cache.overall_hits::total 1 # number of overall hits 811system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 812system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses | 809system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 810system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 811system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 812system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 813system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 814system.cpu.l2cache.overall_hits::total 1 # number of overall hits 815system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 816system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses |
| 813system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 310 # number of ReadCleanReq misses 814system.cpu.l2cache.ReadCleanReq_misses::total 310 # number of ReadCleanReq misses | 817system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 312 # number of ReadCleanReq misses 818system.cpu.l2cache.ReadCleanReq_misses::total 312 # number of ReadCleanReq misses |
| 815system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 816system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses | 819system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 820system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses |
| 817system.cpu.l2cache.demand_misses::cpu.inst 310 # number of demand (read+write) misses | 821system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses |
| 818system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses | 822system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses |
| 819system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses 820system.cpu.l2cache.overall_misses::cpu.inst 310 # number of overall misses | 823system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses 824system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses |
| 821system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses | 825system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses |
| 822system.cpu.l2cache.overall_misses::total 483 # number of overall misses 823system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5558500 # number of ReadExReq miss cycles 824system.cpu.l2cache.ReadExReq_miss_latency::total 5558500 # number of ReadExReq miss cycles 825system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23369500 # number of ReadCleanReq miss cycles 826system.cpu.l2cache.ReadCleanReq_miss_latency::total 23369500 # number of ReadCleanReq miss cycles 827system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8303500 # number of ReadSharedReq miss cycles 828system.cpu.l2cache.ReadSharedReq_miss_latency::total 8303500 # number of ReadSharedReq miss cycles 829system.cpu.l2cache.demand_miss_latency::cpu.inst 23369500 # number of demand (read+write) miss cycles 830system.cpu.l2cache.demand_miss_latency::cpu.data 13862000 # number of demand (read+write) miss cycles 831system.cpu.l2cache.demand_miss_latency::total 37231500 # number of demand (read+write) miss cycles 832system.cpu.l2cache.overall_miss_latency::cpu.inst 23369500 # number of overall miss cycles 833system.cpu.l2cache.overall_miss_latency::cpu.data 13862000 # number of overall miss cycles 834system.cpu.l2cache.overall_miss_latency::total 37231500 # number of overall miss cycles | 826system.cpu.l2cache.overall_misses::total 485 # number of overall misses 827system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5584500 # number of ReadExReq miss cycles 828system.cpu.l2cache.ReadExReq_miss_latency::total 5584500 # number of ReadExReq miss cycles 829system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23987500 # number of ReadCleanReq miss cycles 830system.cpu.l2cache.ReadCleanReq_miss_latency::total 23987500 # number of ReadCleanReq miss cycles 831system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8306000 # number of ReadSharedReq miss cycles 832system.cpu.l2cache.ReadSharedReq_miss_latency::total 8306000 # number of ReadSharedReq miss cycles 833system.cpu.l2cache.demand_miss_latency::cpu.inst 23987500 # number of demand (read+write) miss cycles 834system.cpu.l2cache.demand_miss_latency::cpu.data 13890500 # number of demand (read+write) miss cycles 835system.cpu.l2cache.demand_miss_latency::total 37878000 # number of demand (read+write) miss cycles 836system.cpu.l2cache.overall_miss_latency::cpu.inst 23987500 # number of overall miss cycles 837system.cpu.l2cache.overall_miss_latency::cpu.data 13890500 # number of overall miss cycles 838system.cpu.l2cache.overall_miss_latency::total 37878000 # number of overall miss cycles |
| 835system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 836system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) | 839system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 840system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) |
| 837system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 311 # number of ReadCleanReq accesses(hits+misses) 838system.cpu.l2cache.ReadCleanReq_accesses::total 311 # number of ReadCleanReq accesses(hits+misses) | 841system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) 842system.cpu.l2cache.ReadCleanReq_accesses::total 313 # number of ReadCleanReq accesses(hits+misses) |
| 839system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 840system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) | 843system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 844system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) |
| 841system.cpu.l2cache.demand_accesses::cpu.inst 311 # number of demand (read+write) accesses | 845system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses |
| 842system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses | 846system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses |
| 843system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses 844system.cpu.l2cache.overall_accesses::cpu.inst 311 # number of overall (read+write) accesses | 847system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses 848system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses |
| 845system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses | 849system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses |
| 846system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses | 850system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses |
| 847system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 848system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 851system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 852system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 849system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996785 # miss rate for ReadCleanReq accesses 850system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996785 # miss rate for ReadCleanReq accesses | 853system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadCleanReq accesses 854system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996805 # miss rate for ReadCleanReq accesses |
| 851system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 852system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses | 855system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 856system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| 853system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996785 # miss rate for demand accesses | 857system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses |
| 854system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 858system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 855system.cpu.l2cache.demand_miss_rate::total 0.997934 # miss rate for demand accesses 856system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996785 # miss rate for overall accesses | 859system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses 860system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses |
| 857system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 861system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 858system.cpu.l2cache.overall_miss_rate::total 0.997934 # miss rate for overall accesses 859system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77201.388889 # average ReadExReq miss latency 860system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77201.388889 # average ReadExReq miss latency 861system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75385.483871 # average ReadCleanReq miss latency 862system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75385.483871 # average ReadCleanReq miss latency 863system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82212.871287 # average ReadSharedReq miss latency 864system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82212.871287 # average ReadSharedReq miss latency 865system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75385.483871 # average overall miss latency 866system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80127.167630 # average overall miss latency 867system.cpu.l2cache.demand_avg_miss_latency::total 77083.850932 # average overall miss latency 868system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75385.483871 # average overall miss latency 869system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80127.167630 # average overall miss latency 870system.cpu.l2cache.overall_avg_miss_latency::total 77083.850932 # average overall miss latency | 862system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses 863system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77562.500000 # average ReadExReq miss latency 864system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77562.500000 # average ReadExReq miss latency 865system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76883.012821 # average ReadCleanReq miss latency 866system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76883.012821 # average ReadCleanReq miss latency 867system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82237.623762 # average ReadSharedReq miss latency 868system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82237.623762 # average ReadSharedReq miss latency 869system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76883.012821 # average overall miss latency 870system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80291.907514 # average overall miss latency 871system.cpu.l2cache.demand_avg_miss_latency::total 78098.969072 # average overall miss latency 872system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76883.012821 # average overall miss latency 873system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80291.907514 # average overall miss latency 874system.cpu.l2cache.overall_avg_miss_latency::total 78098.969072 # average overall miss latency |
| 871system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 872system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 873system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 874system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 875system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 876system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 877system.cpu.l2cache.fast_writes 0 # number of fast writes performed 878system.cpu.l2cache.cache_copies 0 # number of cache copies performed 879system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 880system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses | 875system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 876system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 877system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 878system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 879system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 880system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 881system.cpu.l2cache.fast_writes 0 # number of fast writes performed 882system.cpu.l2cache.cache_copies 0 # number of cache copies performed 883system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 884system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses |
| 881system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 310 # number of ReadCleanReq MSHR misses 882system.cpu.l2cache.ReadCleanReq_mshr_misses::total 310 # number of ReadCleanReq MSHR misses | 885system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses 886system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses |
| 883system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 884system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses | 887system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 888system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses |
| 885system.cpu.l2cache.demand_mshr_misses::cpu.inst 310 # number of demand (read+write) MSHR misses | 889system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses |
| 886system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses | 890system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses |
| 887system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses 888system.cpu.l2cache.overall_mshr_misses::cpu.inst 310 # number of overall MSHR misses | 891system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses 892system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses |
| 889system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses | 893system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses |
| 890system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses 891system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4838500 # number of ReadExReq MSHR miss cycles 892system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4838500 # number of ReadExReq MSHR miss cycles 893system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20269500 # number of ReadCleanReq MSHR miss cycles 894system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20269500 # number of ReadCleanReq MSHR miss cycles 895system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7293500 # number of ReadSharedReq MSHR miss cycles 896system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7293500 # number of ReadSharedReq MSHR miss cycles 897system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20269500 # number of demand (read+write) MSHR miss cycles 898system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12132000 # number of demand (read+write) MSHR miss cycles 899system.cpu.l2cache.demand_mshr_miss_latency::total 32401500 # number of demand (read+write) MSHR miss cycles 900system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20269500 # number of overall MSHR miss cycles 901system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12132000 # number of overall MSHR miss cycles 902system.cpu.l2cache.overall_mshr_miss_latency::total 32401500 # number of overall MSHR miss cycles | 894system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses 895system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4864500 # number of ReadExReq MSHR miss cycles 896system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4864500 # number of ReadExReq MSHR miss cycles 897system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20867500 # number of ReadCleanReq MSHR miss cycles 898system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20867500 # number of ReadCleanReq MSHR miss cycles 899system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7296000 # number of ReadSharedReq MSHR miss cycles 900system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7296000 # number of ReadSharedReq MSHR miss cycles 901system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20867500 # number of demand (read+write) MSHR miss cycles 902system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12160500 # number of demand (read+write) MSHR miss cycles 903system.cpu.l2cache.demand_mshr_miss_latency::total 33028000 # number of demand (read+write) MSHR miss cycles 904system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20867500 # number of overall MSHR miss cycles 905system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12160500 # number of overall MSHR miss cycles 906system.cpu.l2cache.overall_mshr_miss_latency::total 33028000 # number of overall MSHR miss cycles |
| 903system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 904system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 907system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 908system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 905system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for ReadCleanReq accesses 906system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996785 # mshr miss rate for ReadCleanReq accesses | 909system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses 910system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses |
| 907system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 908system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses | 911system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 912system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses |
| 909system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for demand accesses | 913system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses |
| 910system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 914system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 911system.cpu.l2cache.demand_mshr_miss_rate::total 0.997934 # mshr miss rate for demand accesses 912system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for overall accesses | 915system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses 916system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses |
| 913system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 917system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 914system.cpu.l2cache.overall_mshr_miss_rate::total 0.997934 # mshr miss rate for overall accesses 915system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency 916system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency 917system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65385.483871 # average ReadCleanReq mshr miss latency 918system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65385.483871 # average ReadCleanReq mshr miss latency 919system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72212.871287 # average ReadSharedReq mshr miss latency 920system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72212.871287 # average ReadSharedReq mshr miss latency 921system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65385.483871 # average overall mshr miss latency 922system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70127.167630 # average overall mshr miss latency 923system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67083.850932 # average overall mshr miss latency 924system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65385.483871 # average overall mshr miss latency 925system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70127.167630 # average overall mshr miss latency 926system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67083.850932 # average overall mshr miss latency | 918system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses 919system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67562.500000 # average ReadExReq mshr miss latency 920system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67562.500000 # average ReadExReq mshr miss latency 921system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66883.012821 # average ReadCleanReq mshr miss latency 922system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66883.012821 # average ReadCleanReq mshr miss latency 923system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72237.623762 # average ReadSharedReq mshr miss latency 924system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72237.623762 # average ReadSharedReq mshr miss latency 925system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency 926system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency 928system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency 929system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency |
| 927system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 931system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 928system.cpu.toL2Bus.snoop_filter.tot_requests 484 # Total number of requests made to the snoop filter. | 932system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. |
| 929system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 930system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 931system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 932system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 933system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 933system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 934system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 935system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 936system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 937system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 934system.cpu.toL2Bus.trans_dist::ReadResp 412 # Transaction distribution | 938system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution |
| 935system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution | 939system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution |
| 937system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution | 941system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution |
| 938system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution | 942system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution |
| 939system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes) | 943system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) |
| 940system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) | 944system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) |
| 941system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes) | 945system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) 946system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20032 # Cumulative packet size per connected master and slave (bytes) |
| 943system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) | 947system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) |
| 944system.cpu.toL2Bus.pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) | 948system.cpu.toL2Bus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) |
| 945system.cpu.toL2Bus.snoops 0 # Total snoops (count) | 949system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| 946system.cpu.toL2Bus.snoop_fanout::samples 484 # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::mean 0.002066 # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::stdev 0.045455 # Request fanout histogram | 950system.cpu.toL2Bus.snoop_fanout::samples 486 # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::mean 0.002058 # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram |
| 949system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 953system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 950system.cpu.toL2Bus.snoop_fanout::0 483 99.79% 99.79% # Request fanout histogram | 954system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram |
| 951system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 955system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 956system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 957system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 959system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 956system.cpu.toL2Bus.snoop_fanout::total 484 # Request fanout histogram 957system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) | 960system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram 961system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) |
| 958system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) | 962system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) |
| 959system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks) | 963system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) |
| 960system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 961system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 962system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) | 964system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 965system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 966system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) |
| 963system.membus.trans_dist::ReadResp 411 # Transaction distribution | 967system.membus.trans_dist::ReadResp 413 # Transaction distribution |
| 964system.membus.trans_dist::ReadExReq 72 # Transaction distribution 965system.membus.trans_dist::ReadExResp 72 # Transaction distribution | 968system.membus.trans_dist::ReadExReq 72 # Transaction distribution 969system.membus.trans_dist::ReadExResp 72 # Transaction distribution |
| 966system.membus.trans_dist::ReadSharedReq 411 # Transaction distribution 967system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 966 # Packet count per connected master and slave (bytes) 968system.membus.pkt_count::total 966 # Packet count per connected master and slave (bytes) 969system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30912 # Cumulative packet size per connected master and slave (bytes) 970system.membus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes) | 970system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 971system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) 972system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 973system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) 974system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) |
| 971system.membus.snoops 0 # Total snoops (count) | 975system.membus.snoops 0 # Total snoops (count) |
| 972system.membus.snoop_fanout::samples 483 # Request fanout histogram | 976system.membus.snoop_fanout::samples 485 # Request fanout histogram |
| 973system.membus.snoop_fanout::mean 0 # Request fanout histogram 974system.membus.snoop_fanout::stdev 0 # Request fanout histogram 975system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 977system.membus.snoop_fanout::mean 0 # Request fanout histogram 978system.membus.snoop_fanout::stdev 0 # Request fanout histogram 979system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 976system.membus.snoop_fanout::0 483 100.00% 100.00% # Request fanout histogram | 980system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram |
| 977system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 978system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 979system.membus.snoop_fanout::min_value 0 # Request fanout histogram 980system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 981system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 982system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 983system.membus.snoop_fanout::min_value 0 # Request fanout histogram 984system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 981system.membus.snoop_fanout::total 483 # Request fanout histogram 982system.membus.reqLayer0.occupancy 588000 # Layer occupancy (ticks) | 985system.membus.snoop_fanout::total 485 # Request fanout histogram 986system.membus.reqLayer0.occupancy 590500 # Layer occupancy (ticks) |
| 983system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) | 987system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) |
| 984system.membus.respLayer1.occupancy 2567750 # Layer occupancy (ticks) | 988system.membus.respLayer1.occupancy 2579250 # Layer occupancy (ticks) |
| 985system.membus.respLayer1.utilization 11.7 # Layer utilization (%) 986 987---------- End Simulation Statistics ---------- | 989system.membus.respLayer1.utilization 11.7 # Layer utilization (%) 990 991---------- End Simulation Statistics ---------- |