| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21900500 # Number of ticks simulated 5final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21900500 # Number of ticks simulated 5final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 43231 # Simulator instruction rate (inst/s) 8host_op_rate 43225 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 148545474 # Simulator tick rate (ticks/s) 10host_mem_usage 289772 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host | 7host_inst_rate 94413 # Simulator instruction rate (inst/s) 8host_op_rate 94393 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 324370159 # Simulator tick rate (ticks/s) 10host_mem_usage 297000 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host |
| 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30784 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory --- 673 unchanged lines hidden (view full) --- 693system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556 # average WriteReq mshr miss latency 694system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556 # average WriteReq mshr miss latency 695system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency 696system.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency 697system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency 698system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency 699system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 700system.cpu.icache.tags.replacements 0 # number of replacements | 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30784 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory --- 673 unchanged lines hidden (view full) --- 693system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556 # average WriteReq mshr miss latency 694system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556 # average WriteReq mshr miss latency 695system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency 696system.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency 697system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency 698system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency 699system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 700system.cpu.icache.tags.replacements 0 # number of replacements |
| 701system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use | 701system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use |
| 702system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. 703system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. 704system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. 705system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 702system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. 703system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. 704system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. 705system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 706system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor | 706system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor |
| 707system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy 708system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy 709system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id 710system.cpu.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 711system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 712system.cpu.icache.tags.occ_task_id_percent::1024 0.151855 # Percentage of cache occupancy per task id 713system.cpu.icache.tags.tag_accesses 4483 # Number of tag accesses 714system.cpu.icache.tags.data_accesses 4483 # Number of data accesses --- 4 unchanged lines hidden (view full) --- 719system.cpu.icache.overall_hits::cpu.inst 1627 # number of overall hits 720system.cpu.icache.overall_hits::total 1627 # number of overall hits 721system.cpu.icache.ReadReq_misses::cpu.inst 459 # number of ReadReq misses 722system.cpu.icache.ReadReq_misses::total 459 # number of ReadReq misses 723system.cpu.icache.demand_misses::cpu.inst 459 # number of demand (read+write) misses 724system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses 725system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses 726system.cpu.icache.overall_misses::total 459 # number of overall misses | 707system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy 708system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy 709system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id 710system.cpu.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 711system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 712system.cpu.icache.tags.occ_task_id_percent::1024 0.151855 # Percentage of cache occupancy per task id 713system.cpu.icache.tags.tag_accesses 4483 # Number of tag accesses 714system.cpu.icache.tags.data_accesses 4483 # Number of data accesses --- 4 unchanged lines hidden (view full) --- 719system.cpu.icache.overall_hits::cpu.inst 1627 # number of overall hits 720system.cpu.icache.overall_hits::total 1627 # number of overall hits 721system.cpu.icache.ReadReq_misses::cpu.inst 459 # number of ReadReq misses 722system.cpu.icache.ReadReq_misses::total 459 # number of ReadReq misses 723system.cpu.icache.demand_misses::cpu.inst 459 # number of demand (read+write) misses 724system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses 725system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses 726system.cpu.icache.overall_misses::total 459 # number of overall misses |
| 727system.cpu.icache.ReadReq_miss_latency::cpu.inst 32352500 # number of ReadReq miss cycles 728system.cpu.icache.ReadReq_miss_latency::total 32352500 # number of ReadReq miss cycles 729system.cpu.icache.demand_miss_latency::cpu.inst 32352500 # number of demand (read+write) miss cycles 730system.cpu.icache.demand_miss_latency::total 32352500 # number of demand (read+write) miss cycles 731system.cpu.icache.overall_miss_latency::cpu.inst 32352500 # number of overall miss cycles 732system.cpu.icache.overall_miss_latency::total 32352500 # number of overall miss cycles | 727system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles 728system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles 729system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles 730system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles 731system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles 732system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles |
| 733system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses) 734system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses) 735system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses 736system.cpu.icache.demand_accesses::total 2086 # number of demand (read+write) accesses 737system.cpu.icache.overall_accesses::cpu.inst 2086 # number of overall (read+write) accesses 738system.cpu.icache.overall_accesses::total 2086 # number of overall (read+write) accesses 739system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.220038 # miss rate for ReadReq accesses 740system.cpu.icache.ReadReq_miss_rate::total 0.220038 # miss rate for ReadReq accesses 741system.cpu.icache.demand_miss_rate::cpu.inst 0.220038 # miss rate for demand accesses 742system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses 743system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses 744system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses | 733system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses) 734system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses) 735system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses 736system.cpu.icache.demand_accesses::total 2086 # number of demand (read+write) accesses 737system.cpu.icache.overall_accesses::cpu.inst 2086 # number of overall (read+write) accesses 738system.cpu.icache.overall_accesses::total 2086 # number of overall (read+write) accesses 739system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.220038 # miss rate for ReadReq accesses 740system.cpu.icache.ReadReq_miss_rate::total 0.220038 # miss rate for ReadReq accesses 741system.cpu.icache.demand_miss_rate::cpu.inst 0.220038 # miss rate for demand accesses 742system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses 743system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses 744system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses |
| 745system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70484.749455 # average ReadReq miss latency 746system.cpu.icache.ReadReq_avg_miss_latency::total 70484.749455 # average ReadReq miss latency 747system.cpu.icache.demand_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency 748system.cpu.icache.demand_avg_miss_latency::total 70484.749455 # average overall miss latency 749system.cpu.icache.overall_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency 750system.cpu.icache.overall_avg_miss_latency::total 70484.749455 # average overall miss latency | 745system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency 746system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency 747system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency 748system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency 749system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency 750system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency |
| 751system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 752system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 753system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 754system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 755system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 756system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 757system.cpu.icache.fast_writes 0 # number of fast writes performed 758system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 763system.cpu.icache.overall_mshr_hits::cpu.inst 148 # number of overall MSHR hits 764system.cpu.icache.overall_mshr_hits::total 148 # number of overall MSHR hits 765system.cpu.icache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses 766system.cpu.icache.ReadReq_mshr_misses::total 311 # number of ReadReq MSHR misses 767system.cpu.icache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses 768system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses 769system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses 770system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses | 751system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 752system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 753system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 754system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 755system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 756system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 757system.cpu.icache.fast_writes 0 # number of fast writes performed 758system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 763system.cpu.icache.overall_mshr_hits::cpu.inst 148 # number of overall MSHR hits 764system.cpu.icache.overall_mshr_hits::total 148 # number of overall MSHR hits 765system.cpu.icache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses 766system.cpu.icache.ReadReq_mshr_misses::total 311 # number of ReadReq MSHR misses 767system.cpu.icache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses 768system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses 769system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses 770system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses |
| 771system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23859500 # number of ReadReq MSHR miss cycles 772system.cpu.icache.ReadReq_mshr_miss_latency::total 23859500 # number of ReadReq MSHR miss cycles 773system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23859500 # number of demand (read+write) MSHR miss cycles 774system.cpu.icache.demand_mshr_miss_latency::total 23859500 # number of demand (read+write) MSHR miss cycles 775system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23859500 # number of overall MSHR miss cycles 776system.cpu.icache.overall_mshr_miss_latency::total 23859500 # number of overall MSHR miss cycles | 771system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles 772system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles 773system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles 774system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles 775system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles 776system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles |
| 777system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses 778system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses 779system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses 780system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses 781system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses 782system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses | 777system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses 778system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses 779system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses 780system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses 781system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses 782system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses |
| 783system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76718.649518 # average ReadReq mshr miss latency 784system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76718.649518 # average ReadReq mshr miss latency 785system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency 786system.cpu.icache.demand_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency 787system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency 788system.cpu.icache.overall_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency | 783system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency 784system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency 785system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency 786system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency 787system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency 788system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency |
| 789system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 790system.cpu.l2cache.tags.replacements 0 # number of replacements 791system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use 792system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 793system.cpu.l2cache.tags.sampled_refs 409 # Sample count of references to valid blocks. 794system.cpu.l2cache.tags.avg_refs 0.002445 # Average number of references to valid blocks. 795system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 796system.cpu.l2cache.tags.occ_blocks::cpu.inst 157.816586 # Average occupied blocks per requestor --- 125 unchanged lines hidden (view full) --- 922system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency 923system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency 924system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency 925system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency 926system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency 927system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency 928system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency 929system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 789system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 790system.cpu.l2cache.tags.replacements 0 # number of replacements 791system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use 792system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 793system.cpu.l2cache.tags.sampled_refs 409 # Sample count of references to valid blocks. 794system.cpu.l2cache.tags.avg_refs 0.002445 # Average number of references to valid blocks. 795system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 796system.cpu.l2cache.tags.occ_blocks::cpu.inst 157.816586 # Average occupied blocks per requestor --- 125 unchanged lines hidden (view full) --- 922system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency 923system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency 924system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency 925system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency 926system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency 927system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency 928system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency 929system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 930system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. 931system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 932system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 933system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 934system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 935system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 930system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution 935system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes) 936system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes) 937system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 938system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes) 939system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 940system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 941system.cpu.toL2Bus.snoops 0 # Total snoops (count) 942system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram | 936system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 937system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 939system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution 941system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes) 943system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 944system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes) 945system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 946system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 947system.cpu.toL2Bus.snoops 0 # Total snoops (count) 948system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram |
| 943system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 944system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 949system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram |
| 945system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 951system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 946system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram | 952system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram |
| 948system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 954system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 950system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 956system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 951system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram 953system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) 954system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 955system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks) 956system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 957system.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks) 958system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) --- 25 unchanged lines hidden --- | 957system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram 959system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) 960system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 961system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks) 962system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 963system.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks) 964system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) --- 25 unchanged lines hidden --- |