| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 22074000 # Number of ticks simulated 5final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 94896 # Simulator instruction rate (inst/s) 8host_op_rate 94876 # Simulator op (including micro ops) rate (op/s) --- 555 unchanged lines hidden (view full) --- 564system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 566system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 567system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 568system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::total 6389 # Class of committed instruction 571system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 22074000 # Number of ticks simulated 5final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 94896 # Simulator instruction rate (inst/s) 8host_op_rate 94876 # Simulator op (including micro ops) rate (op/s) --- 555 unchanged lines hidden (view full) --- 564system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 566system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 567system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 568system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::total 6389 # Class of committed instruction 571system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached |
| 572system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 573system.cpu.rob.rob_reads 25491 # The number of ROB reads 574system.cpu.rob.rob_writes 27316 # The number of ROB writes 575system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself 576system.cpu.idleCycles 29964 # Total number of cycles that the CPU has spent unscheduled due to idling 577system.cpu.committedInsts 6372 # Number of Instructions Simulated 578system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 579system.cpu.cpi 6.928594 # CPI: Cycles Per Instruction 580system.cpu.cpi_total 6.928594 # CPI: Total CPI of All Threads --- 394 unchanged lines hidden --- | 572system.cpu.rob.rob_reads 25491 # The number of ROB reads 573system.cpu.rob.rob_writes 27316 # The number of ROB writes 574system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself 575system.cpu.idleCycles 29964 # Total number of cycles that the CPU has spent unscheduled due to idling 576system.cpu.committedInsts 6372 # Number of Instructions Simulated 577system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 578system.cpu.cpi 6.928594 # CPI: Cycles Per Instruction 579system.cpu.cpi_total 6.928594 # CPI: Total CPI of All Threads --- 394 unchanged lines hidden --- |