stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
---|---|
1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 20537500 # Number of ticks simulated 5final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 22074000 # Number of ticks simulated 5final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 92569 # Simulator instruction rate (inst/s) 8host_op_rate 92553 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 298254404 # Simulator tick rate (ticks/s) 10host_mem_usage 293992 # Number of bytes of host memory used | 7host_inst_rate 94896 # Simulator instruction rate (inst/s) 8host_op_rate 94876 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 328609283 # Simulator tick rate (ticks/s) 10host_mem_usage 293652 # Number of bytes of host memory used |
11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory | 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory |
17system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31168 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31104 # Number of bytes read from this memory |
19system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory | 19system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory |
22system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 487 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 975386488 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 542227632 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1517614121 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 975386488 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 975386488 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 975386488 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 542227632 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1517614121 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 487 # Number of read requests accepted | 22system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 486 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 907492978 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 501585576 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1409078554 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 907492978 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 907492978 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 907492978 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 501585576 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1409078554 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 486 # Number of read requests accepted |
33system.physmem.writeReqs 0 # Number of write requests accepted | 33system.physmem.writeReqs 0 # Number of write requests accepted |
34system.physmem.readBursts 487 # Number of DRAM read bursts, including those serviced by the write queue | 34system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue |
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
36system.physmem.bytesReadDRAM 31168 # Total number of bytes read from DRAM | 36system.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM |
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
39system.physmem.bytesReadSys 31168 # Total read bytes from the system interface side | 39system.physmem.bytesReadSys 31104 # Total read bytes from the system interface side |
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 69 # Per bank write bursts 45system.physmem.perBankRdBursts::1 33 # Per bank write bursts 46system.physmem.perBankRdBursts::2 32 # Per bank write bursts 47system.physmem.perBankRdBursts::3 47 # Per bank write bursts 48system.physmem.perBankRdBursts::4 42 # Per bank write bursts 49system.physmem.perBankRdBursts::5 20 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1 # Per bank write bursts 51system.physmem.perBankRdBursts::7 3 # Per bank write bursts 52system.physmem.perBankRdBursts::8 0 # Per bank write bursts 53system.physmem.perBankRdBursts::9 1 # Per bank write bursts | 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 69 # Per bank write bursts 45system.physmem.perBankRdBursts::1 33 # Per bank write bursts 46system.physmem.perBankRdBursts::2 32 # Per bank write bursts 47system.physmem.perBankRdBursts::3 47 # Per bank write bursts 48system.physmem.perBankRdBursts::4 42 # Per bank write bursts 49system.physmem.perBankRdBursts::5 20 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1 # Per bank write bursts 51system.physmem.perBankRdBursts::7 3 # Per bank write bursts 52system.physmem.perBankRdBursts::8 0 # Per bank write bursts 53system.physmem.perBankRdBursts::9 1 # Per bank write bursts |
54system.physmem.perBankRdBursts::10 23 # Per bank write bursts | 54system.physmem.perBankRdBursts::10 22 # Per bank write bursts |
55system.physmem.perBankRdBursts::11 25 # Per bank write bursts 56system.physmem.perBankRdBursts::12 14 # Per bank write bursts 57system.physmem.perBankRdBursts::13 120 # Per bank write bursts 58system.physmem.perBankRdBursts::14 45 # Per bank write bursts 59system.physmem.perBankRdBursts::15 12 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts --- 7 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 55system.physmem.perBankRdBursts::11 25 # Per bank write bursts 56system.physmem.perBankRdBursts::12 14 # Per bank write bursts 57system.physmem.perBankRdBursts::13 120 # Per bank write bursts 58system.physmem.perBankRdBursts::14 45 # Per bank write bursts 59system.physmem.perBankRdBursts::15 12 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts --- 7 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
78system.physmem.totGap 20412000 # Total gap between requests | 78system.physmem.totGap 21941500 # Total gap between requests |
79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) |
85system.physmem.readPktSize::6 487 # Read request sizes (log2) | 85system.physmem.readPktSize::6 486 # Read request sizes (log2) |
86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see | 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see |
94system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see |
97system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 97system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
189system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 341.853659 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 204.819475 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 342.253502 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 28 34.15% 34.15% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 20.73% 54.88% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 9 10.98% 65.85% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 8 9.76% 75.61% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 4.88% 80.49% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 1.22% 81.71% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation 203system.physmem.totQLat 4742750 # Total ticks spent queuing 204system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst | 189system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 207.818416 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 321.662840 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation 202system.physmem.totQLat 4363750 # Total ticks spent queuing 203system.physmem.totMemAccLat 13476250 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers 205system.physmem.avgQLat 8978.91 # Average queueing delay per DRAM burst |
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
208system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s | 207system.physmem.avgMemAccLat 27728.91 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 1409.08 # Average DRAM read bandwidth in MiByte/s |
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
211system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s | 210system.physmem.avgRdBWSys 1409.08 # Average system read bandwidth in MiByte/s |
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
214system.physmem.busUtil 11.86 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.86 # Data bus utilization in percentage for reads | 213system.physmem.busUtil 11.01 # Data bus utilization in percentage 214system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads |
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
217system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing | 216system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing |
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 390 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 390 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
221system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads | 220system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads |
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
223system.physmem.avgGap 41913.76 # Average gap between requests 224system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 1755000 # Energy for read commands per rank (pJ) | 222system.physmem.avgGap 45147.12 # Average gap between requests 223system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined 224system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) 225system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) 226system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) |
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 227system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
230system.physmem_0.actBackEnergy 10809765 # Energy for active background per rank (pJ) | 229system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) |
231system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) | 230system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) |
232system.physmem_0.totalEnergy 13982370 # Total energy per rank (pJ) 233system.physmem_0.averagePower 881.195525 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 22000 # Time in different power states | 231system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) 232system.physmem_0.averagePower 873.750829 # Core power per rank (mW) 233system.physmem_0.memoryStateTime::IDLE 118250 # Time in different power states |
235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 234system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 235system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
237system.physmem_0.memoryStateTime::ACT 15339250 # Time in different power states | 236system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states |
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
239system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1365000 # Energy for read commands per rank (pJ) | 238system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) 239system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) 240system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) |
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 241system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
244system.physmem_1.actBackEnergy 10541295 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 252750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 13690305 # Total energy per rank (pJ) 247system.physmem_1.averagePower 864.696352 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 637250 # Time in different power states | 243system.physmem_1.actBackEnergy 10123200 # Energy for active background per rank (pJ) 244system.physmem_1.preBackEnergy 619500 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 13518075 # Total energy per rank (pJ) 246system.physmem_1.averagePower 853.818096 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 963500 # Time in different power states |
249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 248system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
251system.physmem_1.memoryStateTime::ACT 14974750 # Time in different power states | 250system.physmem_1.memoryStateTime::ACT 14362750 # Time in different power states |
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
253system.cpu.branchPred.lookups 2806 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted | 252system.cpu.branchPred.lookups 2808 # Number of BP lookups 253system.cpu.branchPred.condPredicted 1660 # Number of conditional branches predicted |
255system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups | 254system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups |
257system.cpu.branchPred.BTBHits 686 # Number of BTB hits | 256system.cpu.branchPred.BTBHits 676 # Number of BTB hits |
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
259system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. | 258system.cpu.branchPred.BTBHitPct 32.007576 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 398 # Number of times the RAS was used to get a target. |
261system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dtb.fetch_hits 0 # ITB hits 264system.cpu.dtb.fetch_misses 0 # ITB misses 265system.cpu.dtb.fetch_acv 0 # ITB acv 266system.cpu.dtb.fetch_accesses 0 # ITB accesses | 260system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. 261system.cpu_clk_domain.clock 500 # Clock period in ticks 262system.cpu.dtb.fetch_hits 0 # ITB hits 263system.cpu.dtb.fetch_misses 0 # ITB misses 264system.cpu.dtb.fetch_acv 0 # ITB acv 265system.cpu.dtb.fetch_accesses 0 # ITB accesses |
267system.cpu.dtb.read_hits 2085 # DTB read hits 268system.cpu.dtb.read_misses 55 # DTB read misses | 266system.cpu.dtb.read_hits 2105 # DTB read hits 267system.cpu.dtb.read_misses 56 # DTB read misses |
269system.cpu.dtb.read_acv 0 # DTB read access violations | 268system.cpu.dtb.read_acv 0 # DTB read access violations |
270system.cpu.dtb.read_accesses 2140 # DTB read accesses 271system.cpu.dtb.write_hits 1069 # DTB write hits | 269system.cpu.dtb.read_accesses 2161 # DTB read accesses 270system.cpu.dtb.write_hits 1074 # DTB write hits |
272system.cpu.dtb.write_misses 30 # DTB write misses 273system.cpu.dtb.write_acv 0 # DTB write access violations | 271system.cpu.dtb.write_misses 30 # DTB write misses 272system.cpu.dtb.write_acv 0 # DTB write access violations |
274system.cpu.dtb.write_accesses 1099 # DTB write accesses 275system.cpu.dtb.data_hits 3154 # DTB hits 276system.cpu.dtb.data_misses 85 # DTB misses | 273system.cpu.dtb.write_accesses 1104 # DTB write accesses 274system.cpu.dtb.data_hits 3179 # DTB hits 275system.cpu.dtb.data_misses 86 # DTB misses |
277system.cpu.dtb.data_acv 0 # DTB access violations | 276system.cpu.dtb.data_acv 0 # DTB access violations |
278system.cpu.dtb.data_accesses 3239 # DTB accesses 279system.cpu.itb.fetch_hits 2196 # ITB hits 280system.cpu.itb.fetch_misses 38 # ITB misses | 277system.cpu.dtb.data_accesses 3265 # DTB accesses 278system.cpu.itb.fetch_hits 2195 # ITB hits 279system.cpu.itb.fetch_misses 34 # ITB misses |
281system.cpu.itb.fetch_acv 0 # ITB acv | 280system.cpu.itb.fetch_acv 0 # ITB acv |
282system.cpu.itb.fetch_accesses 2234 # ITB accesses | 281system.cpu.itb.fetch_accesses 2229 # ITB accesses |
283system.cpu.itb.read_hits 0 # DTB read hits 284system.cpu.itb.read_misses 0 # DTB read misses 285system.cpu.itb.read_acv 0 # DTB read access violations 286system.cpu.itb.read_accesses 0 # DTB read accesses 287system.cpu.itb.write_hits 0 # DTB write hits 288system.cpu.itb.write_misses 0 # DTB write misses 289system.cpu.itb.write_acv 0 # DTB write access violations 290system.cpu.itb.write_accesses 0 # DTB write accesses 291system.cpu.itb.data_hits 0 # DTB hits 292system.cpu.itb.data_misses 0 # DTB misses 293system.cpu.itb.data_acv 0 # DTB access violations 294system.cpu.itb.data_accesses 0 # DTB accesses 295system.cpu.workload.num_syscalls 17 # Number of system calls | 282system.cpu.itb.read_hits 0 # DTB read hits 283system.cpu.itb.read_misses 0 # DTB read misses 284system.cpu.itb.read_acv 0 # DTB read access violations 285system.cpu.itb.read_accesses 0 # DTB read accesses 286system.cpu.itb.write_hits 0 # DTB write hits 287system.cpu.itb.write_misses 0 # DTB write misses 288system.cpu.itb.write_acv 0 # DTB write access violations 289system.cpu.itb.write_accesses 0 # DTB write accesses 290system.cpu.itb.data_hits 0 # DTB hits 291system.cpu.itb.data_misses 0 # DTB misses 292system.cpu.itb.data_acv 0 # DTB access violations 293system.cpu.itb.data_accesses 0 # DTB accesses 294system.cpu.workload.num_syscalls 17 # Number of system calls |
296system.cpu.numCycles 41076 # number of cpu cycles simulated | 295system.cpu.numCycles 44149 # number of cpu cycles simulated |
297system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 298system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 296system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 297system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
299system.cpu.fetch.icacheStallCycles 8744 # Number of cycles fetch is stalled on an Icache miss 300system.cpu.fetch.Insts 16221 # Number of instructions fetch has processed 301system.cpu.fetch.Branches 2806 # Number of branches that fetch encountered 302system.cpu.fetch.predictedBranches 1081 # Number of branches that fetch has predicted taken 303system.cpu.fetch.Cycles 4165 # Number of cycles fetch has run and was not squashing or blocked | 298system.cpu.fetch.icacheStallCycles 8603 # Number of cycles fetch is stalled on an Icache miss 299system.cpu.fetch.Insts 16272 # Number of instructions fetch has processed 300system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered 301system.cpu.fetch.predictedBranches 1074 # Number of branches that fetch has predicted taken 302system.cpu.fetch.Cycles 4302 # Number of cycles fetch has run and was not squashing or blocked |
304system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing 305system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 303system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing 304system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
306system.cpu.fetch.PendingTrapStallCycles 801 # Number of stall cycles due to pending traps 307system.cpu.fetch.CacheLines 2196 # Number of cache lines fetched 308system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed 309system.cpu.fetch.rateDist::samples 14255 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::mean 1.137917 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::stdev 2.547719 # Number of instructions fetched each cycle (Total) | 305system.cpu.fetch.PendingTrapStallCycles 735 # Number of stall cycles due to pending traps 306system.cpu.fetch.CacheLines 2195 # Number of cache lines fetched 307system.cpu.fetch.IcacheSquashes 341 # Number of outstanding Icache misses that were squashed 308system.cpu.fetch.rateDist::samples 14185 # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::mean 1.147127 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::stdev 2.556854 # Number of instructions fetched each cycle (Total) |
312system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 311system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
313system.cpu.fetch.rateDist::0 11405 80.01% 80.01% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::1 289 2.03% 82.03% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::2 215 1.51% 83.54% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::3 201 1.41% 84.95% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::4 243 1.70% 86.66% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::5 210 1.47% 88.13% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::6 240 1.68% 89.81% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::7 179 1.26% 91.07% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::8 1273 8.93% 100.00% # Number of instructions fetched each cycle (Total) | 312system.cpu.fetch.rateDist::0 11330 79.87% 79.87% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::1 287 2.02% 81.90% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::2 214 1.51% 83.41% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::4 242 1.71% 86.55% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::5 209 1.47% 88.02% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::6 241 1.70% 89.72% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::7 178 1.25% 90.98% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::8 1280 9.02% 100.00% # Number of instructions fetched each cycle (Total) |
322system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 321system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
325system.cpu.fetch.rateDist::total 14255 # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.branchRate 0.068312 # Number of branch fetches per cycle 327system.cpu.fetch.rate 0.394902 # Number of inst fetches per cycle 328system.cpu.decode.IdleCycles 8821 # Number of cycles decode is idle 329system.cpu.decode.BlockedCycles 2387 # Number of cycles decode is blocked 330system.cpu.decode.RunCycles 2410 # Number of cycles decode is running 331system.cpu.decode.UnblockCycles 194 # Number of cycles decode is unblocking | 324system.cpu.fetch.rateDist::total 14185 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.branchRate 0.063603 # Number of branch fetches per cycle 326system.cpu.fetch.rate 0.368570 # Number of inst fetches per cycle 327system.cpu.decode.IdleCycles 8626 # Number of cycles decode is idle 328system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked 329system.cpu.decode.RunCycles 2413 # Number of cycles decode is running 330system.cpu.decode.UnblockCycles 199 # Number of cycles decode is unblocking |
332system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing | 331system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing |
333system.cpu.decode.BranchResolved 229 # Number of times decode resolved a branch 334system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction 335system.cpu.decode.DecodedInsts 14785 # Number of instructions handled by decode | 332system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch 333system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction 334system.cpu.decode.DecodedInsts 14877 # Number of instructions handled by decode |
336system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode 337system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing | 335system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode 336system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing |
338system.cpu.rename.IdleCycles 8987 # Number of cycles rename is idle 339system.cpu.rename.BlockCycles 1032 # Number of cycles rename is blocking 340system.cpu.rename.serializeStallCycles 429 # count of cycles rename stalled for serializing inst | 337system.cpu.rename.IdleCycles 8799 # Number of cycles rename is idle 338system.cpu.rename.BlockCycles 1077 # Number of cycles rename is blocking 339system.cpu.rename.serializeStallCycles 424 # count of cycles rename stalled for serializing inst |
341system.cpu.rename.RunCycles 2422 # Number of cycles rename is running | 340system.cpu.rename.RunCycles 2422 # Number of cycles rename is running |
342system.cpu.rename.UnblockCycles 942 # Number of cycles rename is unblocking 343system.cpu.rename.RenamedInsts 14195 # Number of instructions processed by rename 344system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full 345system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 346system.cpu.rename.LQFullEvents 42 # Number of times rename has blocked due to LQ full 347system.cpu.rename.SQFullEvents 850 # Number of times rename has blocked due to SQ full 348system.cpu.rename.RenamedOperands 10723 # Number of destination operands rename has renamed 349system.cpu.rename.RenameLookups 17814 # Number of register rename lookups that rename has made 350system.cpu.rename.int_rename_lookups 17805 # Number of integer rename lookups | 341system.cpu.rename.UnblockCycles 1020 # Number of cycles rename is unblocking 342system.cpu.rename.RenamedInsts 14259 # Number of instructions processed by rename 343system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full 344system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full 345system.cpu.rename.LQFullEvents 32 # Number of times rename has blocked due to LQ full 346system.cpu.rename.SQFullEvents 922 # Number of times rename has blocked due to SQ full 347system.cpu.rename.RenamedOperands 10782 # Number of destination operands rename has renamed 348system.cpu.rename.RenameLookups 17904 # Number of register rename lookups that rename has made 349system.cpu.rename.int_rename_lookups 17895 # Number of integer rename lookups |
351system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 352system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed | 350system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 351system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed |
353system.cpu.rename.UndoneMaps 6153 # Number of HB maps that are undone due to squashing | 352system.cpu.rename.UndoneMaps 6212 # Number of HB maps that are undone due to squashing |
354system.cpu.rename.serializingInsts 32 # count of serializing insts renamed 355system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed | 353system.cpu.rename.serializingInsts 32 # count of serializing insts renamed 354system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed |
356system.cpu.rename.skidInsts 504 # count of insts added to the skid buffer 357system.cpu.memDep0.insertedLoads 2660 # Number of loads inserted to the mem dependence unit. 358system.cpu.memDep0.insertedStores 1309 # Number of stores inserted to the mem dependence unit. 359system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. | 355system.cpu.rename.skidInsts 534 # count of insts added to the skid buffer 356system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. 357system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. 358system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. |
360system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 359system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
361system.cpu.iq.iqInstsAdded 12882 # Number of instructions added to the IQ (excludes non-spec) | 360system.cpu.iq.iqInstsAdded 12936 # Number of instructions added to the IQ (excludes non-spec) |
362system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ | 361system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ |
363system.cpu.iq.iqInstsIssued 10718 # Number of instructions issued 364system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued 365system.cpu.iq.iqSquashedInstsExamined 6142 # Number of squashed instructions iterated over during squash; mainly for profiling 366system.cpu.iq.iqSquashedOperandsExamined 3483 # Number of squashed operands that are examined and possibly removed from graph | 362system.cpu.iq.iqInstsIssued 10742 # Number of instructions issued 363system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued 364system.cpu.iq.iqSquashedInstsExamined 6197 # Number of squashed instructions iterated over during squash; mainly for profiling 365system.cpu.iq.iqSquashedOperandsExamined 3553 # Number of squashed operands that are examined and possibly removed from graph |
367system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed | 366system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed |
368system.cpu.iq.issued_per_cycle::samples 14255 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::mean 0.751877 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::stdev 1.485144 # Number of insts issued each cycle | 367system.cpu.iq.issued_per_cycle::samples 14185 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::mean 0.757279 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::stdev 1.490412 # Number of insts issued each cycle |
371system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 370system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
372system.cpu.iq.issued_per_cycle::0 10249 71.90% 71.90% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::1 1278 8.97% 80.86% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::2 900 6.31% 87.18% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::3 686 4.81% 91.99% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::4 522 3.66% 95.65% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::5 330 2.31% 97.97% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::6 212 1.49% 99.45% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::7 52 0.36% 99.82% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle | 371system.cpu.iq.issued_per_cycle::0 10181 71.77% 71.77% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::1 1265 8.92% 80.69% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::2 910 6.42% 87.11% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::3 677 4.77% 91.88% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::4 530 3.74% 95.62% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::5 330 2.33% 97.94% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::6 213 1.50% 99.44% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::7 54 0.38% 99.82% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::8 25 0.18% 100.00% # Number of insts issued each cycle |
381system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 380system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
384system.cpu.iq.issued_per_cycle::total 14255 # Number of insts issued each cycle | 383system.cpu.iq.issued_per_cycle::total 14185 # Number of insts issued each cycle |
385system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 384system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
386system.cpu.iq.fu_full::IntAlu 30 20.69% 20.69% # attempts to use FU when none available 387system.cpu.iq.fu_full::IntMult 0 0.00% 20.69% # attempts to use FU when none available 388system.cpu.iq.fu_full::IntDiv 0 0.00% 20.69% # attempts to use FU when none available 389system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.69% # attempts to use FU when none available 390system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.69% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.69% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatMult 0 0.00% 20.69% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.69% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.69% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.69% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.69% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.69% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.69% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.69% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.69% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdMult 0 0.00% 20.69% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.69% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdShift 0 0.00% 20.69% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.69% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.69% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.69% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.69% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.69% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.69% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.69% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.69% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.69% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.69% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.69% # attempts to use FU when none available 415system.cpu.iq.fu_full::MemRead 73 50.34% 71.03% # attempts to use FU when none available 416system.cpu.iq.fu_full::MemWrite 42 28.97% 100.00% # attempts to use FU when none available | 385system.cpu.iq.fu_full::IntAlu 29 19.86% 19.86% # attempts to use FU when none available 386system.cpu.iq.fu_full::IntMult 0 0.00% 19.86% # attempts to use FU when none available 387system.cpu.iq.fu_full::IntDiv 0 0.00% 19.86% # attempts to use FU when none available 388system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.86% # attempts to use FU when none available 389system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.86% # attempts to use FU when none available 390system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.86% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatMult 0 0.00% 19.86% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.86% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.86% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.86% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.86% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.86% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.86% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.86% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.86% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdMult 0 0.00% 19.86% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.86% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdShift 0 0.00% 19.86% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.86% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.86% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.86% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.86% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.86% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.86% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.86% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.86% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.86% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.86% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.86% # attempts to use FU when none available 414system.cpu.iq.fu_full::MemRead 74 50.68% 70.55% # attempts to use FU when none available 415system.cpu.iq.fu_full::MemWrite 43 29.45% 100.00% # attempts to use FU when none available |
417system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 418system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 419system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued | 416system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 417system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 418system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued |
420system.cpu.iq.FU_type_0::IntAlu 7258 67.72% 67.74% # Type of FU issued 421system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.75% # Type of FU issued 422system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.75% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 449system.cpu.iq.FU_type_0::MemRead 2331 21.75% 89.51% # Type of FU issued 450system.cpu.iq.FU_type_0::MemWrite 1124 10.49% 100.00% # Type of FU issued | 419system.cpu.iq.FU_type_0::IntAlu 7248 67.47% 67.49% # Type of FU issued 420system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued 421system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued 422system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued 423system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued 424system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued 448system.cpu.iq.FU_type_0::MemRead 2358 21.95% 89.47% # Type of FU issued 449system.cpu.iq.FU_type_0::MemWrite 1131 10.53% 100.00% # Type of FU issued |
451system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 452system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 450system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 451system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
453system.cpu.iq.FU_type_0::total 10718 # Type of FU issued 454system.cpu.iq.rate 0.260931 # Inst issue rate 455system.cpu.iq.fu_busy_cnt 145 # FU busy when requested 456system.cpu.iq.fu_busy_rate 0.013529 # FU busy rate (busy events/executed inst) 457system.cpu.iq.int_inst_queue_reads 35836 # Number of integer instruction queue reads 458system.cpu.iq.int_inst_queue_writes 19060 # Number of integer instruction queue writes 459system.cpu.iq.int_inst_queue_wakeup_accesses 9783 # Number of integer instruction queue wakeup accesses | 452system.cpu.iq.FU_type_0::total 10742 # Type of FU issued 453system.cpu.iq.rate 0.243312 # Inst issue rate 454system.cpu.iq.fu_busy_cnt 146 # FU busy when requested 455system.cpu.iq.fu_busy_rate 0.013592 # FU busy rate (busy events/executed inst) 456system.cpu.iq.int_inst_queue_reads 35814 # Number of integer instruction queue reads 457system.cpu.iq.int_inst_queue_writes 19169 # Number of integer instruction queue writes 458system.cpu.iq.int_inst_queue_wakeup_accesses 9787 # Number of integer instruction queue wakeup accesses |
460system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 461system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 462system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses | 459system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 460system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 461system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses |
463system.cpu.iq.int_alu_accesses 10850 # Number of integer alu accesses | 462system.cpu.iq.int_alu_accesses 10875 # Number of integer alu accesses |
464system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses | 463system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses |
465system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores | 464system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores |
466system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 465system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
467system.cpu.iew.lsq.thread0.squashedLoads 1477 # Number of loads squashed | 466system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed |
468system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 469system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations | 467system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 468system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations |
470system.cpu.iew.lsq.thread0.squashedStores 444 # Number of stores squashed | 469system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed |
471system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 472system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 473system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 470system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 471system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 472system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
474system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked | 473system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked |
475system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 476system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing | 474system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 475system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing |
477system.cpu.iew.iewBlockCycles 1002 # Number of cycles IEW is blocking 478system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking 479system.cpu.iew.iewDispatchedInsts 12999 # Number of instructions dispatched to IQ 480system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch 481system.cpu.iew.iewDispLoadInsts 2660 # Number of dispatched load instructions 482system.cpu.iew.iewDispStoreInsts 1309 # Number of dispatched store instructions | 476system.cpu.iew.iewBlockCycles 1035 # Number of cycles IEW is blocking 477system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking 478system.cpu.iew.iewDispatchedInsts 13050 # Number of instructions dispatched to IQ 479system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch 480system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions 481system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions |
483system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions | 482system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions |
484system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 485system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall | 483system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 484system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall |
486system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations | 485system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations |
487system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly | 486system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly |
488system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly | 487system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly |
489system.cpu.iew.branchMispredicts 470 # Number of branch mispredicts detected at execute 490system.cpu.iew.iewExecutedInsts 10224 # Number of executed instructions 491system.cpu.iew.iewExecLoadInsts 2143 # Number of load instructions executed | 488system.cpu.iew.branchMispredicts 472 # Number of branch mispredicts detected at execute 489system.cpu.iew.iewExecutedInsts 10248 # Number of executed instructions 490system.cpu.iew.iewExecLoadInsts 2164 # Number of load instructions executed |
492system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute 493system.cpu.iew.exec_swp 0 # number of swp insts executed | 491system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute 492system.cpu.iew.exec_swp 0 # number of swp insts executed |
494system.cpu.iew.exec_nop 89 # number of nop insts executed 495system.cpu.iew.exec_refs 3244 # number of memory reference insts executed 496system.cpu.iew.exec_branches 1603 # Number of branches executed 497system.cpu.iew.exec_stores 1101 # Number of stores executed 498system.cpu.iew.exec_rate 0.248904 # Inst execution rate 499system.cpu.iew.wb_sent 9953 # cumulative count of insts sent to commit 500system.cpu.iew.wb_count 9793 # cumulative count of insts written-back 501system.cpu.iew.wb_producers 5300 # num instructions producing a value 502system.cpu.iew.wb_consumers 7279 # num instructions consuming a value | 493system.cpu.iew.exec_nop 86 # number of nop insts executed 494system.cpu.iew.exec_refs 3270 # number of memory reference insts executed 495system.cpu.iew.exec_branches 1599 # Number of branches executed 496system.cpu.iew.exec_stores 1106 # Number of stores executed 497system.cpu.iew.exec_rate 0.232123 # Inst execution rate 498system.cpu.iew.wb_sent 9960 # cumulative count of insts sent to commit 499system.cpu.iew.wb_count 9797 # cumulative count of insts written-back 500system.cpu.iew.wb_producers 5308 # num instructions producing a value 501system.cpu.iew.wb_consumers 7306 # num instructions consuming a value |
503system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 502system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
504system.cpu.iew.wb_rate 0.238412 # insts written-back per cycle 505system.cpu.iew.wb_fanout 0.728122 # average fanout of values written-back | 503system.cpu.iew.wb_rate 0.221908 # insts written-back per cycle 504system.cpu.iew.wb_fanout 0.726526 # average fanout of values written-back |
506system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 505system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
507system.cpu.commit.commitSquashedInsts 6609 # The number of squashed insts skipped by commit | 506system.cpu.commit.commitSquashedInsts 6660 # The number of squashed insts skipped by commit |
508system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 509system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted | 507system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 508system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted |
510system.cpu.commit.committed_per_cycle::samples 13051 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::mean 0.489541 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::stdev 1.404135 # Number of insts commited each cycle | 509system.cpu.commit.committed_per_cycle::samples 12983 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::mean 0.492105 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::stdev 1.404730 # Number of insts commited each cycle |
513system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 512system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
514system.cpu.commit.committed_per_cycle::0 10600 81.22% 81.22% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::1 1162 8.90% 90.12% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::2 501 3.84% 93.96% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::3 211 1.62% 95.58% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::4 133 1.02% 96.60% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::5 75 0.57% 97.17% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::6 89 0.68% 97.85% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::7 89 0.68% 98.54% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::8 191 1.46% 100.00% # Number of insts commited each cycle | 513system.cpu.commit.committed_per_cycle::0 10525 81.07% 81.07% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::1 1166 8.98% 90.05% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::2 505 3.89% 93.94% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::4 137 1.06% 96.60% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::5 75 0.58% 97.18% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle |
523system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 522system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
526system.cpu.commit.committed_per_cycle::total 13051 # Number of insts commited each cycle | 525system.cpu.commit.committed_per_cycle::total 12983 # Number of insts commited each cycle |
527system.cpu.commit.committedInsts 6389 # Number of instructions committed 528system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 529system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 530system.cpu.commit.refs 2048 # Number of memory references committed 531system.cpu.commit.loads 1183 # Number of loads committed 532system.cpu.commit.membars 0 # Number of memory barriers committed 533system.cpu.commit.branches 1050 # Number of branches committed 534system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 564system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 567system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 568system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 571system.cpu.commit.op_class_0::total 6389 # Class of committed instruction | 526system.cpu.commit.committedInsts 6389 # Number of instructions committed 527system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 528system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 529system.cpu.commit.refs 2048 # Number of memory references committed 530system.cpu.commit.loads 1183 # Number of loads committed 531system.cpu.commit.membars 0 # Number of memory barriers committed 532system.cpu.commit.branches 1050 # Number of branches committed 533system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 563system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 566system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 567system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 568system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::total 6389 # Class of committed instruction |
572system.cpu.commit.bw_lim_events 191 # number cycles where commit BW limit reached | 571system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached |
573system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 572system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
574system.cpu.rob.rob_reads 25507 # The number of ROB reads 575system.cpu.rob.rob_writes 27214 # The number of ROB writes 576system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself 577system.cpu.idleCycles 26821 # Total number of cycles that the CPU has spent unscheduled due to idling | 573system.cpu.rob.rob_reads 25491 # The number of ROB reads 574system.cpu.rob.rob_writes 27316 # The number of ROB writes 575system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself 576system.cpu.idleCycles 29964 # Total number of cycles that the CPU has spent unscheduled due to idling |
578system.cpu.committedInsts 6372 # Number of Instructions Simulated 579system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated | 577system.cpu.committedInsts 6372 # Number of Instructions Simulated 578system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated |
580system.cpu.cpi 6.446328 # CPI: Cycles Per Instruction 581system.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads 582system.cpu.ipc 0.155127 # IPC: Instructions Per Cycle 583system.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads 584system.cpu.int_regfile_reads 12992 # number of integer regfile reads 585system.cpu.int_regfile_writes 7455 # number of integer regfile writes | 579system.cpu.cpi 6.928594 # CPI: Cycles Per Instruction 580system.cpu.cpi_total 6.928594 # CPI: Total CPI of All Threads 581system.cpu.ipc 0.144329 # IPC: Instructions Per Cycle 582system.cpu.ipc_total 0.144329 # IPC: Total IPC of All Threads 583system.cpu.int_regfile_reads 13019 # number of integer regfile reads 584system.cpu.int_regfile_writes 7461 # number of integer regfile writes |
586system.cpu.fp_regfile_reads 8 # number of floating regfile reads 587system.cpu.fp_regfile_writes 2 # number of floating regfile writes 588system.cpu.misc_regfile_reads 1 # number of misc regfile reads 589system.cpu.misc_regfile_writes 1 # number of misc regfile writes 590system.cpu.dcache.tags.replacements 0 # number of replacements | 585system.cpu.fp_regfile_reads 8 # number of floating regfile reads 586system.cpu.fp_regfile_writes 2 # number of floating regfile writes 587system.cpu.misc_regfile_reads 1 # number of misc regfile reads 588system.cpu.misc_regfile_writes 1 # number of misc regfile writes 589system.cpu.dcache.tags.replacements 0 # number of replacements |
591system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use 592system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. 593system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. 594system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. | 590system.cpu.dcache.tags.tagsinuse 107.596270 # Cycle average of tags in use 591system.cpu.dcache.tags.total_refs 2347 # Total number of references to valid blocks. 592system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. 593system.cpu.dcache.tags.avg_refs 13.566474 # Average number of references to valid blocks. |
595system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 594system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
596system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor 597system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy 598system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy 599system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id 600system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 601system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 602system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id 603system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses 604system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses 605system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits 606system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits 607system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 608system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 609system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits 610system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits 611system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits 612system.cpu.dcache.overall_hits::total 2314 # number of overall hits 613system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses 614system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses 615system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 616system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 617system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses 618system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses 619system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses 620system.cpu.dcache.overall_misses::total 522 # number of overall misses 621system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles 622system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles 623system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles 625system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles 626system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles 627system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles 628system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles 629system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) 630system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) | 595system.cpu.dcache.tags.occ_blocks::cpu.data 107.596270 # Average occupied blocks per requestor 596system.cpu.dcache.tags.occ_percent::cpu.data 0.026269 # Average percentage of cache occupancy 597system.cpu.dcache.tags.occ_percent::total 0.026269 # Average percentage of cache occupancy 598system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 599system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 600system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id 601system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id 602system.cpu.dcache.tags.tag_accesses 5893 # Number of tag accesses 603system.cpu.dcache.tags.data_accesses 5893 # Number of data accesses 604system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits 605system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits 606system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits 607system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits 608system.cpu.dcache.demand_hits::cpu.data 2347 # number of demand (read+write) hits 609system.cpu.dcache.demand_hits::total 2347 # number of demand (read+write) hits 610system.cpu.dcache.overall_hits::cpu.data 2347 # number of overall hits 611system.cpu.dcache.overall_hits::total 2347 # number of overall hits 612system.cpu.dcache.ReadReq_misses::cpu.data 157 # number of ReadReq misses 613system.cpu.dcache.ReadReq_misses::total 157 # number of ReadReq misses 614system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses 615system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses 616system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses 617system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses 618system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses 619system.cpu.dcache.overall_misses::total 513 # number of overall misses 620system.cpu.dcache.ReadReq_miss_latency::cpu.data 12056250 # number of ReadReq miss cycles 621system.cpu.dcache.ReadReq_miss_latency::total 12056250 # number of ReadReq miss cycles 622system.cpu.dcache.WriteReq_miss_latency::cpu.data 24043225 # number of WriteReq miss cycles 623system.cpu.dcache.WriteReq_miss_latency::total 24043225 # number of WriteReq miss cycles 624system.cpu.dcache.demand_miss_latency::cpu.data 36099475 # number of demand (read+write) miss cycles 625system.cpu.dcache.demand_miss_latency::total 36099475 # number of demand (read+write) miss cycles 626system.cpu.dcache.overall_miss_latency::cpu.data 36099475 # number of overall miss cycles 627system.cpu.dcache.overall_miss_latency::total 36099475 # number of overall miss cycles 628system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) 629system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) |
631system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 632system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) | 630system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 631system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) |
633system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses 634system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses 635system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses 636system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses 637system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses 638system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses 639system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 640system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 641system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses 642system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses 643system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses 644system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses 645system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency 646system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency 647system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency 648system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency 649system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency 650system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency 651system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency 652system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency 653system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked | 632system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses 633system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses 634system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses 635system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses 636system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078697 # miss rate for ReadReq accesses 637system.cpu.dcache.ReadReq_miss_rate::total 0.078697 # miss rate for ReadReq accesses 638system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses 639system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses 640system.cpu.dcache.demand_miss_rate::cpu.data 0.179371 # miss rate for demand accesses 641system.cpu.dcache.demand_miss_rate::total 0.179371 # miss rate for demand accesses 642system.cpu.dcache.overall_miss_rate::cpu.data 0.179371 # miss rate for overall accesses 643system.cpu.dcache.overall_miss_rate::total 0.179371 # miss rate for overall accesses 644system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76791.401274 # average ReadReq miss latency 645system.cpu.dcache.ReadReq_avg_miss_latency::total 76791.401274 # average ReadReq miss latency 646system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67537.148876 # average WriteReq miss latency 647system.cpu.dcache.WriteReq_avg_miss_latency::total 67537.148876 # average WriteReq miss latency 648system.cpu.dcache.demand_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency 649system.cpu.dcache.demand_avg_miss_latency::total 70369.346979 # average overall miss latency 650system.cpu.dcache.overall_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency 651system.cpu.dcache.overall_avg_miss_latency::total 70369.346979 # average overall miss latency 652system.cpu.dcache.blocked_cycles::no_mshrs 2245 # number of cycles access was blocked |
654system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 653system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
655system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked | 654system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked |
656system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 655system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
657system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked | 656system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.078947 # average number of cycles each access was blocked |
658system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.dcache.fast_writes 0 # number of fast writes performed 660system.cpu.dcache.cache_copies 0 # number of cache copies performed | 657system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.cpu.dcache.fast_writes 0 # number of fast writes performed 659system.cpu.dcache.cache_copies 0 # number of cache copies performed |
661system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 662system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits 663system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 664system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 665system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits 666system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits 667system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits 668system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits 669system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 670system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses | 660system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits 661system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits 662system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits 663system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits 664system.cpu.dcache.demand_mshr_hits::cpu.data 340 # number of demand (read+write) MSHR hits 665system.cpu.dcache.demand_mshr_hits::total 340 # number of demand (read+write) MSHR hits 666system.cpu.dcache.overall_mshr_hits::cpu.data 340 # number of overall MSHR hits 667system.cpu.dcache.overall_mshr_hits::total 340 # number of overall MSHR hits 668system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 669system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses |
671system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 672system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses | 670system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 671system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses |
673system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 674system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 675system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 676system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 677system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles 678system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles 679system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles 680system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles 681system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles 682system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles 683system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles 684system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles 685system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses 686system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses | 672system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 673system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 674system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 675system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses 676system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8557250 # number of ReadReq MSHR miss cycles 677system.cpu.dcache.ReadReq_mshr_miss_latency::total 8557250 # number of ReadReq MSHR miss cycles 678system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5645250 # number of WriteReq MSHR miss cycles 679system.cpu.dcache.WriteReq_mshr_miss_latency::total 5645250 # number of WriteReq MSHR miss cycles 680system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14202500 # number of demand (read+write) MSHR miss cycles 681system.cpu.dcache.demand_mshr_miss_latency::total 14202500 # number of demand (read+write) MSHR miss cycles 682system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14202500 # number of overall MSHR miss cycles 683system.cpu.dcache.overall_mshr_miss_latency::total 14202500 # number of overall MSHR miss cycles 684system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050627 # mshr miss rate for ReadReq accesses 685system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050627 # mshr miss rate for ReadReq accesses |
687system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 688system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses | 686system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 687system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses |
689system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses 690system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses 691system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses 692system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses 693system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency 694system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency 695system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency 696system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency 697system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency 698system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency 699system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency 700system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency | 688system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for demand accesses 689system.cpu.dcache.demand_mshr_miss_rate::total 0.060490 # mshr miss rate for demand accesses 690system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for overall accesses 691system.cpu.dcache.overall_mshr_miss_rate::total 0.060490 # mshr miss rate for overall accesses 692system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84725.247525 # average ReadReq mshr miss latency 693system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84725.247525 # average ReadReq mshr miss latency 694system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78406.250000 # average WriteReq mshr miss latency 695system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78406.250000 # average WriteReq mshr miss latency 696system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency 697system.cpu.dcache.demand_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency 698system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency 699system.cpu.dcache.overall_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency |
701system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 702system.cpu.icache.tags.replacements 0 # number of replacements | 700system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 701system.cpu.icache.tags.replacements 0 # number of replacements |
703system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use 704system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. | 702system.cpu.icache.tags.tagsinuse 158.400693 # Cycle average of tags in use 703system.cpu.icache.tags.total_refs 1716 # Total number of references to valid blocks. |
705system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. | 704system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. |
706system.cpu.icache.tags.avg_refs 5.471338 # Average number of references to valid blocks. | 705system.cpu.icache.tags.avg_refs 5.464968 # Average number of references to valid blocks. |
707system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 706system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
708system.cpu.icache.tags.occ_blocks::cpu.inst 158.374396 # Average occupied blocks per requestor 709system.cpu.icache.tags.occ_percent::cpu.inst 0.077331 # Average percentage of cache occupancy 710system.cpu.icache.tags.occ_percent::total 0.077331 # Average percentage of cache occupancy | 707system.cpu.icache.tags.occ_blocks::cpu.inst 158.400693 # Average occupied blocks per requestor 708system.cpu.icache.tags.occ_percent::cpu.inst 0.077344 # Average percentage of cache occupancy 709system.cpu.icache.tags.occ_percent::total 0.077344 # Average percentage of cache occupancy |
711system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id | 710system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id |
712system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 713system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id | 711system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id 712system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id |
714system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id | 713system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id |
715system.cpu.icache.tags.tag_accesses 4706 # Number of tag accesses 716system.cpu.icache.tags.data_accesses 4706 # Number of data accesses 717system.cpu.icache.ReadReq_hits::cpu.inst 1718 # number of ReadReq hits 718system.cpu.icache.ReadReq_hits::total 1718 # number of ReadReq hits 719system.cpu.icache.demand_hits::cpu.inst 1718 # number of demand (read+write) hits 720system.cpu.icache.demand_hits::total 1718 # number of demand (read+write) hits 721system.cpu.icache.overall_hits::cpu.inst 1718 # number of overall hits 722system.cpu.icache.overall_hits::total 1718 # number of overall hits 723system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses 724system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses 725system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses 726system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses 727system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses 728system.cpu.icache.overall_misses::total 478 # number of overall misses 729system.cpu.icache.ReadReq_miss_latency::cpu.inst 31723500 # number of ReadReq miss cycles 730system.cpu.icache.ReadReq_miss_latency::total 31723500 # number of ReadReq miss cycles 731system.cpu.icache.demand_miss_latency::cpu.inst 31723500 # number of demand (read+write) miss cycles 732system.cpu.icache.demand_miss_latency::total 31723500 # number of demand (read+write) miss cycles 733system.cpu.icache.overall_miss_latency::cpu.inst 31723500 # number of overall miss cycles 734system.cpu.icache.overall_miss_latency::total 31723500 # number of overall miss cycles 735system.cpu.icache.ReadReq_accesses::cpu.inst 2196 # number of ReadReq accesses(hits+misses) 736system.cpu.icache.ReadReq_accesses::total 2196 # number of ReadReq accesses(hits+misses) 737system.cpu.icache.demand_accesses::cpu.inst 2196 # number of demand (read+write) accesses 738system.cpu.icache.demand_accesses::total 2196 # number of demand (read+write) accesses 739system.cpu.icache.overall_accesses::cpu.inst 2196 # number of overall (read+write) accesses 740system.cpu.icache.overall_accesses::total 2196 # number of overall (read+write) accesses 741system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217668 # miss rate for ReadReq accesses 742system.cpu.icache.ReadReq_miss_rate::total 0.217668 # miss rate for ReadReq accesses 743system.cpu.icache.demand_miss_rate::cpu.inst 0.217668 # miss rate for demand accesses 744system.cpu.icache.demand_miss_rate::total 0.217668 # miss rate for demand accesses 745system.cpu.icache.overall_miss_rate::cpu.inst 0.217668 # miss rate for overall accesses 746system.cpu.icache.overall_miss_rate::total 0.217668 # miss rate for overall accesses 747system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66367.154812 # average ReadReq miss latency 748system.cpu.icache.ReadReq_avg_miss_latency::total 66367.154812 # average ReadReq miss latency 749system.cpu.icache.demand_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency 750system.cpu.icache.demand_avg_miss_latency::total 66367.154812 # average overall miss latency 751system.cpu.icache.overall_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency 752system.cpu.icache.overall_avg_miss_latency::total 66367.154812 # average overall miss latency | 714system.cpu.icache.tags.tag_accesses 4704 # Number of tag accesses 715system.cpu.icache.tags.data_accesses 4704 # Number of data accesses 716system.cpu.icache.ReadReq_hits::cpu.inst 1716 # number of ReadReq hits 717system.cpu.icache.ReadReq_hits::total 1716 # number of ReadReq hits 718system.cpu.icache.demand_hits::cpu.inst 1716 # number of demand (read+write) hits 719system.cpu.icache.demand_hits::total 1716 # number of demand (read+write) hits 720system.cpu.icache.overall_hits::cpu.inst 1716 # number of overall hits 721system.cpu.icache.overall_hits::total 1716 # number of overall hits 722system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses 723system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses 724system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses 725system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses 726system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses 727system.cpu.icache.overall_misses::total 479 # number of overall misses 728system.cpu.icache.ReadReq_miss_latency::cpu.inst 34067500 # number of ReadReq miss cycles 729system.cpu.icache.ReadReq_miss_latency::total 34067500 # number of ReadReq miss cycles 730system.cpu.icache.demand_miss_latency::cpu.inst 34067500 # number of demand (read+write) miss cycles 731system.cpu.icache.demand_miss_latency::total 34067500 # number of demand (read+write) miss cycles 732system.cpu.icache.overall_miss_latency::cpu.inst 34067500 # number of overall miss cycles 733system.cpu.icache.overall_miss_latency::total 34067500 # number of overall miss cycles 734system.cpu.icache.ReadReq_accesses::cpu.inst 2195 # number of ReadReq accesses(hits+misses) 735system.cpu.icache.ReadReq_accesses::total 2195 # number of ReadReq accesses(hits+misses) 736system.cpu.icache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses 737system.cpu.icache.demand_accesses::total 2195 # number of demand (read+write) accesses 738system.cpu.icache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses 739system.cpu.icache.overall_accesses::total 2195 # number of overall (read+write) accesses 740system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218223 # miss rate for ReadReq accesses 741system.cpu.icache.ReadReq_miss_rate::total 0.218223 # miss rate for ReadReq accesses 742system.cpu.icache.demand_miss_rate::cpu.inst 0.218223 # miss rate for demand accesses 743system.cpu.icache.demand_miss_rate::total 0.218223 # miss rate for demand accesses 744system.cpu.icache.overall_miss_rate::cpu.inst 0.218223 # miss rate for overall accesses 745system.cpu.icache.overall_miss_rate::total 0.218223 # miss rate for overall accesses 746system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71122.129436 # average ReadReq miss latency 747system.cpu.icache.ReadReq_avg_miss_latency::total 71122.129436 # average ReadReq miss latency 748system.cpu.icache.demand_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency 749system.cpu.icache.demand_avg_miss_latency::total 71122.129436 # average overall miss latency 750system.cpu.icache.overall_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency 751system.cpu.icache.overall_avg_miss_latency::total 71122.129436 # average overall miss latency |
753system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 754system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 756system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 758system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu.icache.fast_writes 0 # number of fast writes performed 760system.cpu.icache.cache_copies 0 # number of cache copies performed | 752system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 753system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 754system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 755system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 756system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 757system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 758system.cpu.icache.fast_writes 0 # number of fast writes performed 759system.cpu.icache.cache_copies 0 # number of cache copies performed |
761system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits 762system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits 763system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits 764system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits 765system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits 766system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits | 760system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits 761system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits 762system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits 763system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits 764system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits 765system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits |
767system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 768system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses 769system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 770system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses 771system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 772system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses | 766system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 767system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses 768system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 769system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses 770system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 771system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses |
773system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22315500 # number of ReadReq MSHR miss cycles 774system.cpu.icache.ReadReq_mshr_miss_latency::total 22315500 # number of ReadReq MSHR miss cycles 775system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22315500 # number of demand (read+write) MSHR miss cycles 776system.cpu.icache.demand_mshr_miss_latency::total 22315500 # number of demand (read+write) MSHR miss cycles 777system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22315500 # number of overall MSHR miss cycles 778system.cpu.icache.overall_mshr_miss_latency::total 22315500 # number of overall MSHR miss cycles 779system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for ReadReq accesses 780system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142987 # mshr miss rate for ReadReq accesses 781system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for demand accesses 782system.cpu.icache.demand_mshr_miss_rate::total 0.142987 # mshr miss rate for demand accesses 783system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for overall accesses 784system.cpu.icache.overall_mshr_miss_rate::total 0.142987 # mshr miss rate for overall accesses 785system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71068.471338 # average ReadReq mshr miss latency 786system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71068.471338 # average ReadReq mshr miss latency 787system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency 788system.cpu.icache.demand_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency 789system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency 790system.cpu.icache.overall_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency | 772system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24276250 # number of ReadReq MSHR miss cycles 773system.cpu.icache.ReadReq_mshr_miss_latency::total 24276250 # number of ReadReq MSHR miss cycles 774system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24276250 # number of demand (read+write) MSHR miss cycles 775system.cpu.icache.demand_mshr_miss_latency::total 24276250 # number of demand (read+write) MSHR miss cycles 776system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24276250 # number of overall MSHR miss cycles 777system.cpu.icache.overall_mshr_miss_latency::total 24276250 # number of overall MSHR miss cycles 778system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for ReadReq accesses 779system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143052 # mshr miss rate for ReadReq accesses 780system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for demand accesses 781system.cpu.icache.demand_mshr_miss_rate::total 0.143052 # mshr miss rate for demand accesses 782system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for overall accesses 783system.cpu.icache.overall_mshr_miss_rate::total 0.143052 # mshr miss rate for overall accesses 784system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77312.898089 # average ReadReq mshr miss latency 785system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77312.898089 # average ReadReq mshr miss latency 786system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77312.898089 # average overall mshr miss latency 787system.cpu.icache.demand_avg_mshr_miss_latency::total 77312.898089 # average overall mshr miss latency 788system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77312.898089 # average overall mshr miss latency 789system.cpu.icache.overall_avg_mshr_miss_latency::total 77312.898089 # average overall mshr miss latency |
791system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 792system.cpu.l2cache.tags.replacements 0 # number of replacements | 790system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 791system.cpu.l2cache.tags.replacements 0 # number of replacements |
793system.cpu.l2cache.tags.tagsinuse 218.773509 # Cycle average of tags in use | 792system.cpu.l2cache.tags.tagsinuse 219.195035 # Cycle average of tags in use |
794system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. | 793system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. |
795system.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks. 796system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. | 794system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. 795system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. |
797system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 796system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
798system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.460945 # Average occupied blocks per requestor 799system.cpu.l2cache.tags.occ_blocks::cpu.data 60.312564 # Average occupied blocks per requestor | 797system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.471795 # Average occupied blocks per requestor 798system.cpu.l2cache.tags.occ_blocks::cpu.data 60.723240 # Average occupied blocks per requestor |
800system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy | 799system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy |
801system.cpu.l2cache.tags.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy 802system.cpu.l2cache.tags.occ_percent::total 0.006676 # Average percentage of cache occupancy 803system.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 805system.cpu.l2cache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id 806system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id 807system.cpu.l2cache.tags.tag_accesses 4391 # Number of tag accesses 808system.cpu.l2cache.tags.data_accesses 4391 # Number of data accesses | 800system.cpu.l2cache.tags.occ_percent::cpu.data 0.001853 # Average percentage of cache occupancy 801system.cpu.l2cache.tags.occ_percent::total 0.006689 # Average percentage of cache occupancy 802system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 805system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id 806system.cpu.l2cache.tags.tag_accesses 4382 # Number of tag accesses 807system.cpu.l2cache.tags.data_accesses 4382 # Number of data accesses |
809system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 810system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 811system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 812system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 813system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 814system.cpu.l2cache.overall_hits::total 1 # number of overall hits 815system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses | 808system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 809system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 810system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 811system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 812system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 813system.cpu.l2cache.overall_hits::total 1 # number of overall hits 814system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses |
816system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses 817system.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses | 815system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 816system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses |
818system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 819system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 820system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses | 817system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 818system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 819system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses |
821system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 822system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses | 820system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 821system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses |
823system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses | 822system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses |
824system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 825system.cpu.l2cache.overall_misses::total 487 # number of overall misses 826system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21990500 # number of ReadReq miss cycles 827system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7915750 # number of ReadReq miss cycles 828system.cpu.l2cache.ReadReq_miss_latency::total 29906250 # number of ReadReq miss cycles 829system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5408750 # number of ReadExReq miss cycles 830system.cpu.l2cache.ReadExReq_miss_latency::total 5408750 # number of ReadExReq miss cycles 831system.cpu.l2cache.demand_miss_latency::cpu.inst 21990500 # number of demand (read+write) miss cycles 832system.cpu.l2cache.demand_miss_latency::cpu.data 13324500 # number of demand (read+write) miss cycles 833system.cpu.l2cache.demand_miss_latency::total 35315000 # number of demand (read+write) miss cycles 834system.cpu.l2cache.overall_miss_latency::cpu.inst 21990500 # number of overall miss cycles 835system.cpu.l2cache.overall_miss_latency::cpu.data 13324500 # number of overall miss cycles 836system.cpu.l2cache.overall_miss_latency::total 35315000 # number of overall miss cycles | 823system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 824system.cpu.l2cache.overall_misses::total 486 # number of overall misses 825system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles 826system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8448250 # number of ReadReq miss cycles 827system.cpu.l2cache.ReadReq_miss_latency::total 32399000 # number of ReadReq miss cycles 828system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5570250 # number of ReadExReq miss cycles 829system.cpu.l2cache.ReadExReq_miss_latency::total 5570250 # number of ReadExReq miss cycles 830system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles 831system.cpu.l2cache.demand_miss_latency::cpu.data 14018500 # number of demand (read+write) miss cycles 832system.cpu.l2cache.demand_miss_latency::total 37969250 # number of demand (read+write) miss cycles 833system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles 834system.cpu.l2cache.overall_miss_latency::cpu.data 14018500 # number of overall miss cycles 835system.cpu.l2cache.overall_miss_latency::total 37969250 # number of overall miss cycles |
837system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) | 836system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) |
838system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) 839system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) | 837system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 838system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) |
840system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 841system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 842system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses | 839system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 840system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 841system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses |
843system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 844system.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses | 842system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses 843system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses |
845system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses | 844system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses |
846system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 847system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses | 845system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses 846system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses |
848system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses 849system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses | 847system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses 848system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses |
850system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses | 849system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses |
851system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 852system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 853system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses 854system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 850system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 851system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 852system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses 853system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
855system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses | 854system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses |
856system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses 857system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 855system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses 856system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
858system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses 859system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70257.188498 # average ReadReq miss latency 860system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77605.392157 # average ReadReq miss latency 861system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.253012 # average ReadReq miss latency 862system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75121.527778 # average ReadExReq miss latency 863system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75121.527778 # average ReadExReq miss latency 864system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency 865system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency 866system.cpu.l2cache.demand_avg_miss_latency::total 72515.400411 # average overall miss latency 867system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency 868system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency 869system.cpu.l2cache.overall_avg_miss_latency::total 72515.400411 # average overall miss latency | 857system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses 858system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76519.968051 # average ReadReq miss latency 859system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83646.039604 # average ReadReq miss latency 860system.cpu.l2cache.ReadReq_avg_miss_latency::total 78258.454106 # average ReadReq miss latency 861system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77364.583333 # average ReadExReq miss latency 862system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77364.583333 # average ReadExReq miss latency 863system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76519.968051 # average overall miss latency 864system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81031.791908 # average overall miss latency 865system.cpu.l2cache.demand_avg_miss_latency::total 78126.028807 # average overall miss latency 866system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76519.968051 # average overall miss latency 867system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81031.791908 # average overall miss latency 868system.cpu.l2cache.overall_avg_miss_latency::total 78126.028807 # average overall miss latency |
870system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 871system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 872system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 873system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 874system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 875system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 876system.cpu.l2cache.fast_writes 0 # number of fast writes performed 877system.cpu.l2cache.cache_copies 0 # number of cache copies performed 878system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses | 869system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 870system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 871system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 872system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 873system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 874system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 875system.cpu.l2cache.fast_writes 0 # number of fast writes performed 876system.cpu.l2cache.cache_copies 0 # number of cache copies performed 877system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses |
879system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 880system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses | 878system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 879system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses |
881system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 882system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 883system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses | 880system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 881system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 882system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses |
884system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 885system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses | 883system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 884system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses |
886system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses | 885system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses |
887system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 888system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses 889system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18043000 # number of ReadReq MSHR miss cycles 890system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6661250 # number of ReadReq MSHR miss cycles 891system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24704250 # number of ReadReq MSHR miss cycles 892system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4522750 # number of ReadExReq MSHR miss cycles 893system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4522750 # number of ReadExReq MSHR miss cycles 894system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18043000 # number of demand (read+write) MSHR miss cycles 895system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11184000 # number of demand (read+write) MSHR miss cycles 896system.cpu.l2cache.demand_mshr_miss_latency::total 29227000 # number of demand (read+write) MSHR miss cycles 897system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18043000 # number of overall MSHR miss cycles 898system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11184000 # number of overall MSHR miss cycles 899system.cpu.l2cache.overall_mshr_miss_latency::total 29227000 # number of overall MSHR miss cycles | 886system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 887system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses 888system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20032750 # number of ReadReq MSHR miss cycles 889system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7188250 # number of ReadReq MSHR miss cycles 890system.cpu.l2cache.ReadReq_mshr_miss_latency::total 27221000 # number of ReadReq MSHR miss cycles 891system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4674250 # number of ReadExReq MSHR miss cycles 892system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4674250 # number of ReadExReq MSHR miss cycles 893system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20032750 # number of demand (read+write) MSHR miss cycles 894system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11862500 # number of demand (read+write) MSHR miss cycles 895system.cpu.l2cache.demand_mshr_miss_latency::total 31895250 # number of demand (read+write) MSHR miss cycles 896system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20032750 # number of overall MSHR miss cycles 897system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11862500 # number of overall MSHR miss cycles 898system.cpu.l2cache.overall_mshr_miss_latency::total 31895250 # number of overall MSHR miss cycles |
900system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses 901system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses | 899system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses 900system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses |
902system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses | 901system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses |
903system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 904system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 905system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses 906system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 902system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 903system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 904system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses 905system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
907system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses | 906system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses |
908system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses 909system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 907system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses 908system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
910system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses 911system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57645.367412 # average ReadReq mshr miss latency 912system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65306.372549 # average ReadReq mshr miss latency 913system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59528.313253 # average ReadReq mshr miss latency 914system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62815.972222 # average ReadExReq mshr miss latency 915system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62815.972222 # average ReadExReq mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency | 909system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses 910system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64002.396166 # average ReadReq mshr miss latency 911system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71170.792079 # average ReadReq mshr miss latency 912system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65751.207729 # average ReadReq mshr miss latency 913system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64920.138889 # average ReadExReq mshr miss latency 914system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64920.138889 # average ReadExReq mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency |
922system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 921system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
923system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 924system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution | 922system.cpu.toL2Bus.trans_dist::ReadReq 415 # Transaction distribution 923system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution |
925system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 926system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 927system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) | 924system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 925system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 926system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) |
928system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 929system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) | 927system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) 928system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) |
930system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) | 929system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) |
931system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 932system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) | 930system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) 931system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) |
933system.cpu.toL2Bus.snoops 0 # Total snoops (count) | 932system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
934system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram | 933system.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram |
935system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 936system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 937system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 938system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 934system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 935system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 936system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 937system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
939system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram | 938system.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram |
940system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 941system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 942system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 943system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 939system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 940system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 941system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 942system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
944system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram 945system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) 946system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 947system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) 948system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 949system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) | 943system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram 944system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) 945system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 946system.cpu.toL2Bus.respLayer0.occupancy 535750 # Layer occupancy (ticks) 947system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 948system.cpu.toL2Bus.respLayer1.occupancy 285500 # Layer occupancy (ticks) |
950system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) | 949system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) |
951system.membus.trans_dist::ReadReq 415 # Transaction distribution 952system.membus.trans_dist::ReadResp 415 # Transaction distribution | 950system.membus.trans_dist::ReadReq 414 # Transaction distribution 951system.membus.trans_dist::ReadResp 414 # Transaction distribution |
953system.membus.trans_dist::ReadExReq 72 # Transaction distribution 954system.membus.trans_dist::ReadExResp 72 # Transaction distribution | 952system.membus.trans_dist::ReadExReq 72 # Transaction distribution 953system.membus.trans_dist::ReadExResp 72 # Transaction distribution |
955system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) 956system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) 957system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 958system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) | 954system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) 955system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) 956system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) 957system.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) |
959system.membus.snoops 0 # Total snoops (count) | 958system.membus.snoops 0 # Total snoops (count) |
960system.membus.snoop_fanout::samples 487 # Request fanout histogram | 959system.membus.snoop_fanout::samples 486 # Request fanout histogram |
961system.membus.snoop_fanout::mean 0 # Request fanout histogram 962system.membus.snoop_fanout::stdev 0 # Request fanout histogram 963system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 960system.membus.snoop_fanout::mean 0 # Request fanout histogram 961system.membus.snoop_fanout::stdev 0 # Request fanout histogram 962system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
964system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram | 963system.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram |
965system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 966system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 967system.membus.snoop_fanout::min_value 0 # Request fanout histogram 968system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 964system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 965system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 966system.membus.snoop_fanout::min_value 0 # Request fanout histogram 967system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
969system.membus.snoop_fanout::total 487 # Request fanout histogram 970system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) 971system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 972system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) 973system.membus.respLayer1.utilization 22.2 # Layer utilization (%) | 968system.membus.snoop_fanout::total 486 # Request fanout histogram 969system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) 970system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) 971system.membus.respLayer1.occupancy 2581250 # Layer occupancy (ticks) 972system.membus.respLayer1.utilization 11.7 # Layer utilization (%) |
974 975---------- End Simulation Statistics ---------- | 973 974---------- End Simulation Statistics ---------- |