| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated |
| 4sim_ticks 21078000 # Number of ticks simulated 5final_tick 21078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 21025000 # Number of ticks simulated 5final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 72140 # Simulator instruction rate (inst/s) 8host_op_rate 72127 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 238549554 # Simulator tick rate (ticks/s) 10host_mem_usage 265696 # Number of bytes of host memory used | 7host_inst_rate 72274 # Simulator instruction rate (inst/s) 8host_op_rate 72262 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 238397605 # Simulator tick rate (ticks/s) 10host_mem_usage 265716 # Number of bytes of host memory used |
| 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31168 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 487 # Number of read requests responded to by this memory | 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31168 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 487 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 950374798 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 528323370 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1478698169 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 950374798 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 950374798 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 950374798 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 528323370 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1478698169 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 488 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 488 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 21045000 # Total gap between requests | 78system.physmem.totGap 20992000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 488 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 488 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see |
| 94system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see | 95system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see |
| 97system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 97system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 76 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 328.393443 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 194.167058 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 347.898610 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 21 34.43% 34.43% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 16 26.23% 60.66% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 6 9.84% 70.49% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 6.56% 77.05% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.92% 81.97% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::896-1023 1 1.64% 83.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1024-1151 10 16.39% 100.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation 201system.physmem.totQLat 3243750 # Total ticks spent queuing 202system.physmem.totMemAccLat 13328750 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 224.218426 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 329.360278 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 19 24.05% 50.63% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation 203system.physmem.totQLat 4394750 # Total ticks spent queuing 204system.physmem.totMemAccLat 13544750 # Total ticks spent from burst creation until serviced by the DRAM |
| 203system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers |
| 204system.physmem.totBankLat 7645000 # Total ticks spent accessing banks 205system.physmem.avgQLat 6647.03 # Average queueing delay per DRAM burst 206system.physmem.avgBankLat 15665.98 # Average bank access latency per DRAM burst | 206system.physmem.avgQLat 9005.64 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 27313.01 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1481.73 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 27755.64 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1481.73 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.physmem.busUtil 11.58 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 11.61 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads |
| 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 394 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 394 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 43125.00 # Average gap between requests | 223system.physmem.avgGap 43016.39 # Average gap between requests |
| 224system.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined | 224system.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined |
| 225system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state 226system.membus.throughput 1478698169 # Throughput (bytes/s) | 225system.physmem.memoryStateTime::IDLE 22000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15304250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 1482425684 # Throughput (bytes/s) |
| 227system.membus.trans_dist::ReadReq 415 # Transaction distribution 228system.membus.trans_dist::ReadResp 414 # Transaction distribution 229system.membus.trans_dist::ReadExReq 73 # Transaction distribution 230system.membus.trans_dist::ReadExResp 73 # Transaction distribution 231system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) 232system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) 233system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 234system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 235system.membus.data_through_bus 31168 # Total data (bytes) 236system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 231system.membus.trans_dist::ReadReq 415 # Transaction distribution 232system.membus.trans_dist::ReadResp 414 # Transaction distribution 233system.membus.trans_dist::ReadExReq 73 # Transaction distribution 234system.membus.trans_dist::ReadExResp 73 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 31168 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 237system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) | 241system.membus.reqLayer0.occupancy 618500 # Layer occupancy (ticks) |
| 238system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) | 242system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) |
| 239system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) 240system.membus.respLayer1.utilization 21.6 # Layer utilization (%) | 243system.membus.respLayer1.occupancy 4556750 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 21.7 # Layer utilization (%) |
| 241system.cpu_clk_domain.clock 500 # Clock period in ticks 242system.cpu.branchPred.lookups 2894 # Number of BP lookups 243system.cpu.branchPred.condPredicted 1702 # Number of conditional branches predicted 244system.cpu.branchPred.condIncorrect 512 # Number of conditional branches incorrect 245system.cpu.branchPred.BTBLookups 2209 # Number of BTB lookups 246system.cpu.branchPred.BTBHits 756 # Number of BTB hits 247system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 248system.cpu.branchPred.BTBHitPct 34.223631 # BTB Hit Percentage 249system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. 250system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 251system.cpu.dtb.fetch_hits 0 # ITB hits 252system.cpu.dtb.fetch_misses 0 # ITB misses 253system.cpu.dtb.fetch_acv 0 # ITB acv 254system.cpu.dtb.fetch_accesses 0 # ITB accesses | 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 2894 # Number of BP lookups 247system.cpu.branchPred.condPredicted 1702 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 512 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 2209 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 756 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 252system.cpu.branchPred.BTBHitPct 34.223631 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 255system.cpu.dtb.fetch_hits 0 # ITB hits 256system.cpu.dtb.fetch_misses 0 # ITB misses 257system.cpu.dtb.fetch_acv 0 # ITB acv 258system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 255system.cpu.dtb.read_hits 2078 # DTB read hits | 259system.cpu.dtb.read_hits 2077 # DTB read hits |
| 256system.cpu.dtb.read_misses 47 # DTB read misses 257system.cpu.dtb.read_acv 0 # DTB read access violations | 260system.cpu.dtb.read_misses 47 # DTB read misses 261system.cpu.dtb.read_acv 0 # DTB read access violations |
| 258system.cpu.dtb.read_accesses 2125 # DTB read accesses | 262system.cpu.dtb.read_accesses 2124 # DTB read accesses |
| 259system.cpu.dtb.write_hits 1062 # DTB write hits 260system.cpu.dtb.write_misses 31 # DTB write misses 261system.cpu.dtb.write_acv 0 # DTB write access violations 262system.cpu.dtb.write_accesses 1093 # DTB write accesses | 263system.cpu.dtb.write_hits 1062 # DTB write hits 264system.cpu.dtb.write_misses 31 # DTB write misses 265system.cpu.dtb.write_acv 0 # DTB write access violations 266system.cpu.dtb.write_accesses 1093 # DTB write accesses |
| 263system.cpu.dtb.data_hits 3140 # DTB hits | 267system.cpu.dtb.data_hits 3139 # DTB hits |
| 264system.cpu.dtb.data_misses 78 # DTB misses 265system.cpu.dtb.data_acv 0 # DTB access violations | 268system.cpu.dtb.data_misses 78 # DTB misses 269system.cpu.dtb.data_acv 0 # DTB access violations |
| 266system.cpu.dtb.data_accesses 3218 # DTB accesses 267system.cpu.itb.fetch_hits 2388 # ITB hits | 270system.cpu.dtb.data_accesses 3217 # DTB accesses 271system.cpu.itb.fetch_hits 2387 # ITB hits |
| 268system.cpu.itb.fetch_misses 39 # ITB misses 269system.cpu.itb.fetch_acv 0 # ITB acv | 272system.cpu.itb.fetch_misses 39 # ITB misses 273system.cpu.itb.fetch_acv 0 # ITB acv |
| 270system.cpu.itb.fetch_accesses 2427 # ITB accesses | 274system.cpu.itb.fetch_accesses 2426 # ITB accesses |
| 271system.cpu.itb.read_hits 0 # DTB read hits 272system.cpu.itb.read_misses 0 # DTB read misses 273system.cpu.itb.read_acv 0 # DTB read access violations 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_acv 0 # DTB write access violations 278system.cpu.itb.write_accesses 0 # DTB write accesses 279system.cpu.itb.data_hits 0 # DTB hits 280system.cpu.itb.data_misses 0 # DTB misses 281system.cpu.itb.data_acv 0 # DTB access violations 282system.cpu.itb.data_accesses 0 # DTB accesses 283system.cpu.workload.num_syscalls 17 # Number of system calls | 275system.cpu.itb.read_hits 0 # DTB read hits 276system.cpu.itb.read_misses 0 # DTB read misses 277system.cpu.itb.read_acv 0 # DTB read access violations 278system.cpu.itb.read_accesses 0 # DTB read accesses 279system.cpu.itb.write_hits 0 # DTB write hits 280system.cpu.itb.write_misses 0 # DTB write misses 281system.cpu.itb.write_acv 0 # DTB write access violations 282system.cpu.itb.write_accesses 0 # DTB write accesses 283system.cpu.itb.data_hits 0 # DTB hits 284system.cpu.itb.data_misses 0 # DTB misses 285system.cpu.itb.data_acv 0 # DTB access violations 286system.cpu.itb.data_accesses 0 # DTB accesses 287system.cpu.workload.num_syscalls 17 # Number of system calls |
| 284system.cpu.numCycles 42157 # number of cpu cycles simulated | 288system.cpu.numCycles 42051 # number of cpu cycles simulated |
| 285system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 286system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 289system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 287system.cpu.fetch.icacheStallCycles 8510 # Number of cycles fetch is stalled on an Icache miss 288system.cpu.fetch.Insts 16605 # Number of instructions fetch has processed | 291system.cpu.fetch.icacheStallCycles 8515 # Number of cycles fetch is stalled on an Icache miss 292system.cpu.fetch.Insts 16590 # Number of instructions fetch has processed |
| 289system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered 290system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken | 293system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered 294system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken |
| 291system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked | 295system.cpu.fetch.Cycles 2968 # Number of cycles fetch has run and was not squashing or blocked |
| 292system.cpu.fetch.SquashCycles 1911 # Number of cycles fetch has spent squashing | 296system.cpu.fetch.SquashCycles 1911 # Number of cycles fetch has spent squashing |
| 293system.cpu.fetch.BlockedCycles 1405 # Number of cycles fetch has spent blocked | 297system.cpu.fetch.BlockedCycles 1438 # Number of cycles fetch has spent blocked |
| 294system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 295system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps | 298system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 299system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps |
| 296system.cpu.fetch.CacheLines 2388 # Number of cache lines fetched 297system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed 298system.cpu.fetch.rateDist::samples 14964 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::mean 1.109663 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::stdev 2.506678 # Number of instructions fetched each cycle (Total) | 300system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched 301system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed 302system.cpu.fetch.rateDist::samples 15000 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::mean 1.106000 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::stdev 2.503194 # Number of instructions fetched each cycle (Total) |
| 301system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 305system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 302system.cpu.fetch.rateDist::0 11994 80.15% 80.15% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::1 318 2.13% 82.28% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::2 234 1.56% 83.84% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::3 214 1.43% 85.27% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::4 255 1.70% 86.98% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::5 241 1.61% 88.59% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::6 264 1.76% 90.35% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::7 184 1.23% 91.58% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::8 1260 8.42% 100.00% # Number of instructions fetched each cycle (Total) | 306system.cpu.fetch.rateDist::0 12032 80.21% 80.21% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::1 318 2.12% 82.33% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::2 234 1.56% 83.89% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::3 214 1.43% 85.32% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::4 255 1.70% 87.02% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::5 241 1.61% 88.63% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::6 264 1.76% 90.39% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::7 183 1.22% 91.61% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::8 1259 8.39% 100.00% # Number of instructions fetched each cycle (Total) |
| 311system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 315system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 314system.cpu.fetch.rateDist::total 14964 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.branchRate 0.068648 # Number of branch fetches per cycle 316system.cpu.fetch.rate 0.393885 # Number of inst fetches per cycle 317system.cpu.decode.IdleCycles 9327 # Number of cycles decode is idle 318system.cpu.decode.BlockedCycles 1567 # Number of cycles decode is blocked 319system.cpu.decode.RunCycles 2770 # Number of cycles decode is running | 318system.cpu.fetch.rateDist::total 15000 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.branchRate 0.068821 # Number of branch fetches per cycle 320system.cpu.fetch.rate 0.394521 # Number of inst fetches per cycle 321system.cpu.decode.IdleCycles 9332 # Number of cycles decode is idle 322system.cpu.decode.BlockedCycles 1599 # Number of cycles decode is blocked 323system.cpu.decode.RunCycles 2769 # Number of cycles decode is running |
| 320system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking 321system.cpu.decode.SquashCycles 1226 # Number of cycles decode is squashing 322system.cpu.decode.BranchResolved 243 # Number of times decode resolved a branch 323system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction | 324system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking 325system.cpu.decode.SquashCycles 1226 # Number of cycles decode is squashing 326system.cpu.decode.BranchResolved 243 # Number of times decode resolved a branch 327system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction |
| 324system.cpu.decode.DecodedInsts 15343 # Number of instructions handled by decode | 328system.cpu.decode.DecodedInsts 15335 # Number of instructions handled by decode |
| 325system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode 326system.cpu.rename.SquashCycles 1226 # Number of cycles rename is squashing | 329system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode 330system.cpu.rename.SquashCycles 1226 # Number of cycles rename is squashing |
| 327system.cpu.rename.IdleCycles 9537 # Number of cycles rename is idle 328system.cpu.rename.BlockCycles 678 # Number of cycles rename is blocking 329system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst 330system.cpu.rename.RunCycles 2628 # Number of cycles rename is running 331system.cpu.rename.UnblockCycles 341 # Number of cycles rename is unblocking 332system.cpu.rename.RenamedInsts 14637 # Number of instructions processed by rename | 331system.cpu.rename.IdleCycles 9542 # Number of cycles rename is idle 332system.cpu.rename.BlockCycles 708 # Number of cycles rename is blocking 333system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst 334system.cpu.rename.RunCycles 2627 # Number of cycles rename is running 335system.cpu.rename.UnblockCycles 344 # Number of cycles rename is unblocking 336system.cpu.rename.RenamedInsts 14630 # Number of instructions processed by rename |
| 333system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full 334system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full | 337system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full 338system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full |
| 335system.cpu.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full 336system.cpu.rename.RenamedOperands 10979 # Number of destination operands rename has renamed 337system.cpu.rename.RenameLookups 18262 # Number of register rename lookups that rename has made 338system.cpu.rename.int_rename_lookups 18253 # Number of integer rename lookups | 339system.cpu.rename.LSQFullEvents 301 # Number of times rename has blocked due to LSQ full 340system.cpu.rename.RenamedOperands 10973 # Number of destination operands rename has renamed 341system.cpu.rename.RenameLookups 18255 # Number of register rename lookups that rename has made 342system.cpu.rename.int_rename_lookups 18246 # Number of integer rename lookups |
| 339system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 340system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed | 343system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 344system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed |
| 341system.cpu.rename.UndoneMaps 6409 # Number of HB maps that are undone due to squashing | 345system.cpu.rename.UndoneMaps 6403 # Number of HB maps that are undone due to squashing |
| 342system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 343system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed | 346system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 347system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed |
| 344system.cpu.rename.skidInsts 843 # count of insts added to the skid buffer 345system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. | 348system.cpu.rename.skidInsts 874 # count of insts added to the skid buffer 349system.cpu.memDep0.insertedLoads 2768 # Number of loads inserted to the mem dependence unit. |
| 346system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. 347system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 348system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 350system.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. 351system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 352system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 349system.cpu.iq.iqInstsAdded 12974 # Number of instructions added to the IQ (excludes non-spec) | 353system.cpu.iq.iqInstsAdded 12973 # Number of instructions added to the IQ (excludes non-spec) |
| 350system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ | 354system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ |
| 351system.cpu.iq.iqInstsIssued 10780 # Number of instructions issued | 355system.cpu.iq.iqInstsIssued 10779 # Number of instructions issued |
| 352system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued | 356system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued |
| 353system.cpu.iq.iqSquashedInstsExamined 6201 # Number of squashed instructions iterated over during squash; mainly for profiling 354system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph | 357system.cpu.iq.iqSquashedInstsExamined 6200 # Number of squashed instructions iterated over during squash; mainly for profiling 358system.cpu.iq.iqSquashedOperandsExamined 3613 # Number of squashed operands that are examined and possibly removed from graph |
| 355system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed | 359system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed |
| 356system.cpu.iq.issued_per_cycle::samples 14964 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::mean 0.720396 # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::stdev 1.363744 # Number of insts issued each cycle | 360system.cpu.iq.issued_per_cycle::samples 15000 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::mean 0.718600 # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::stdev 1.361398 # Number of insts issued each cycle |
| 359system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 363system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 360system.cpu.iq.issued_per_cycle::0 10463 69.92% 69.92% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::1 1623 10.85% 80.77% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::2 1158 7.74% 88.51% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::3 756 5.05% 93.56% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::4 501 3.35% 96.91% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::5 270 1.80% 98.71% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::6 146 0.98% 99.69% # Number of insts issued each cycle | 364system.cpu.iq.issued_per_cycle::0 10485 69.90% 69.90% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::1 1646 10.97% 80.87% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::2 1153 7.69% 88.56% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::3 753 5.02% 93.58% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::4 501 3.34% 96.92% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::5 269 1.79% 98.71% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle |
| 367system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 371system.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 372system.cpu.iq.issued_per_cycle::total 14964 # Number of insts issued each cycle | 376system.cpu.iq.issued_per_cycle::total 15000 # Number of insts issued each cycle |
| 373system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available 375system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available 376system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 400system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available 403system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available 404system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available 405system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 406system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 407system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued | 377system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 378system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available 379system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available 380system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 404system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available 407system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available 408system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available 409system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 410system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 411system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| 408system.cpu.iq.FU_type_0::IntAlu 7243 67.19% 67.21% # Type of FU issued | 412system.cpu.iq.FU_type_0::IntAlu 7243 67.20% 67.21% # Type of FU issued |
| 409system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued 410system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued 416system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 429system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued | 413system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued 414system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued 416system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 433system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued |
| 437system.cpu.iq.FU_type_0::MemRead 2399 22.25% 89.49% # Type of FU issued | 441system.cpu.iq.FU_type_0::MemRead 2398 22.25% 89.49% # Type of FU issued |
| 438system.cpu.iq.FU_type_0::MemWrite 1133 10.51% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 442system.cpu.iq.FU_type_0::MemWrite 1133 10.51% 100.00% # Type of FU issued 443system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 444system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 441system.cpu.iq.FU_type_0::total 10780 # Type of FU issued 442system.cpu.iq.rate 0.255711 # Inst issue rate | 445system.cpu.iq.FU_type_0::total 10779 # Type of FU issued 446system.cpu.iq.rate 0.256332 # Inst issue rate |
| 443system.cpu.iq.fu_busy_cnt 112 # FU busy when requested | 447system.cpu.iq.fu_busy_cnt 112 # FU busy when requested |
| 444system.cpu.iq.fu_busy_rate 0.010390 # FU busy rate (busy events/executed inst) 445system.cpu.iq.int_inst_queue_reads 36671 # Number of integer instruction queue reads 446system.cpu.iq.int_inst_queue_writes 19208 # Number of integer instruction queue writes | 448system.cpu.iq.fu_busy_rate 0.010391 # FU busy rate (busy events/executed inst) 449system.cpu.iq.int_inst_queue_reads 36705 # Number of integer instruction queue reads 450system.cpu.iq.int_inst_queue_writes 19206 # Number of integer instruction queue writes |
| 447system.cpu.iq.int_inst_queue_wakeup_accesses 9602 # Number of integer instruction queue wakeup accesses 448system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 449system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 450system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses | 451system.cpu.iq.int_inst_queue_wakeup_accesses 9602 # Number of integer instruction queue wakeup accesses 452system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 453system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 454system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses |
| 451system.cpu.iq.int_alu_accesses 10879 # Number of integer alu accesses | 455system.cpu.iq.int_alu_accesses 10878 # Number of integer alu accesses |
| 452system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 453system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 454system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 456system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 457system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 458system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 455system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed | 459system.cpu.iew.lsq.thread0.squashedLoads 1585 # Number of loads squashed |
| 456system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 457system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations 458system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed 459system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 460system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 461system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 460system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 461system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations 462system.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed 463system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 464system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 465system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
| 462system.cpu.iew.lsq.thread0.cacheBlocked 127 # Number of times an access to memory failed due to the cache being blocked | 466system.cpu.iew.lsq.thread0.cacheBlocked 132 # Number of times an access to memory failed due to the cache being blocked |
| 463system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 464system.cpu.iew.iewSquashCycles 1226 # Number of cycles IEW is squashing 465system.cpu.iew.iewBlockCycles 247 # Number of cycles IEW is blocking 466system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking | 467system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 468system.cpu.iew.iewSquashCycles 1226 # Number of cycles IEW is squashing 469system.cpu.iew.iewBlockCycles 247 # Number of cycles IEW is blocking 470system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking |
| 467system.cpu.iew.iewDispatchedInsts 13092 # Number of instructions dispatched to IQ | 471system.cpu.iew.iewDispatchedInsts 13091 # Number of instructions dispatched to IQ |
| 468system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch | 472system.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch |
| 469system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions | 473system.cpu.iew.iewDispLoadInsts 2768 # Number of dispatched load instructions |
| 470system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions 471system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions 472system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 473system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 474system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations 475system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly 476system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly 477system.cpu.iew.branchMispredicts 504 # Number of branch mispredicts detected at execute | 474system.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions 475system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions 476system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 477system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 478system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations 479system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly 480system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly 481system.cpu.iew.branchMispredicts 504 # Number of branch mispredicts detected at execute |
| 478system.cpu.iew.iewExecutedInsts 10072 # Number of executed instructions 479system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed | 482system.cpu.iew.iewExecutedInsts 10071 # Number of executed instructions 483system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed |
| 480system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute 481system.cpu.iew.exec_swp 0 # number of swp insts executed 482system.cpu.iew.exec_nop 89 # number of nop insts executed | 484system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute 485system.cpu.iew.exec_swp 0 # number of swp insts executed 486system.cpu.iew.exec_nop 89 # number of nop insts executed |
| 483system.cpu.iew.exec_refs 3231 # number of memory reference insts executed | 487system.cpu.iew.exec_refs 3230 # number of memory reference insts executed |
| 484system.cpu.iew.exec_branches 1589 # Number of branches executed 485system.cpu.iew.exec_stores 1095 # Number of stores executed | 488system.cpu.iew.exec_branches 1589 # Number of branches executed 489system.cpu.iew.exec_stores 1095 # Number of stores executed |
| 486system.cpu.iew.exec_rate 0.238916 # Inst execution rate | 490system.cpu.iew.exec_rate 0.239495 # Inst execution rate |
| 487system.cpu.iew.wb_sent 9755 # cumulative count of insts sent to commit 488system.cpu.iew.wb_count 9612 # cumulative count of insts written-back | 491system.cpu.iew.wb_sent 9755 # cumulative count of insts sent to commit 492system.cpu.iew.wb_count 9612 # cumulative count of insts written-back |
| 489system.cpu.iew.wb_producers 5080 # num instructions producing a value 490system.cpu.iew.wb_consumers 6838 # num instructions consuming a value | 493system.cpu.iew.wb_producers 5069 # num instructions producing a value 494system.cpu.iew.wb_consumers 6811 # num instructions consuming a value |
| 491system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 495system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 492system.cpu.iew.wb_rate 0.228005 # insts written-back per cycle 493system.cpu.iew.wb_fanout 0.742907 # average fanout of values written-back | 496system.cpu.iew.wb_rate 0.228580 # insts written-back per cycle 497system.cpu.iew.wb_fanout 0.744237 # average fanout of values written-back |
| 494system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 498system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 495system.cpu.commit.commitSquashedInsts 6701 # The number of squashed insts skipped by commit | 499system.cpu.commit.commitSquashedInsts 6700 # The number of squashed insts skipped by commit |
| 496system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 497system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted | 500system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 501system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted |
| 498system.cpu.commit.committed_per_cycle::samples 13738 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::mean 0.465060 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::stdev 1.277866 # Number of insts commited each cycle | 502system.cpu.commit.committed_per_cycle::samples 13774 # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::mean 0.463845 # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::stdev 1.273398 # Number of insts commited each cycle |
| 501system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 505system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 502system.cpu.commit.committed_per_cycle::0 10960 79.78% 79.78% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::1 1479 10.77% 90.54% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::2 519 3.78% 94.32% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::3 236 1.72% 96.04% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::4 157 1.14% 97.18% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::5 106 0.77% 97.95% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::6 104 0.76% 98.71% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::7 34 0.25% 98.96% # Number of insts commited each cycle | 506system.cpu.commit.committed_per_cycle::0 10981 79.72% 79.72% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::1 1489 10.81% 90.53% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::2 532 3.86% 94.40% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::3 235 1.71% 96.10% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::4 155 1.13% 97.23% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::5 100 0.73% 97.95% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::6 106 0.77% 98.72% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::7 33 0.24% 98.96% # Number of insts commited each cycle |
| 510system.cpu.commit.committed_per_cycle::8 143 1.04% 100.00% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 514system.cpu.commit.committed_per_cycle::8 143 1.04% 100.00% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 514system.cpu.commit.committed_per_cycle::total 13738 # Number of insts commited each cycle | 518system.cpu.commit.committed_per_cycle::total 13774 # Number of insts commited each cycle |
| 515system.cpu.commit.committedInsts 6389 # Number of instructions committed 516system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 517system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 518system.cpu.commit.refs 2048 # Number of memory references committed 519system.cpu.commit.loads 1183 # Number of loads committed 520system.cpu.commit.membars 0 # Number of memory barriers committed 521system.cpu.commit.branches 1050 # Number of branches committed 522system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 523system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 524system.cpu.commit.function_calls 127 # Number of function calls committed. | 519system.cpu.commit.committedInsts 6389 # Number of instructions committed 520system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 521system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 522system.cpu.commit.refs 2048 # Number of memory references committed 523system.cpu.commit.loads 1183 # Number of loads committed 524system.cpu.commit.membars 0 # Number of memory barriers committed 525system.cpu.commit.branches 1050 # Number of branches committed 526system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 527system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 528system.cpu.commit.function_calls 127 # Number of function calls committed. |
| 529system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 530system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 531system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 532system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 533system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 534system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 535system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 536system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 537system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 538system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 559system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 560system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 561system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 562system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 563system.cpu.commit.op_class_0::total 6389 # Class of committed instruction |
|
| 525system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached 526system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 564system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached 565system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 527system.cpu.rob.rob_reads 26334 # The number of ROB reads 528system.cpu.rob.rob_writes 27415 # The number of ROB writes | 566system.cpu.rob.rob_reads 26369 # The number of ROB reads 567system.cpu.rob.rob_writes 27413 # The number of ROB writes |
| 529system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself | 568system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 530system.cpu.idleCycles 27193 # Total number of cycles that the CPU has spent unscheduled due to idling | 569system.cpu.idleCycles 27051 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 531system.cpu.committedInsts 6372 # Number of Instructions Simulated 532system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 533system.cpu.committedInsts_total 6372 # Number of Instructions Simulated | 570system.cpu.committedInsts 6372 # Number of Instructions Simulated 571system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 572system.cpu.committedInsts_total 6372 # Number of Instructions Simulated |
| 534system.cpu.cpi 6.615976 # CPI: Cycles Per Instruction 535system.cpu.cpi_total 6.615976 # CPI: Total CPI of All Threads 536system.cpu.ipc 0.151149 # IPC: Instructions Per Cycle 537system.cpu.ipc_total 0.151149 # IPC: Total IPC of All Threads 538system.cpu.int_regfile_reads 12785 # number of integer regfile reads | 573system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction 574system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads 575system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle 576system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads 577system.cpu.int_regfile_reads 12784 # number of integer regfile reads |
| 539system.cpu.int_regfile_writes 7268 # number of integer regfile writes 540system.cpu.fp_regfile_reads 8 # number of floating regfile reads 541system.cpu.fp_regfile_writes 2 # number of floating regfile writes 542system.cpu.misc_regfile_reads 1 # number of misc regfile reads 543system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 578system.cpu.int_regfile_writes 7268 # number of integer regfile writes 579system.cpu.fp_regfile_reads 8 # number of floating regfile reads 580system.cpu.fp_regfile_writes 2 # number of floating regfile writes 581system.cpu.misc_regfile_reads 1 # number of misc regfile reads 582system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 544system.cpu.toL2Bus.throughput 1481734510 # Throughput (bytes/s) | 583system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s) |
| 545system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 546system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution 547system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 548system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 549system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) 550system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 551system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) 552system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 553system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 554system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) 555system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) 556system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 557system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 558system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) | 584system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 585system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution 586system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 587system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 588system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) 589system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 590system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) 591system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 592system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 593system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) 594system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) 595system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 596system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 597system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) |
| 559system.cpu.toL2Bus.respLayer0.occupancy 528000 # Layer occupancy (ticks) | 598system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) |
| 560system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) | 599system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) |
| 561system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) | 600system.cpu.toL2Bus.respLayer1.occupancy 278250 # Layer occupancy (ticks) |
| 562system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 563system.cpu.icache.tags.replacements 0 # number of replacements | 601system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 602system.cpu.icache.tags.replacements 0 # number of replacements |
| 564system.cpu.icache.tags.tagsinuse 159.411930 # Cycle average of tags in use 565system.cpu.icache.tags.total_refs 1899 # Total number of references to valid blocks. | 603system.cpu.icache.tags.tagsinuse 159.423717 # Cycle average of tags in use 604system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. |
| 566system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. | 605system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. |
| 567system.cpu.icache.tags.avg_refs 6.047771 # Average number of references to valid blocks. | 606system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. |
| 568system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 607system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 569system.cpu.icache.tags.occ_blocks::cpu.inst 159.411930 # Average occupied blocks per requestor 570system.cpu.icache.tags.occ_percent::cpu.inst 0.077838 # Average percentage of cache occupancy 571system.cpu.icache.tags.occ_percent::total 0.077838 # Average percentage of cache occupancy | 608system.cpu.icache.tags.occ_blocks::cpu.inst 159.423717 # Average occupied blocks per requestor 609system.cpu.icache.tags.occ_percent::cpu.inst 0.077844 # Average percentage of cache occupancy 610system.cpu.icache.tags.occ_percent::total 0.077844 # Average percentage of cache occupancy |
| 572system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id 573system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id 574system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 575system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id | 611system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 614system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id |
| 576system.cpu.icache.tags.tag_accesses 5090 # Number of tag accesses 577system.cpu.icache.tags.data_accesses 5090 # Number of data accesses 578system.cpu.icache.ReadReq_hits::cpu.inst 1899 # number of ReadReq hits 579system.cpu.icache.ReadReq_hits::total 1899 # number of ReadReq hits 580system.cpu.icache.demand_hits::cpu.inst 1899 # number of demand (read+write) hits 581system.cpu.icache.demand_hits::total 1899 # number of demand (read+write) hits 582system.cpu.icache.overall_hits::cpu.inst 1899 # number of overall hits 583system.cpu.icache.overall_hits::total 1899 # number of overall hits | 615system.cpu.icache.tags.tag_accesses 5088 # Number of tag accesses 616system.cpu.icache.tags.data_accesses 5088 # Number of data accesses 617system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits 618system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits 619system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits 620system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits 621system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits 622system.cpu.icache.overall_hits::total 1898 # number of overall hits |
| 584system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses 585system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses 586system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses 587system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses 588system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses 589system.cpu.icache.overall_misses::total 489 # number of overall misses | 623system.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses 624system.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses 625system.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses 626system.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses 627system.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses 628system.cpu.icache.overall_misses::total 489 # number of overall misses |
| 590system.cpu.icache.ReadReq_miss_latency::cpu.inst 31431750 # number of ReadReq miss cycles 591system.cpu.icache.ReadReq_miss_latency::total 31431750 # number of ReadReq miss cycles 592system.cpu.icache.demand_miss_latency::cpu.inst 31431750 # number of demand (read+write) miss cycles 593system.cpu.icache.demand_miss_latency::total 31431750 # number of demand (read+write) miss cycles 594system.cpu.icache.overall_miss_latency::cpu.inst 31431750 # number of overall miss cycles 595system.cpu.icache.overall_miss_latency::total 31431750 # number of overall miss cycles 596system.cpu.icache.ReadReq_accesses::cpu.inst 2388 # number of ReadReq accesses(hits+misses) 597system.cpu.icache.ReadReq_accesses::total 2388 # number of ReadReq accesses(hits+misses) 598system.cpu.icache.demand_accesses::cpu.inst 2388 # number of demand (read+write) accesses 599system.cpu.icache.demand_accesses::total 2388 # number of demand (read+write) accesses 600system.cpu.icache.overall_accesses::cpu.inst 2388 # number of overall (read+write) accesses 601system.cpu.icache.overall_accesses::total 2388 # number of overall (read+write) accesses 602system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204774 # miss rate for ReadReq accesses 603system.cpu.icache.ReadReq_miss_rate::total 0.204774 # miss rate for ReadReq accesses 604system.cpu.icache.demand_miss_rate::cpu.inst 0.204774 # miss rate for demand accesses 605system.cpu.icache.demand_miss_rate::total 0.204774 # miss rate for demand accesses 606system.cpu.icache.overall_miss_rate::cpu.inst 0.204774 # miss rate for overall accesses 607system.cpu.icache.overall_miss_rate::total 0.204774 # miss rate for overall accesses 608system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64277.607362 # average ReadReq miss latency 609system.cpu.icache.ReadReq_avg_miss_latency::total 64277.607362 # average ReadReq miss latency 610system.cpu.icache.demand_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency 611system.cpu.icache.demand_avg_miss_latency::total 64277.607362 # average overall miss latency 612system.cpu.icache.overall_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency 613system.cpu.icache.overall_avg_miss_latency::total 64277.607362 # average overall miss latency | 629system.cpu.icache.ReadReq_miss_latency::cpu.inst 31330250 # number of ReadReq miss cycles 630system.cpu.icache.ReadReq_miss_latency::total 31330250 # number of ReadReq miss cycles 631system.cpu.icache.demand_miss_latency::cpu.inst 31330250 # number of demand (read+write) miss cycles 632system.cpu.icache.demand_miss_latency::total 31330250 # number of demand (read+write) miss cycles 633system.cpu.icache.overall_miss_latency::cpu.inst 31330250 # number of overall miss cycles 634system.cpu.icache.overall_miss_latency::total 31330250 # number of overall miss cycles 635system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) 637system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses 638system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses 639system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses 640system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses 641system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses 642system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses 643system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses 644system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses 645system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses 646system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses 647system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900 # average ReadReq miss latency 648system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900 # average ReadReq miss latency 649system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency 650system.cpu.icache.demand_avg_miss_latency::total 64070.040900 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::total 64070.040900 # average overall miss latency |
| 614system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 615system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 616system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 617system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 618system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 619system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 620system.cpu.icache.fast_writes 0 # number of fast writes performed 621system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 626system.cpu.icache.overall_mshr_hits::cpu.inst 174 # number of overall MSHR hits 627system.cpu.icache.overall_mshr_hits::total 174 # number of overall MSHR hits 628system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 629system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 630system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 631system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 632system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 633system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses | 653system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 658system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.icache.fast_writes 0 # number of fast writes performed 660system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 665system.cpu.icache.overall_mshr_hits::cpu.inst 174 # number of overall MSHR hits 666system.cpu.icache.overall_mshr_hits::total 174 # number of overall MSHR hits 667system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 668system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 669system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 670system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 671system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 672system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses |
| 634system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22098000 # number of ReadReq MSHR miss cycles 635system.cpu.icache.ReadReq_mshr_miss_latency::total 22098000 # number of ReadReq MSHR miss cycles 636system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22098000 # number of demand (read+write) MSHR miss cycles 637system.cpu.icache.demand_mshr_miss_latency::total 22098000 # number of demand (read+write) MSHR miss cycles 638system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22098000 # number of overall MSHR miss cycles 639system.cpu.icache.overall_mshr_miss_latency::total 22098000 # number of overall MSHR miss cycles 640system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for ReadReq accesses 641system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131910 # mshr miss rate for ReadReq accesses 642system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for demand accesses 643system.cpu.icache.demand_mshr_miss_rate::total 0.131910 # mshr miss rate for demand accesses 644system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for overall accesses 645system.cpu.icache.overall_mshr_miss_rate::total 0.131910 # mshr miss rate for overall accesses 646system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70152.380952 # average ReadReq mshr miss latency 647system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70152.380952 # average ReadReq mshr miss latency 648system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency 649system.cpu.icache.demand_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency 650system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency 651system.cpu.icache.overall_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency | 673system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22016000 # number of ReadReq MSHR miss cycles 674system.cpu.icache.ReadReq_mshr_miss_latency::total 22016000 # number of ReadReq MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22016000 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::total 22016000 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22016000 # number of overall MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::total 22016000 # number of overall MSHR miss cycles 679system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses 680system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses 681system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses 682system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses 684system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492 # average ReadReq mshr miss latency 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492 # average ReadReq mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency |
| 652system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 653system.cpu.l2cache.tags.replacements 0 # number of replacements | 691system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 692system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 654system.cpu.l2cache.tags.tagsinuse 219.244506 # Cycle average of tags in use | 693system.cpu.l2cache.tags.tagsinuse 219.258059 # Cycle average of tags in use |
| 655system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 656system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. 657system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. 658system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 694system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 695system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. 696system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. 697system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 659system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.494883 # Average occupied blocks per requestor 660system.cpu.l2cache.tags.occ_blocks::cpu.data 59.749622 # Average occupied blocks per requestor 661system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004867 # Average percentage of cache occupancy | 698system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.507047 # Average occupied blocks per requestor 699system.cpu.l2cache.tags.occ_blocks::cpu.data 59.751013 # Average occupied blocks per requestor 700system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy |
| 662system.cpu.l2cache.tags.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy 663system.cpu.l2cache.tags.occ_percent::total 0.006691 # Average percentage of cache occupancy 664system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id 665system.cpu.l2cache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id 666system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 667system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id 668system.cpu.l2cache.tags.tag_accesses 4399 # Number of tag accesses 669system.cpu.l2cache.tags.data_accesses 4399 # Number of data accesses --- 9 unchanged lines hidden (view full) --- 679system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 680system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 681system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 682system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 683system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses 684system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 685system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 686system.cpu.l2cache.overall_misses::total 488 # number of overall misses | 701system.cpu.l2cache.tags.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_percent::total 0.006691 # Average percentage of cache occupancy 703system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id 706system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id 707system.cpu.l2cache.tags.tag_accesses 4399 # Number of tag accesses 708system.cpu.l2cache.tags.data_accesses 4399 # Number of data accesses --- 9 unchanged lines hidden (view full) --- 718system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 719system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 720system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 721system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 722system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses 723system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 724system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 725system.cpu.l2cache.overall_misses::total 488 # number of overall misses |
| 687system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21772000 # number of ReadReq miss cycles 688system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7725500 # number of ReadReq miss cycles 689system.cpu.l2cache.ReadReq_miss_latency::total 29497500 # number of ReadReq miss cycles 690system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5467500 # number of ReadExReq miss cycles 691system.cpu.l2cache.ReadExReq_miss_latency::total 5467500 # number of ReadExReq miss cycles 692system.cpu.l2cache.demand_miss_latency::cpu.inst 21772000 # number of demand (read+write) miss cycles 693system.cpu.l2cache.demand_miss_latency::cpu.data 13193000 # number of demand (read+write) miss cycles 694system.cpu.l2cache.demand_miss_latency::total 34965000 # number of demand (read+write) miss cycles 695system.cpu.l2cache.overall_miss_latency::cpu.inst 21772000 # number of overall miss cycles 696system.cpu.l2cache.overall_miss_latency::cpu.data 13193000 # number of overall miss cycles 697system.cpu.l2cache.overall_miss_latency::total 34965000 # number of overall miss cycles | 726system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21690000 # number of ReadReq miss cycles 727system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718000 # number of ReadReq miss cycles 728system.cpu.l2cache.ReadReq_miss_latency::total 29408000 # number of ReadReq miss cycles 729system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles 730system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles 731system.cpu.l2cache.demand_miss_latency::cpu.inst 21690000 # number of demand (read+write) miss cycles 732system.cpu.l2cache.demand_miss_latency::cpu.data 13435750 # number of demand (read+write) miss cycles 733system.cpu.l2cache.demand_miss_latency::total 35125750 # number of demand (read+write) miss cycles 734system.cpu.l2cache.overall_miss_latency::cpu.inst 21690000 # number of overall miss cycles 735system.cpu.l2cache.overall_miss_latency::cpu.data 13435750 # number of overall miss cycles 736system.cpu.l2cache.overall_miss_latency::total 35125750 # number of overall miss cycles |
| 698system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 699system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 700system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) 701system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 702system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 703system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 704system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 705system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 712system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 713system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 714system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 715system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 716system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 717system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 718system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 719system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses | 737system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 738system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 739system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) 740system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 741system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 742system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 743system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 744system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 751system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 752system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 753system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 754system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 755system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 756system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 757system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 758system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses |
| 720system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69337.579618 # average ReadReq miss latency 721system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76490.099010 # average ReadReq miss latency 722system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.313253 # average ReadReq miss latency 723system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74897.260274 # average ReadExReq miss latency 724system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74897.260274 # average ReadExReq miss latency 725system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency 726system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency 727system.cpu.l2cache.demand_avg_miss_latency::total 71649.590164 # average overall miss latency 728system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency 729system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency 730system.cpu.l2cache.overall_avg_miss_latency::total 71649.590164 # average overall miss latency | 759system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121 # average ReadReq miss latency 760system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584 # average ReadReq miss latency 761system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602 # average ReadReq miss latency 762system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466 # average ReadExReq miss latency 763system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466 # average ReadExReq miss latency 764system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency 765system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency 766system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902 # average overall miss latency 767system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency 768system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency 769system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902 # average overall miss latency |
| 731system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 732system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 733system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 734system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 735system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 736system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 737system.cpu.l2cache.fast_writes 0 # number of fast writes performed 738system.cpu.l2cache.cache_copies 0 # number of cache copies performed 739system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 740system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 741system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses 742system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 743system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 744system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 745system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 746system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses 747system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 748system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 749system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses | 770system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 771system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 772system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 773system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 774system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 775system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 776system.cpu.l2cache.fast_writes 0 # number of fast writes performed 777system.cpu.l2cache.cache_copies 0 # number of cache copies performed 778system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 779system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 780system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses 781system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 782system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 783system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 784system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 785system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses 786system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 787system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 788system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses |
| 750system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17823000 # number of ReadReq MSHR miss cycles 751system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6485500 # number of ReadReq MSHR miss cycles 752system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308500 # number of ReadReq MSHR miss cycles 753system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4573000 # number of ReadExReq MSHR miss cycles 754system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4573000 # number of ReadExReq MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17823000 # number of demand (read+write) MSHR miss cycles 756system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11058500 # number of demand (read+write) MSHR miss cycles 757system.cpu.l2cache.demand_mshr_miss_latency::total 28881500 # number of demand (read+write) MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17823000 # number of overall MSHR miss cycles 759system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11058500 # number of overall MSHR miss cycles 760system.cpu.l2cache.overall_mshr_miss_latency::total 28881500 # number of overall MSHR miss cycles | 789system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17737500 # number of ReadReq MSHR miss cycles 790system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6477000 # number of ReadReq MSHR miss cycles 791system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24214500 # number of ReadReq MSHR miss cycles 792system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4818250 # number of ReadExReq MSHR miss cycles 793system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4818250 # number of ReadExReq MSHR miss cycles 794system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17737500 # number of demand (read+write) MSHR miss cycles 795system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11295250 # number of demand (read+write) MSHR miss cycles 796system.cpu.l2cache.demand_mshr_miss_latency::total 29032750 # number of demand (read+write) MSHR miss cycles 797system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17737500 # number of overall MSHR miss cycles 798system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11295250 # number of overall MSHR miss cycles 799system.cpu.l2cache.overall_mshr_miss_latency::total 29032750 # number of overall MSHR miss cycles |
| 761system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 762system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 763system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses 764system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 765system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 766system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 768system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 769system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 771system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses | 800system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 801system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 802system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses 803system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 804system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 805system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 806system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 807system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 808system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 809system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 810system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses |
| 772system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56761.146497 # average ReadReq mshr miss latency 773system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64212.871287 # average ReadReq mshr miss latency 774system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58574.698795 # average ReadReq mshr miss latency 775system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62643.835616 # average ReadExReq mshr miss latency 776system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62643.835616 # average ReadExReq mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency 778system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency 779system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency 781system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency 782system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency | 811system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503 # average ReadReq mshr miss latency 812system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871 # average ReadReq mshr miss latency 813system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58348.192771 # average ReadReq mshr miss latency 814system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66003.424658 # average ReadExReq mshr miss latency 815system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66003.424658 # average ReadExReq mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency 817system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency 818system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency 820system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency 821system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency |
| 783system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 784system.cpu.dcache.tags.replacements 0 # number of replacements | 822system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 823system.cpu.dcache.tags.replacements 0 # number of replacements |
| 785system.cpu.dcache.tags.tagsinuse 107.267771 # Cycle average of tags in use 786system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. | 824system.cpu.dcache.tags.tagsinuse 107.231811 # Cycle average of tags in use 825system.cpu.dcache.tags.total_refs 2229 # Total number of references to valid blocks. |
| 787system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. | 826system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. |
| 788system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. | 827system.cpu.dcache.tags.avg_refs 12.810345 # Average number of references to valid blocks. |
| 789system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 828system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 790system.cpu.dcache.tags.occ_blocks::cpu.data 107.267771 # Average occupied blocks per requestor 791system.cpu.dcache.tags.occ_percent::cpu.data 0.026188 # Average percentage of cache occupancy 792system.cpu.dcache.tags.occ_percent::total 0.026188 # Average percentage of cache occupancy | 829system.cpu.dcache.tags.occ_blocks::cpu.data 107.231811 # Average occupied blocks per requestor 830system.cpu.dcache.tags.occ_percent::cpu.data 0.026180 # Average percentage of cache occupancy 831system.cpu.dcache.tags.occ_percent::total 0.026180 # Average percentage of cache occupancy |
| 793system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id 794system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 795system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 796system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id | 832system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id 833system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 834system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 835system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id |
| 797system.cpu.dcache.tags.tag_accesses 5694 # Number of tag accesses 798system.cpu.dcache.tags.data_accesses 5694 # Number of data accesses 799system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits 800system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits | 836system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses 837system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses 838system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits 839system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits |
| 801system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 802system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits | 840system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 841system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits |
| 803system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits 804system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits 805system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits 806system.cpu.dcache.overall_hits::total 2230 # number of overall hits | 842system.cpu.dcache.demand_hits::cpu.data 2229 # number of demand (read+write) hits 843system.cpu.dcache.demand_hits::total 2229 # number of demand (read+write) hits 844system.cpu.dcache.overall_hits::cpu.data 2229 # number of overall hits 845system.cpu.dcache.overall_hits::total 2229 # number of overall hits |
| 807system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses 808system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses 809system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 810system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 811system.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses 812system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses 813system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses 814system.cpu.dcache.overall_misses::total 530 # number of overall misses | 846system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses 847system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses 848system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 849system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 850system.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses 851system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses 852system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses 853system.cpu.dcache.overall_misses::total 530 # number of overall misses |
| 815system.cpu.dcache.ReadReq_miss_latency::cpu.data 11467500 # number of ReadReq miss cycles 816system.cpu.dcache.ReadReq_miss_latency::total 11467500 # number of ReadReq miss cycles 817system.cpu.dcache.WriteReq_miss_latency::cpu.data 23223733 # number of WriteReq miss cycles 818system.cpu.dcache.WriteReq_miss_latency::total 23223733 # number of WriteReq miss cycles 819system.cpu.dcache.demand_miss_latency::cpu.data 34691233 # number of demand (read+write) miss cycles 820system.cpu.dcache.demand_miss_latency::total 34691233 # number of demand (read+write) miss cycles 821system.cpu.dcache.overall_miss_latency::cpu.data 34691233 # number of overall miss cycles 822system.cpu.dcache.overall_miss_latency::total 34691233 # number of overall miss cycles 823system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) 824system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) | 854system.cpu.dcache.ReadReq_miss_latency::cpu.data 11460500 # number of ReadReq miss cycles 855system.cpu.dcache.ReadReq_miss_latency::total 11460500 # number of ReadReq miss cycles 856system.cpu.dcache.WriteReq_miss_latency::cpu.data 25449978 # number of WriteReq miss cycles 857system.cpu.dcache.WriteReq_miss_latency::total 25449978 # number of WriteReq miss cycles 858system.cpu.dcache.demand_miss_latency::cpu.data 36910478 # number of demand (read+write) miss cycles 859system.cpu.dcache.demand_miss_latency::total 36910478 # number of demand (read+write) miss cycles 860system.cpu.dcache.overall_miss_latency::cpu.data 36910478 # number of overall miss cycles 861system.cpu.dcache.overall_miss_latency::total 36910478 # number of overall miss cycles 862system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) 863system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) |
| 825system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 826system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) | 864system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 865system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) |
| 827system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses 828system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses 829system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses 830system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses 831system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090237 # miss rate for ReadReq accesses 832system.cpu.dcache.ReadReq_miss_rate::total 0.090237 # miss rate for ReadReq accesses | 866system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses 867system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses 868system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses 869system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses 870system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090285 # miss rate for ReadReq accesses 871system.cpu.dcache.ReadReq_miss_rate::total 0.090285 # miss rate for ReadReq accesses |
| 833system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 834system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses | 872system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 873system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses |
| 835system.cpu.dcache.demand_miss_rate::cpu.data 0.192029 # miss rate for demand accesses 836system.cpu.dcache.demand_miss_rate::total 0.192029 # miss rate for demand accesses 837system.cpu.dcache.overall_miss_rate::cpu.data 0.192029 # miss rate for overall accesses 838system.cpu.dcache.overall_miss_rate::total 0.192029 # miss rate for overall accesses 839system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509 # average ReadReq miss latency 840system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509 # average ReadReq miss latency 841system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067 # average WriteReq miss latency 842system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067 # average WriteReq miss latency 843system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency 844system.cpu.dcache.demand_avg_miss_latency::total 65455.156604 # average overall miss latency 845system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency 846system.cpu.dcache.overall_avg_miss_latency::total 65455.156604 # average overall miss latency 847system.cpu.dcache.blocked_cycles::no_mshrs 1533 # number of cycles access was blocked | 874system.cpu.dcache.demand_miss_rate::cpu.data 0.192099 # miss rate for demand accesses 875system.cpu.dcache.demand_miss_rate::total 0.192099 # miss rate for demand accesses 876system.cpu.dcache.overall_miss_rate::cpu.data 0.192099 # miss rate for overall accesses 877system.cpu.dcache.overall_miss_rate::total 0.192099 # miss rate for overall accesses 878system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836 # average ReadReq miss latency 879system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836 # average ReadReq miss latency 880system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621 # average WriteReq miss latency 881system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621 # average WriteReq miss latency 882system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency 883system.cpu.dcache.demand_avg_miss_latency::total 69642.411321 # average overall miss latency 884system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency 885system.cpu.dcache.overall_avg_miss_latency::total 69642.411321 # average overall miss latency 886system.cpu.dcache.blocked_cycles::no_mshrs 1529 # number of cycles access was blocked |
| 848system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 887system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 849system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked | 888system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked |
| 850system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 889system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 851system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.862069 # average number of cycles each access was blocked | 890system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.970588 # average number of cycles each access was blocked |
| 852system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 853system.cpu.dcache.fast_writes 0 # number of fast writes performed 854system.cpu.dcache.cache_copies 0 # number of cache copies performed 855system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 856system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 857system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 858system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 859system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits 860system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits 861system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits 862system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits 863system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 864system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 865system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 866system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 867system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 868system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 869system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 870system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses | 891system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu.dcache.fast_writes 0 # number of fast writes performed 893system.cpu.dcache.cache_copies 0 # number of cache copies performed 894system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 895system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 896system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 897system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 898system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits 899system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits 900system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits 901system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits 902system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 903system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 904system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 905system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 906system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 907system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 908system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 909system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses |
| 871system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7915000 # number of ReadReq MSHR miss cycles 872system.cpu.dcache.ReadReq_mshr_miss_latency::total 7915000 # number of ReadReq MSHR miss cycles 873system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5462500 # number of WriteReq MSHR miss cycles 874system.cpu.dcache.WriteReq_mshr_miss_latency::total 5462500 # number of WriteReq MSHR miss cycles 875system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13377500 # number of demand (read+write) MSHR miss cycles 876system.cpu.dcache.demand_mshr_miss_latency::total 13377500 # number of demand (read+write) MSHR miss cycles 877system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13377500 # number of overall MSHR miss cycles 878system.cpu.dcache.overall_mshr_miss_latency::total 13377500 # number of overall MSHR miss cycles 879system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses 880system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses | 910system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7907500 # number of ReadReq MSHR miss cycles 911system.cpu.dcache.ReadReq_mshr_miss_latency::total 7907500 # number of ReadReq MSHR miss cycles 912system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5712750 # number of WriteReq MSHR miss cycles 913system.cpu.dcache.WriteReq_mshr_miss_latency::total 5712750 # number of WriteReq MSHR miss cycles 914system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13620250 # number of demand (read+write) MSHR miss cycles 915system.cpu.dcache.demand_mshr_miss_latency::total 13620250 # number of demand (read+write) MSHR miss cycles 916system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13620250 # number of overall MSHR miss cycles 917system.cpu.dcache.overall_mshr_miss_latency::total 13620250 # number of overall MSHR miss cycles 918system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053854 # mshr miss rate for ReadReq accesses 919system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053854 # mshr miss rate for ReadReq accesses |
| 881system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 882system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses | 920system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 921system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses |
| 883system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for demand accesses 884system.cpu.dcache.demand_mshr_miss_rate::total 0.063043 # mshr miss rate for demand accesses 885system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for overall accesses 886system.cpu.dcache.overall_mshr_miss_rate::total 0.063043 # mshr miss rate for overall accesses 887system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216 # average ReadReq mshr miss latency 888system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216 # average ReadReq mshr miss latency 889system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556 # average WriteReq mshr miss latency 890system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556 # average WriteReq mshr miss latency 891system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency 892system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency 893system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency 894system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency | 922system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses 923system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses 924system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses 925system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses 926system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804 # average ReadReq mshr miss latency 927system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804 # average ReadReq mshr miss latency 928system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average WriteReq mshr miss latency 929system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000 # average WriteReq mshr miss latency 930system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency 931system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency 932system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency 933system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency |
| 895system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 896 897---------- End Simulation Statistics ---------- | 934system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 935 936---------- End Simulation Statistics ---------- |