| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated |
| 4sim_ticks 16039500 # Number of ticks simulated 5final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1336 # Simulator instruction rate (inst/s) 8host_op_rate 1336 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3362323 # Simulator tick rate (ticks/s) 10host_mem_usage 225744 # Number of bytes of host memory used 11host_seconds 4.77 # Real time elapsed on the host |
| 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 16system.physmem.bytes_read::total 31104 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 486 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 486 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 31104 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q --- 27 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 15803000 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 486 # Categorize read packet sizes |
| 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 88system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 152system.physmem.totQLat 2921750 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests |
| 154system.physmem.totBusLat 2430000 # Total cycles spent in databus access 155system.physmem.totBankLat 8305000 # Total cycles spent in bank access |
| 156system.physmem.avgQLat 6011.83 # Average queueing delay per request |
| 157system.physmem.avgBankLat 17088.48 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 159system.physmem.avgMemAccLat 28100.31 # Average memory access latency 160system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s |
| 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 162system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s |
| 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 165system.physmem.busUtil 15.15 # Data bus utilization in percentage |
| 166system.physmem.avgRdQLen 0.85 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time 168system.physmem.readRowHits 396 # Number of row buffer hits during reads 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes 170system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 172system.physmem.avgGap 32516.46 # Average gap between requests |
| 173system.cpu.branchPred.lookups 2896 # Number of BP lookups 174system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 746 # Number of BTB hits 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 179system.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. --- 26 unchanged lines hidden (view full) --- 207system.cpu.itb.write_misses 0 # DTB write misses 208system.cpu.itb.write_acv 0 # DTB write access violations 209system.cpu.itb.write_accesses 0 # DTB write accesses 210system.cpu.itb.data_hits 0 # DTB hits 211system.cpu.itb.data_misses 0 # DTB misses 212system.cpu.itb.data_acv 0 # DTB access violations 213system.cpu.itb.data_accesses 0 # DTB accesses 214system.cpu.workload.num_syscalls 17 # Number of system calls |
| 215system.cpu.numCycles 32080 # number of cpu cycles simulated |
| 216system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 217system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 218system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss 219system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed 220system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered 221system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken 222system.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked 223system.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing --- 14 unchanged lines hidden (view full) --- 238system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::7 185 1.28% 91.30% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) |
| 246system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle 247system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle |
| 248system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle 249system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked 250system.cpu.decode.RunCycles 2753 # Number of cycles decode is running 251system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking 252system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing 253system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch 254system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction 255system.cpu.decode.DecodedInsts 15363 # Number of instructions handled by decode --- 108 unchanged lines hidden (view full) --- 364system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued 367system.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued 368system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued 369system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 370system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 371system.cpu.iq.FU_type_0::total 10806 # Type of FU issued |
| 372system.cpu.iq.rate 0.336845 # Inst issue rate |
| 373system.cpu.iq.fu_busy_cnt 118 # FU busy when requested 374system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) 375system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads 376system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes 377system.cpu.iq.int_inst_queue_wakeup_accesses 9700 # Number of integer instruction queue wakeup accesses 378system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 379system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 380system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses --- 27 unchanged lines hidden (view full) --- 408system.cpu.iew.iewExecutedInsts 10154 # Number of executed instructions 409system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed 410system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute 411system.cpu.iew.exec_swp 0 # number of swp insts executed 412system.cpu.iew.exec_nop 86 # number of nop insts executed 413system.cpu.iew.exec_refs 3233 # number of memory reference insts executed 414system.cpu.iew.exec_branches 1613 # Number of branches executed 415system.cpu.iew.exec_stores 1101 # Number of stores executed |
| 416system.cpu.iew.exec_rate 0.316521 # Inst execution rate |
| 417system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit 418system.cpu.iew.wb_count 9710 # cumulative count of insts written-back 419system.cpu.iew.wb_producers 5134 # num instructions producing a value 420system.cpu.iew.wb_consumers 6919 # num instructions consuming a value 421system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 422system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle |
| 423system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back 424system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 425system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit 426system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 427system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted 428system.cpu.commit.committed_per_cycle::samples 13297 # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::mean 0.480484 # Number of insts commited each cycle 430system.cpu.commit.committed_per_cycle::stdev 1.303494 # Number of insts commited each cycle --- 21 unchanged lines hidden (view full) --- 452system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 453system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 454system.cpu.commit.function_calls 127 # Number of function calls committed. 455system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached 456system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 457system.cpu.rob.rob_reads 25928 # The number of ROB reads 458system.cpu.rob.rob_writes 27481 # The number of ROB writes 459system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 460system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 461system.cpu.committedInsts 6372 # Number of Instructions Simulated 462system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 463system.cpu.committedInsts_total 6372 # Number of Instructions Simulated |
| 464system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction 465system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads 466system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle 467system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads |
| 468system.cpu.int_regfile_reads 12888 # number of integer regfile reads 469system.cpu.int_regfile_writes 7343 # number of integer regfile writes 470system.cpu.fp_regfile_reads 8 # number of floating regfile reads 471system.cpu.fp_regfile_writes 2 # number of floating regfile writes 472system.cpu.misc_regfile_reads 1 # number of misc regfile reads 473system.cpu.misc_regfile_writes 1 # number of misc regfile writes 474system.cpu.icache.replacements 0 # number of replacements |
| 475system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use |
| 476system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. 477system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. 478system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. 479system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 480system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor 481system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy 482system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy |
| 483system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits 484system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits 485system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits 486system.cpu.icache.demand_hits::total 1869 # number of demand (read+write) hits 487system.cpu.icache.overall_hits::cpu.inst 1869 # number of overall hits 488system.cpu.icache.overall_hits::total 1869 # number of overall hits 489system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses 490system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses 491system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses 492system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses 493system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses 494system.cpu.icache.overall_misses::total 480 # number of overall misses |
| 495system.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles 496system.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles 497system.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles 498system.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles 499system.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles 500system.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles |
| 501system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) 502system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) 503system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses 504system.cpu.icache.demand_accesses::total 2349 # number of demand (read+write) accesses 505system.cpu.icache.overall_accesses::cpu.inst 2349 # number of overall (read+write) accesses 506system.cpu.icache.overall_accesses::total 2349 # number of overall (read+write) accesses 507system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204342 # miss rate for ReadReq accesses 508system.cpu.icache.ReadReq_miss_rate::total 0.204342 # miss rate for ReadReq accesses 509system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 # miss rate for demand accesses 510system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses 511system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses 512system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses |
| 513system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency 514system.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency 515system.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency 516system.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency 517system.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency 518system.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency |
| 519system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 520system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 521system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 522system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 523system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 524system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 525system.cpu.icache.fast_writes 0 # number of fast writes performed 526system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 531system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits 532system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits 533system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 534system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 535system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 536system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 537system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 538system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses |
| 539system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles 540system.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles 541system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles 542system.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles 543system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles 544system.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles |
| 545system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses 546system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses 547system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses 548system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses 549system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses 550system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses |
| 551system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency 552system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency 553system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency 554system.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency 555system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency 556system.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency |
| 557system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 558system.cpu.l2cache.replacements 0 # number of replacements |
| 559system.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use |
| 560system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 561system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. 562system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. 563system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 564system.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor 565system.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy |
| 567system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy |
| 568system.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy |
| 569system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 570system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 571system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 572system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 573system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 574system.cpu.l2cache.overall_hits::total 1 # number of overall hits 575system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses 576system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 577system.cpu.l2cache.ReadReq_misses::total 413 # number of ReadReq misses 578system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 579system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 580system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 581system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 582system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses 583system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 584system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 585system.cpu.l2cache.overall_misses::total 486 # number of overall misses |
| 586system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles |
| 587system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles |
| 588system.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles |
| 589system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles 590system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles |
| 591system.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles |
| 592system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles |
| 593system.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles 594system.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles |
| 595system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles |
| 596system.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles |
| 597system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) 598system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 599system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) 600system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 601system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 602system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses 603system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 604system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 611system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 612system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 613system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 614system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 615system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses 616system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 617system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 618system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses |
| 619system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency |
| 620system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency |
| 621system.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency |
| 622system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency 623system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency |
| 624system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency |
| 625system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency |
| 626system.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency 627system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency |
| 628system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency |
| 629system.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency |
| 630system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.l2cache.fast_writes 0 # number of fast writes performed 637system.cpu.l2cache.cache_copies 0 # number of cache copies performed 638system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses 639system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 640system.cpu.l2cache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses 641system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 642system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 643system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 644system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 645system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses 646system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 647system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 648system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses |
| 649system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles 651system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles 652system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles 654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles 657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles |
| 660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses 661system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 662system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses 663system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 664system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 665system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 666system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 667system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses 668system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 669system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 670system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses |
| 671system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency 672system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency 673system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency 674system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency 675system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency 678system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency 680system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency 681system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency |
| 682system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 683system.cpu.dcache.replacements 0 # number of replacements |
| 684system.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use |
| 685system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. 686system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 687system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. 688system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 689system.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor 690system.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy 691system.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy |
| 692system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits 693system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits 694system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 695system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 696system.cpu.dcache.demand_hits::cpu.data 2262 # number of demand (read+write) hits 697system.cpu.dcache.demand_hits::total 2262 # number of demand (read+write) hits 698system.cpu.dcache.overall_hits::cpu.data 2262 # number of overall hits 699system.cpu.dcache.overall_hits::total 2262 # number of overall hits --- 91 unchanged lines hidden --- |