4,5c4,5
< sim_ticks 20671000 # Number of ticks simulated
< final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 21065000 # Number of ticks simulated
> final_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 10783 # Simulator instruction rate (inst/s)
< host_op_rate 10783 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 34979840 # Simulator tick rate (ticks/s)
< host_mem_usage 229184 # Number of bytes of host memory used
< host_seconds 0.59 # Real time elapsed on the host
---
> host_inst_rate 31290 # Simulator instruction rate (inst/s)
> host_op_rate 31288 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 103426086 # Simulator tick rate (ticks/s)
> host_mem_usage 226120 # Number of bytes of host memory used
> host_seconds 0.20 # Real time elapsed on the host
22,89c22,91
< system.physmem.bw_read::cpu.inst 969087127 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 538725751 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1507812878 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 969087127 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 969087127 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller
< system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
< system.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
< system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
< system.physmem.bytesRead 31168 # Total number of bytes read from memory
< system.physmem.bytesWritten 0 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
< system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
< system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
< system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
< system.physmem.totGap 20638000 # Total gap between requests
< system.physmem.readPktSize::0 0 # Categorize read packet sizes
< system.physmem.readPktSize::1 0 # Categorize read packet sizes
< system.physmem.readPktSize::2 0 # Categorize read packet sizes
< system.physmem.readPktSize::3 0 # Categorize read packet sizes
< system.physmem.readPktSize::4 0 # Categorize read packet sizes
< system.physmem.readPktSize::5 0 # Categorize read packet sizes
< system.physmem.readPktSize::6 488 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # Categorize write packet sizes
< system.physmem.writePktSize::1 0 # Categorize write packet sizes
< system.physmem.writePktSize::2 0 # Categorize write packet sizes
< system.physmem.writePktSize::3 0 # Categorize write packet sizes
< system.physmem.writePktSize::4 0 # Categorize write packet sizes
< system.physmem.writePktSize::5 0 # Categorize write packet sizes
< system.physmem.writePktSize::6 0 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 286 # What read queue length does an incoming req see
---
> system.physmem.bw_read::cpu.inst 950961310 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 528649418 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1479610729 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 950961310 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 950961310 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 950961310 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 528649418 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1479610729 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 488 # Number of read requests accepted
> system.physmem.writeReqs 0 # Number of write requests accepted
> system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
> system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 69 # Per bank write bursts
> system.physmem.perBankRdBursts::1 34 # Per bank write bursts
> system.physmem.perBankRdBursts::2 32 # Per bank write bursts
> system.physmem.perBankRdBursts::3 47 # Per bank write bursts
> system.physmem.perBankRdBursts::4 43 # Per bank write bursts
> system.physmem.perBankRdBursts::5 21 # Per bank write bursts
> system.physmem.perBankRdBursts::6 1 # Per bank write bursts
> system.physmem.perBankRdBursts::7 3 # Per bank write bursts
> system.physmem.perBankRdBursts::8 0 # Per bank write bursts
> system.physmem.perBankRdBursts::9 1 # Per bank write bursts
> system.physmem.perBankRdBursts::10 23 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24 # Per bank write bursts
> system.physmem.perBankRdBursts::12 14 # Per bank write bursts
> system.physmem.perBankRdBursts::13 119 # Per bank write bursts
> system.physmem.perBankRdBursts::14 45 # Per bank write bursts
> system.physmem.perBankRdBursts::15 12 # Per bank write bursts
> system.physmem.perBankWrBursts::0 0 # Per bank write bursts
> system.physmem.perBankWrBursts::1 0 # Per bank write bursts
> system.physmem.perBankWrBursts::2 0 # Per bank write bursts
> system.physmem.perBankWrBursts::3 0 # Per bank write bursts
> system.physmem.perBankWrBursts::4 0 # Per bank write bursts
> system.physmem.perBankWrBursts::5 0 # Per bank write bursts
> system.physmem.perBankWrBursts::6 0 # Per bank write bursts
> system.physmem.perBankWrBursts::7 0 # Per bank write bursts
> system.physmem.perBankWrBursts::8 0 # Per bank write bursts
> system.physmem.perBankWrBursts::9 0 # Per bank write bursts
> system.physmem.perBankWrBursts::10 0 # Per bank write bursts
> system.physmem.perBankWrBursts::11 0 # Per bank write bursts
> system.physmem.perBankWrBursts::12 0 # Per bank write bursts
> system.physmem.perBankWrBursts::13 0 # Per bank write bursts
> system.physmem.perBankWrBursts::14 0 # Per bank write bursts
> system.physmem.perBankWrBursts::15 0 # Per bank write bursts
> system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 21032000 # Total gap between requests
> system.physmem.readPktSize::0 0 # Read request sizes (log2)
> system.physmem.readPktSize::1 0 # Read request sizes (log2)
> system.physmem.readPktSize::2 0 # Read request sizes (log2)
> system.physmem.readPktSize::3 0 # Read request sizes (log2)
> system.physmem.readPktSize::4 0 # Read request sizes (log2)
> system.physmem.readPktSize::5 0 # Read request sizes (log2)
> system.physmem.readPktSize::6 488 # Read request sizes (log2)
> system.physmem.writePktSize::0 0 # Write request sizes (log2)
> system.physmem.writePktSize::1 0 # Write request sizes (log2)
> system.physmem.writePktSize::2 0 # Write request sizes (log2)
> system.physmem.writePktSize::3 0 # Write request sizes (log2)
> system.physmem.writePktSize::4 0 # Write request sizes (log2)
> system.physmem.writePktSize::5 0 # Write request sizes (log2)
> system.physmem.writePktSize::6 0 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see
91,92c93,94
< system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
153,188c155,195
< system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation
< system.physmem.totQLat 2449250 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 12424250 # Sum of mem lat for all requests
< system.physmem.totBusLat 2440000 # Total cycles spent in databus access
< system.physmem.totBankLat 7535000 # Total cycles spent in bank access
< system.physmem.avgQLat 5018.95 # Average queueing delay per request
< system.physmem.avgBankLat 15440.57 # Average bank access latency per request
< system.physmem.avgBusLat 5000.00 # Average bus latency per request
< system.physmem.avgMemAccLat 25459.53 # Average memory access latency
< system.physmem.avgRdBW 1507.81 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 1507.81 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
< system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
< system.physmem.busUtil 11.78 # Data bus utilization in percentage
< system.physmem.avgRdQLen 0.60 # Average read queue length over time
< system.physmem.avgWrQLen 0.00 # Average write queue length over time
< system.physmem.readRowHits 419 # Number of row buffer hits during reads
---
> system.physmem.bytesPerActivate::samples 85 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 326.023529 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 167.928934 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 483.454089 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64 37 43.53% 43.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128 8 9.41% 52.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192 10 11.76% 64.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256 7 8.24% 72.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320 3 3.53% 76.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384 2 2.35% 78.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448 2 2.35% 81.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512 4 4.71% 85.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576 1 1.18% 87.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640 1 1.18% 88.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832 2 2.35% 90.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960 1 1.18% 91.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024 1 1.18% 92.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472 3 3.53% 96.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920 1 1.18% 97.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304 1 1.18% 98.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432 1 1.18% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 85 # Bytes accessed per row activation
> system.physmem.totQLat 3258750 # Total ticks spent queuing
> system.physmem.totMemAccLat 13288750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 7590000 # Total ticks spent accessing banks
> system.physmem.avgQLat 6677.77 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 15553.28 # Average bank access latency per DRAM burst
> system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 27231.05 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1482.65 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1482.65 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
> system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
> system.physmem.busUtil 11.58 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
> system.physmem.readRowHits 403 # Number of row buffer hits during reads
190c197
< system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads
192,193c199,202
< system.physmem.avgGap 42290.98 # Average gap between requests
< system.membus.throughput 1507812878 # Throughput (bytes/s)
---
> system.physmem.avgGap 43098.36 # Average gap between requests
> system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined
> system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state
> system.membus.throughput 1479610729 # Throughput (bytes/s)
204,209c213,218
< system.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
< system.membus.respLayer1.occupancy 4561500 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 22.1 # Layer utilization (%)
< system.cpu.branchPred.lookups 2888 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1700 # Number of conditional branches predicted
---
> system.membus.reqLayer0.occupancy 619000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
> system.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 21.6 # Layer utilization (%)
> system.cpu.branchPred.lookups 2884 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted
211,212c220,221
< system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 757 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 756 # Number of BTB hits
214,215c223,224
< system.cpu.branchPred.BTBHitPct 34.393458 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 418 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 34.363636 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target.
221c230
< system.cpu.dtb.read_hits 2082 # DTB read hits
---
> system.cpu.dtb.read_hits 2076 # DTB read hits
224c233
< system.cpu.dtb.read_accesses 2129 # DTB read accesses
---
> system.cpu.dtb.read_accesses 2123 # DTB read accesses
229c238
< system.cpu.dtb.data_hits 3145 # DTB hits
---
> system.cpu.dtb.data_hits 3139 # DTB hits
232,233c241,242
< system.cpu.dtb.data_accesses 3223 # DTB accesses
< system.cpu.itb.fetch_hits 2387 # ITB hits
---
> system.cpu.dtb.data_accesses 3217 # DTB accesses
> system.cpu.itb.fetch_hits 2382 # ITB hits
236c245
< system.cpu.itb.fetch_accesses 2426 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2421 # ITB accesses
250c259
< system.cpu.numCycles 41343 # number of cpu cycles simulated
---
> system.cpu.numCycles 42131 # number of cpu cycles simulated
253,259c262,268
< system.cpu.fetch.icacheStallCycles 8507 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 16592 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2888 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 1175 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1903 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 1523 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.icacheStallCycles 8530 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 16561 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2884 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 2964 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked
262,266c271,275
< system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 382 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 15073 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.100776 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.497742 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 2382 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.095812 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.493603 # Number of instructions fetched each cycle (Total)
268,276c277,285
< system.cpu.fetch.rateDist::0 12103 80.30% 80.30% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 318 2.11% 82.41% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 234 1.55% 83.96% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 215 1.43% 85.38% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 257 1.71% 87.09% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 241 1.60% 88.69% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 264 1.75% 90.44% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 184 1.22% 91.66% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1257 8.34% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 12149 80.39% 80.39% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 318 2.10% 82.49% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 234 1.55% 84.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 255 1.69% 87.14% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 240 1.59% 88.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 264 1.75% 90.48% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 183 1.21% 91.69% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1256 8.31% 100.00% # Number of instructions fetched each cycle (Total)
280,285c289,294
< system.cpu.fetch.rateDist::total 15073 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.069855 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.401325 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 9323 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 1686 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2770 # Number of cycles decode is running
---
> system.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.068453 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.393083 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2764 # Number of cycles decode is running
287c296
< system.cpu.decode.SquashCycles 1220 # Number of cycles decode is squashing
---
> system.cpu.decode.SquashCycles 1219 # Number of cycles decode is squashing
290c299
< system.cpu.decode.DecodedInsts 15336 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 15308 # Number of instructions handled by decode
292,296c301,305
< system.cpu.rename.SquashCycles 1220 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 9534 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 784 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2627 # Number of cycles rename is running
---
> system.cpu.rename.SquashCycles 1219 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 9554 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 808 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2623 # Number of cycles rename is running
298c307
< system.cpu.rename.RenamedInsts 14625 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 14604 # Number of instructions processed by rename
302,304c311,313
< system.cpu.rename.RenamedOperands 10969 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 18250 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 18241 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 10951 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 18225 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 18216 # Number of integer rename lookups
307c316
< system.cpu.rename.UndoneMaps 6399 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 6381 # Number of HB maps that are undone due to squashing
311c320
< system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 2766 # Number of loads inserted to the mem dependence unit.
315c324
< system.cpu.iq.iqInstsAdded 12962 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 12953 # Number of instructions added to the IQ (excludes non-spec)
317c326
< system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 10771 # Number of instructions issued
319,320c328,329
< system.cpu.iq.iqSquashedInstsExamined 6234 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3590 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 6180 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3598 # Number of squashed operands that are examined and possibly removed from graph
322,324c331,333
< system.cpu.iq.issued_per_cycle::samples 15073 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.715651 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.357561 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15113 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.712698 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.354769 # Number of insts issued each cycle
326,332c335,341
< system.cpu.iq.issued_per_cycle::0 10531 69.87% 69.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1674 11.11% 80.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1174 7.79% 88.76% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 731 4.85% 93.61% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 498 3.30% 96.92% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 271 1.80% 98.71% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 147 0.98% 99.69% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10572 69.95% 69.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1678 11.10% 81.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1174 7.77% 88.82% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 728 4.82% 93.64% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 498 3.30% 96.94% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 270 1.79% 98.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle
338c347
< system.cpu.iq.issued_per_cycle::total 15073 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15113 # Number of insts issued each cycle
340,370c349,379
< system.cpu.iq.fu_full::IntAlu 15 13.27% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.27% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 60 53.10% 66.37% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 38 33.63% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available
374,404c383,413
< system.cpu.iq.FU_type_0::IntAlu 7249 67.20% 67.22% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.23% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2400 22.25% 89.50% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1133 10.50% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 7236 67.18% 67.20% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.21% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.21% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2397 22.25% 89.48% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1133 10.52% 100.00% # Type of FU issued
407,413c416,422
< system.cpu.iq.FU_type_0::total 10787 # Type of FU issued
< system.cpu.iq.rate 0.260915 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 113 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.010476 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 36793 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 19230 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 9615 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 10771 # Type of FU issued
> system.cpu.iq.rate 0.255655 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 112 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.010398 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 36800 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 19167 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 9598 # Number of integer instruction queue wakeup accesses
417c426
< system.cpu.iq.int_alu_accesses 10887 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 10870 # Number of integer alu accesses
421c430
< system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1583 # Number of loads squashed
430,431c439,440
< system.cpu.iew.iewSquashCycles 1220 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewSquashCycles 1219 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 264 # Number of cycles IEW is blocking
433c442
< system.cpu.iew.iewDispatchedInsts 13080 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 13071 # Number of instructions dispatched to IQ
435c444
< system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 2766 # Number of dispatched load instructions
441,446c450,455
< system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 505 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 10087 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 700 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 381 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 10067 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 704 # Number of squashed instructions skipped in execute
449,450c458,459
< system.cpu.iew.exec_refs 3236 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1591 # Number of branches executed
---
> system.cpu.iew.exec_refs 3230 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1588 # Number of branches executed
452,456c461,465
< system.cpu.iew.exec_rate 0.243983 # Inst execution rate
< system.cpu.iew.wb_sent 9767 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 9625 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 5058 # num instructions producing a value
< system.cpu.iew.wb_consumers 6775 # num instructions consuming a value
---
> system.cpu.iew.exec_rate 0.238945 # Inst execution rate
> system.cpu.iew.wb_sent 9751 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 9608 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 5048 # num instructions producing a value
> system.cpu.iew.wb_consumers 6764 # num instructions consuming a value
458,459c467,468
< system.cpu.iew.wb_rate 0.232808 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.746568 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.228051 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.746304 # average fanout of values written-back
461c470
< system.cpu.commit.commitSquashedInsts 6689 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 6680 # The number of squashed insts skipped by commit
464,466c473,475
< system.cpu.commit.committed_per_cycle::samples 13853 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.461200 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.266599 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 13894 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.459839 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.263268 # Number of insts commited each cycle
468,476c477,485
< system.cpu.commit.committed_per_cycle::0 11035 79.66% 79.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1522 10.99% 90.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 530 3.83% 94.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 235 1.70% 96.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 147 1.06% 97.23% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 108 0.78% 98.01% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 103 0.74% 98.75% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 28 0.20% 98.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 145 1.05% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11073 79.70% 79.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1524 10.97% 90.67% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 530 3.81% 94.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 235 1.69% 96.17% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 148 1.07% 97.24% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 110 0.79% 98.03% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 103 0.74% 98.77% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 28 0.20% 98.97% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle
480c489
< system.cpu.commit.committed_per_cycle::total 13853 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 13894 # Number of insts commited each cycle
491c500
< system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached
493,496c502,505
< system.cpu.rob.rob_reads 26435 # The number of ROB reads
< system.cpu.rob.rob_writes 27385 # The number of ROB writes
< system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 26270 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 26469 # The number of ROB reads
> system.cpu.rob.rob_writes 27366 # The number of ROB writes
> system.cpu.timesIdled 271 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 27018 # Total number of cycles that the CPU has spent unscheduled due to idling
500,505c509,514
< system.cpu.cpi 6.488230 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.488230 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.154125 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.154125 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 12801 # number of integer regfile reads
< system.cpu.int_regfile_writes 7277 # number of integer regfile writes
---
> system.cpu.cpi 6.611896 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.611896 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.151243 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.151243 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 12780 # number of integer regfile reads
> system.cpu.int_regfile_writes 7264 # number of integer regfile writes
510c519
< system.cpu.toL2Bus.throughput 1510909003 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1482648944 # Throughput (bytes/s)
525,528c534,537
< system.cpu.toL2Bus.respLayer0.occupancy 531250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 278500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
530,531c539,540
< system.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 159.548856 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1893 # Total number of references to valid blocks.
533c542
< system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 6.028662 # Average number of references to valid blocks.
535,543c544,552
< system.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits
< system.cpu.icache.overall_hits::total 1898 # number of overall hits
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 159.548856 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.077905 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.077905 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 1893 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1893 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1893 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1893 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1893 # number of overall hits
> system.cpu.icache.overall_hits::total 1893 # number of overall hits
550,573c559,582
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30301750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30301750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30301750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30301750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30301750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30301750 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61966.768916 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61966.768916 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61966.768916 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61966.768916 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31381500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31381500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31381500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31381500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31381500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31381500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2382 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2382 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2382 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2382 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2382 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2382 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205290 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.205290 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.205290 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.205290 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.205290 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.205290 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64174.846626 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 64174.846626 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 64174.846626 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 64174.846626 # average overall miss latency
594,611c603,620
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21363250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 21363250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21363250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 21363250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21363250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 21363250 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67819.841270 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67819.841270 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22109000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22109000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22109000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22109000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22109000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22109000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132242 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.132242 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.132242 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70187.301587 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70187.301587 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency
614c623
< system.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 219.420292 # Cycle average of tags in use
619,623c628,632
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.632644 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 59.787647 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001825 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006696 # Average percentage of cache occupancy
641,651c650,660
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21037250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7945250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 28982500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5109500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5109500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21037250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13054750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34092000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21037250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13054750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34092000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21783000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 29501750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5390750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5390750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21783000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13109500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 34892500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21783000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13109500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 34892500 # number of overall miss cycles
674,684c683,693
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66997.611465 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78665.841584 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 69837.349398 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69993.150685 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69993.150685 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69860.655738 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69860.655738 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69372.611465 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76423.267327 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 71088.554217 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73845.890411 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73845.890411 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 71501.024590 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 71501.024590 # average overall miss latency
704,714c713,723
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17080250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6700750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23781000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4208000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4208000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17080250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10908750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 27989000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17080250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10908750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 27989000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17830500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6478250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4491250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4491250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17830500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10969500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 28800000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17830500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10969500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 28800000 # number of overall MSHR miss cycles
726,736c735,745
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54395.700637 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66344.059406 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57303.614458 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57643.835616 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57643.835616 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56785.031847 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64141.089109 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58575.301205 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61523.972603 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61523.972603 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency
739,740c748,749
< system.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 107.351368 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks.
742c751
< system.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks.
744,748c753,757
< system.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 107.351368 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.026209 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.026209 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits
751,754c760,763
< system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits
< system.cpu.dcache.overall_hits::total 2236 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits
> system.cpu.dcache.overall_hits::total 2230 # number of overall hits
763,772c772,781
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11600250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11600250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 21979228 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 21979228 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 33579478 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 33579478 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 33579478 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 33579478 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1900 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1900 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11435000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11435000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 23196228 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 23196228 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 34631228 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34631228 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34631228 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34631228 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses)
775,780c784,789
< system.cpu.dcache.demand_accesses::cpu.data 2765 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2765 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2765 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2765 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089474 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.089474 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089757 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.089757 # miss rate for ReadReq accesses
783,795c792,804
< system.cpu.dcache.demand_miss_rate::cpu.data 0.191320 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.191320 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.191320 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.191320 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68236.764706 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 68236.764706 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61223.476323 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61223.476323 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63477.274102 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63477.274102 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 1567 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.191736 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.191736 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.191736 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.191736 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67264.705882 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 67264.705882 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64613.448468 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 64613.448468 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 65465.459357 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 65465.459357 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked
799c808
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.484848 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.030303 # average number of cycles each access was blocked
819,828c828,837
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8053750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8053750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13239250 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13239250 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13239250 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13239250 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053158 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053158 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7827250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7827250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5466750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13294000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13294000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13294000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13294000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses
831,842c840,851
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79740.099010 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79740.099010 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71034.246575 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71034.246575 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77497.524752 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77497.524752 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74886.986301 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74886.986301 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency