4,5c4,5
< sim_ticks 16030500 # Number of ticks simulated
< final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 16039500 # Number of ticks simulated
> final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 76258 # Simulator instruction rate (inst/s)
< host_op_rate 76239 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 191753794 # Simulator tick rate (ticks/s)
< host_mem_usage 225728 # Number of bytes of host memory used
< host_seconds 0.08 # Real time elapsed on the host
---
> host_inst_rate 1336 # Simulator instruction rate (inst/s)
> host_op_rate 1336 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3362323 # Simulator tick rate (ticks/s)
> host_mem_usage 225744 # Number of bytes of host memory used
> host_seconds 4.77 # Real time elapsed on the host
22,29c22,29
< system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s)
73c73
< system.physmem.totGap 15817000 # Total gap between requests
---
> system.physmem.totGap 15803000 # Total gap between requests
81,100c81,87
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 0 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
---
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 0 # Categorize write packet sizes
133d119
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
166,168c152,153
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 2909986 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests
---
> system.physmem.totQLat 2921750 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests
171c156
< system.physmem.avgQLat 5987.63 # Average queueing delay per request
---
> system.physmem.avgQLat 6011.83 # Average queueing delay per request
174,175c159,160
< system.physmem.avgMemAccLat 28076.10 # Average memory access latency
< system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s
---
> system.physmem.avgMemAccLat 28100.31 # Average memory access latency
> system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s
177c162
< system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s
---
> system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s
180c165
< system.physmem.busUtil 15.16 # Data bus utilization in percentage
---
> system.physmem.busUtil 15.15 # Data bus utilization in percentage
187c172
< system.physmem.avgGap 32545.27 # Average gap between requests
---
> system.physmem.avgGap 32516.46 # Average gap between requests
230c215
< system.cpu.numCycles 32062 # number of cpu cycles simulated
---
> system.cpu.numCycles 32080 # number of cpu cycles simulated
261,262c246,247
< system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle
---
> system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle
387c372
< system.cpu.iq.rate 0.337034 # Inst issue rate
---
> system.cpu.iq.rate 0.336845 # Inst issue rate
431c416
< system.cpu.iew.exec_rate 0.316699 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.316521 # Inst execution rate
437c422
< system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle
475c460
< system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling
479,482c464,467
< system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads
490c475
< system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use
495,497c480,482
< system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy
---
> system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy
510,515c495,500
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles
528,533c513,518
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency
554,559c539,544
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16102000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 16102000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16102000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 16102000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16102000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 16102000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles
566,571c551,556
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51444.089457 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51444.089457 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency
574c559
< system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use
579,581c564,566
< system.cpu.l2cache.occ_blocks::cpu.inst 159.327355 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 60.316098 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy
583c568
< system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy
601c586
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15777000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles
603c588
< system.cpu.l2cache.ReadReq_miss_latency::total 21857500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles
606c591
< system.cpu.l2cache.demand_miss_latency::cpu.inst 15777000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles
608,609c593,594
< system.cpu.l2cache.demand_miss_latency::total 25545000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 15777000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles
611c596
< system.cpu.l2cache.overall_miss_latency::total 25545000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles
634c619
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50567.307692 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency
636c621
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52923.728814 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency
639c624
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency
641,642c626,627
< system.cpu.l2cache.demand_avg_miss_latency::total 52561.728395 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency
644c629
< system.cpu.l2cache.overall_avg_miss_latency::total 52561.728395 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency
664,674c649,659
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11907990 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848832 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16756822 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795812 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795812 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11907990 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644644 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 19552634 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11907990 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644644 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19552634 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles
686,696c671,681
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency
699c684
< system.cpu.dcache.tagsinuse 107.713176 # Cycle average of tags in use
---
> system.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use
704,706c689,691
< system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy
---
> system.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy
< sim_ticks 16030500 # Number of ticks simulated
< final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 16039500 # Number of ticks simulated
> final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 76258 # Simulator instruction rate (inst/s)
< host_op_rate 76239 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 191753794 # Simulator tick rate (ticks/s)
< host_mem_usage 225728 # Number of bytes of host memory used
< host_seconds 0.08 # Real time elapsed on the host
---
> host_inst_rate 1336 # Simulator instruction rate (inst/s)
> host_op_rate 1336 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3362323 # Simulator tick rate (ticks/s)
> host_mem_usage 225744 # Number of bytes of host memory used
> host_seconds 4.77 # Real time elapsed on the host
22,29c22,29
< system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s)
73c73
< system.physmem.totGap 15817000 # Total gap between requests
---
> system.physmem.totGap 15803000 # Total gap between requests
81,100c81,87
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 0 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
---
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 0 # Categorize write packet sizes
133d119
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
166,168c152,153
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 2909986 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests
---
> system.physmem.totQLat 2921750 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests
171c156
< system.physmem.avgQLat 5987.63 # Average queueing delay per request
---
> system.physmem.avgQLat 6011.83 # Average queueing delay per request
174,175c159,160
< system.physmem.avgMemAccLat 28076.10 # Average memory access latency
< system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s
---
> system.physmem.avgMemAccLat 28100.31 # Average memory access latency
> system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s
177c162
< system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s
---
> system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s
180c165
< system.physmem.busUtil 15.16 # Data bus utilization in percentage
---
> system.physmem.busUtil 15.15 # Data bus utilization in percentage
187c172
< system.physmem.avgGap 32545.27 # Average gap between requests
---
> system.physmem.avgGap 32516.46 # Average gap between requests
230c215
< system.cpu.numCycles 32062 # number of cpu cycles simulated
---
> system.cpu.numCycles 32080 # number of cpu cycles simulated
261,262c246,247
< system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle
---
> system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle
387c372
< system.cpu.iq.rate 0.337034 # Inst issue rate
---
> system.cpu.iq.rate 0.336845 # Inst issue rate
431c416
< system.cpu.iew.exec_rate 0.316699 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.316521 # Inst execution rate
437c422
< system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle
475c460
< system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling
479,482c464,467
< system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads
490c475
< system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use
---
> system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use
495,497c480,482
< system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy
---
> system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy
510,515c495,500
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles
528,533c513,518
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency
554,559c539,544
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16102000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 16102000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16102000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 16102000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16102000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 16102000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles
566,571c551,556
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51444.089457 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51444.089457 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency
574c559
< system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use
579,581c564,566
< system.cpu.l2cache.occ_blocks::cpu.inst 159.327355 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 60.316098 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy
583c568
< system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy
601c586
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15777000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles
603c588
< system.cpu.l2cache.ReadReq_miss_latency::total 21857500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles
606c591
< system.cpu.l2cache.demand_miss_latency::cpu.inst 15777000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles
608,609c593,594
< system.cpu.l2cache.demand_miss_latency::total 25545000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 15777000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles
611c596
< system.cpu.l2cache.overall_miss_latency::total 25545000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles
634c619
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50567.307692 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency
636c621
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52923.728814 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency
639c624
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency
641,642c626,627
< system.cpu.l2cache.demand_avg_miss_latency::total 52561.728395 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency
644c629
< system.cpu.l2cache.overall_avg_miss_latency::total 52561.728395 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency
664,674c649,659
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11907990 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848832 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16756822 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795812 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795812 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11907990 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644644 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 19552634 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11907990 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644644 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 19552634 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles
686,696c671,681
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency
699c684
< system.cpu.dcache.tagsinuse 107.713176 # Cycle average of tags in use
---
> system.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use
704,706c689,691
< system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy
---
> system.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy