7,11c7,11
< host_inst_rate 42940 # Simulator instruction rate (inst/s)
< host_op_rate 42933 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 83690683 # Simulator tick rate (ticks/s)
< host_mem_usage 215012 # Number of bytes of host memory used
< host_seconds 0.15 # Real time elapsed on the host
---
> host_inst_rate 73568 # Simulator instruction rate (inst/s)
> host_op_rate 73552 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 143373020 # Simulator tick rate (ticks/s)
> host_mem_usage 215332 # Number of bytes of host memory used
> host_seconds 0.09 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 31360 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 490 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory
> system.physmem.bytes_read::total 31360 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 490 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s)
358a366
> system.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses
359a368
> system.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses
360a370
> system.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses
361a372
> system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency
362a374
> system.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency
363a376
> system.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency
390a404
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses
391a406
> system.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses
392a408
> system.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses
393a410
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency
394a412
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency
395a414
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency
438a458
> system.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses
439a460
> system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
440a462
> system.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses
441a464
> system.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses
442a466
> system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency
443a468
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency
444a470
> system.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency
445a472
> system.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency
478a506
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses
479a508
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
480a510
> system.cpu.dcache.demand_mshr_miss_rate::total 0.064140 # mshr miss rate for demand accesses
481a512
> system.cpu.dcache.overall_mshr_miss_rate::total 0.064140 # mshr miss rate for overall accesses
482a514
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538 # average ReadReq mshr miss latency
483a516
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency
484a518
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency
485a520
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency
538a574
> system.cpu.l2cache.ReadReq_miss_rate::total 0.997613 # miss rate for ReadReq accesses
539a576
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
541a579
> system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses
543a582
> system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses
545a585
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703 # average ReadReq miss latency
546a587
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000 # average ReadExReq miss latency
548a590
> system.cpu.l2cache.demand_avg_miss_latency::total 34424.489796 # average overall miss latency
550a593
> system.cpu.l2cache.overall_avg_miss_latency::total 34424.489796 # average overall miss latency
582a626
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses
583a628
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
585a631
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses
587a634
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses
589a637
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency
590a639
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency
592a642
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency
594a645
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency
< host_inst_rate 42940 # Simulator instruction rate (inst/s)
< host_op_rate 42933 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 83690683 # Simulator tick rate (ticks/s)
< host_mem_usage 215012 # Number of bytes of host memory used
< host_seconds 0.15 # Real time elapsed on the host
---
> host_inst_rate 73568 # Simulator instruction rate (inst/s)
> host_op_rate 73552 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 143373020 # Simulator tick rate (ticks/s)
> host_mem_usage 215332 # Number of bytes of host memory used
> host_seconds 0.09 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 31360 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 490 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory
> system.physmem.bytes_read::total 31360 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 490 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s)
358a366
> system.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses
359a368
> system.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses
360a370
> system.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses
361a372
> system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency
362a374
> system.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency
363a376
> system.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency
390a404
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses
391a406
> system.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses
392a408
> system.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses
393a410
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency
394a412
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency
395a414
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency
438a458
> system.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses
439a460
> system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
440a462
> system.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses
441a464
> system.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses
442a466
> system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency
443a468
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency
444a470
> system.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency
445a472
> system.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency
478a506
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses
479a508
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
480a510
> system.cpu.dcache.demand_mshr_miss_rate::total 0.064140 # mshr miss rate for demand accesses
481a512
> system.cpu.dcache.overall_mshr_miss_rate::total 0.064140 # mshr miss rate for overall accesses
482a514
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538 # average ReadReq mshr miss latency
483a516
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency
484a518
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency
485a520
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency
538a574
> system.cpu.l2cache.ReadReq_miss_rate::total 0.997613 # miss rate for ReadReq accesses
539a576
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
541a579
> system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses
543a582
> system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses
545a585
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703 # average ReadReq miss latency
546a587
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000 # average ReadExReq miss latency
548a590
> system.cpu.l2cache.demand_avg_miss_latency::total 34424.489796 # average overall miss latency
550a593
> system.cpu.l2cache.overall_avg_miss_latency::total 34424.489796 # average overall miss latency
582a626
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses
583a628
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
585a631
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses
587a634
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses
589a637
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency
590a639
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency
592a642
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency
594a645
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency