7,11c7,11
< host_inst_rate 139405 # Simulator instruction rate (inst/s)
< host_op_rate 139373 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 518883929 # Simulator tick rate (ticks/s)
< host_mem_usage 254032 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 4743 # Simulator instruction rate (inst/s)
> host_op_rate 4743 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 17659718 # Simulator tick rate (ticks/s)
> host_mem_usage 236044 # Number of bytes of host memory used
> host_seconds 1.35 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 8009750 # Total ticks spent queuing
< system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 8008750 # Total ticks spent queuing
> system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst
231c231
< system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ)
233c233
< system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ)
238c238
< system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank
243,244c243,244
< system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states
316c316
< system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss
326,328c326,328
< system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total)
330c330
< system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total)
342c342
< system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total)
345c345
< system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle
---
> system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle
355c355
< system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle
385,387c385,387
< system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle
389,390c389,390
< system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle
394c394
< system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle
401c401
< system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle
482c482
< system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads
533,535c533,535
< system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle
537c537
< system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle
549c549
< system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle
600c600
< system.cpu.rob.rob_reads 26790 # The number of ROB reads
---
> system.cpu.rob.rob_reads 26792 # The number of ROB reads
603c603
< system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling
756,761c756,761
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 35506500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 35506500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 35506500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 35506500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 35506500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 35506500 # number of overall miss cycles
774,779c774,779
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77525.109170 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77525.109170 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77525.109170 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77525.109170 # average overall miss latency
798,803c798,803
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26274500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 26274500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26274500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 26274500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26274500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 26274500 # number of overall MSHR miss cycles
810,815c810,815
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83944.089457 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83944.089457 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency
855,856c855,856
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25791500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 25791500 # number of ReadCleanReq miss cycles
859c859
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 25791500 # number of demand (read+write) miss cycles
861,862c861,862
< system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 41935500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 25791500 # number of overall miss cycles
864c864
< system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 41935500 # number of overall miss cycles
891,892c891,892
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency
895c895
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency
897,898c897,898
< system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency
900c900
< system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency
921,922c921,922
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles
925c925
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles
927,928c927,928
< system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles
930c930
< system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles
945,946c945,946
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency
949c949
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency
951,952c951,952
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency
954c954
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency
< host_inst_rate 139405 # Simulator instruction rate (inst/s)
< host_op_rate 139373 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 518883929 # Simulator tick rate (ticks/s)
< host_mem_usage 254032 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 4743 # Simulator instruction rate (inst/s)
> host_op_rate 4743 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 17659718 # Simulator tick rate (ticks/s)
> host_mem_usage 236044 # Number of bytes of host memory used
> host_seconds 1.35 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 8009750 # Total ticks spent queuing
< system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 8008750 # Total ticks spent queuing
> system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst
231c231
< system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ)
233c233
< system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ)
238c238
< system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank
243,244c243,244
< system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states
316c316
< system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss
326,328c326,328
< system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total)
330c330
< system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total)
342c342
< system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total)
345c345
< system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle
---
> system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle
355c355
< system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle
385,387c385,387
< system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle
389,390c389,390
< system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle
394c394
< system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle
401c401
< system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle
482c482
< system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads
533,535c533,535
< system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle
537c537
< system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle
549c549
< system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle
600c600
< system.cpu.rob.rob_reads 26790 # The number of ROB reads
---
> system.cpu.rob.rob_reads 26792 # The number of ROB reads
603c603
< system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling
756,761c756,761
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 35506500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 35506500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 35506500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 35506500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 35506500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 35506500 # number of overall miss cycles
774,779c774,779
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77525.109170 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77525.109170 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77525.109170 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77525.109170 # average overall miss latency
798,803c798,803
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26274500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 26274500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26274500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 26274500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26274500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 26274500 # number of overall MSHR miss cycles
810,815c810,815
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83944.089457 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83944.089457 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency
855,856c855,856
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25791500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 25791500 # number of ReadCleanReq miss cycles
859c859
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 25791500 # number of demand (read+write) miss cycles
861,862c861,862
< system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 41935500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 25791500 # number of overall miss cycles
864c864
< system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 41935500 # number of overall miss cycles
891,892c891,892
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency
895c895
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency
897,898c897,898
< system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency
900c900
< system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency
921,922c921,922
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles
925c925
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles
927,928c927,928
< system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles
930c930
< system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles
945,946c945,946
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency
949c949
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency
951,952c951,952
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency
954c954
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency