3,5c3,5
< sim_seconds 0.000022 # Number of seconds simulated
< sim_ticks 22248000 # Number of ticks simulated
< final_tick 22248000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000024 # Number of seconds simulated
> sim_ticks 23776000 # Number of ticks simulated
> final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 114507 # Simulator instruction rate (inst/s)
< host_op_rate 114481 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 398824007 # Simulator tick rate (ticks/s)
< host_mem_usage 254412 # Number of bytes of host memory used
< host_seconds 0.06 # Real time elapsed on the host
---
> host_inst_rate 93889 # Simulator instruction rate (inst/s)
> host_op_rate 93856 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 349385939 # Simulator tick rate (ticks/s)
> host_mem_usage 252568 # Number of bytes of host memory used
> host_seconds 0.07 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 897518878 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 497662711 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1395181589 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 897518878 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 897518878 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 897518878 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 497662711 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1395181589 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 22109000 # Total gap between requests
---
> system.physmem.totGap 23381000 # Total gap between requests
94,98c94,98
< system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
190,204c190,205
< system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 352.842105 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 230.159600 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 321.021248 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 19 25.00% 48.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9 11.84% 60.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 11 14.47% 75.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 6 7.89% 82.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1 1.32% 84.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 2.63% 86.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation
< system.physmem.totQLat 4498250 # Total ticks spent queuing
< system.physmem.totMemAccLat 13592000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation
> system.physmem.totQLat 8009750 # Total ticks spent queuing
> system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM
206c207
< system.physmem.avgQLat 9274.74 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst
208,209c209,210
< system.physmem.avgMemAccLat 28024.74 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1395.18 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s
211c212
< system.physmem.avgRdBWSys 1395.18 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s
214,215c215,216
< system.physmem.busUtil 10.90 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.20 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads
217c218
< system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing
219c220
< system.physmem.readRowHits 394 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 395 # Number of row buffer hits during reads
221c222
< system.physmem.readRowHitRate 81.24 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads
223,227c224,228
< system.physmem.avgGap 45585.57 # Average gap between requests
< system.physmem.pageHitRate 81.24 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1645800 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 48208.25 # Average gap between requests
> system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ)
229,241c230,247
< system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 13790805 # Total energy per rank (pJ)
< system.physmem_0.averagePower 871.044055 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ)
> system.physmem_0.averagePower 621.784975 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states
> system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ)
243,257c249,268
< system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 10074465 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 662250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 13465350 # Total energy per rank (pJ)
< system.physmem_1.averagePower 850.487920 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1034500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 14291750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 2853 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1680 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups
---
> system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ)
> system.physmem_1.averagePower 629.216130 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 2854 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups
260,263c271,274
< system.cpu.branchPred.BTBHitPct 32.394366 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 41 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups.
265c276
< system.cpu.branchPred.indirectMisses 436 # Number of indirect misses.
---
> system.cpu.branchPred.indirectMisses 437 # Number of indirect misses.
272c283
< system.cpu.dtb.read_hits 2261 # DTB read hits
---
> system.cpu.dtb.read_hits 2252 # DTB read hits
275,276c286,287
< system.cpu.dtb.read_accesses 2309 # DTB read accesses
< system.cpu.dtb.write_hits 1039 # DTB write hits
---
> system.cpu.dtb.read_accesses 2300 # DTB read accesses
> system.cpu.dtb.write_hits 1038 # DTB write hits
279,280c290,291
< system.cpu.dtb.write_accesses 1067 # DTB write accesses
< system.cpu.dtb.data_hits 3300 # DTB hits
---
> system.cpu.dtb.write_accesses 1066 # DTB write accesses
> system.cpu.dtb.data_hits 3290 # DTB hits
283,284c294,295
< system.cpu.dtb.data_accesses 3376 # DTB accesses
< system.cpu.itb.fetch_hits 2294 # ITB hits
---
> system.cpu.dtb.data_accesses 3366 # DTB accesses
> system.cpu.itb.fetch_hits 2295 # ITB hits
287c298
< system.cpu.itb.fetch_accesses 2321 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2322 # ITB accesses
301,302c312,313
< system.cpu.pwrStateResidencyTicks::ON 22248000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 44497 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 47553 # number of cpu cycles simulated
305,310c316,321
< system.cpu.fetch.icacheStallCycles 8475 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 16557 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2853 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 5121 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1044 # Number of cycles fetch has spent squashing
---
> system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing
313,317c324,328
< system.cpu.fetch.CacheLines 2294 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 14796 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.119019 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.502117 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total)
319,327c330,338
< system.cpu.fetch.rateDist::0 11808 79.81% 79.81% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 299 2.02% 81.83% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 232 1.57% 83.39% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 257 1.74% 85.13% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 292 1.97% 87.10% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 233 1.57% 88.68% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 283 1.91% 90.59% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 144 0.97% 91.57% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1248 8.43% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total)
331,338c342,349
< system.cpu.fetch.rateDist::total 14796 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.064117 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.372093 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 8328 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 3356 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2449 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 215 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 448 # Number of cycles decode is squashing
---
> system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing
341c352
< system.cpu.decode.DecodedInsts 15018 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode
343,349c354,360
< system.cpu.rename.SquashCycles 448 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 8488 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 1745 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 620 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2480 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 14460 # Number of instructions processed by rename
---
> system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2476 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename
353,356c364,367
< system.cpu.rename.SQFullEvents 949 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 10938 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 17913 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 17904 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups
359c370
< system.cpu.rename.UndoneMaps 6361 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing
363,364c374,375
< system.cpu.memDep0.insertedLoads 2839 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1293 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit.
367c378
< system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec)
369c380
< system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued
371,372c382,383
< system.cpu.iq.iqSquashedInstsExamined 6710 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3679 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph
374,376c385,387
< system.cpu.iq.issued_per_cycle::samples 14796 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.729048 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.467428 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle
378,386c389,397
< system.cpu.iq.issued_per_cycle::0 10757 72.70% 72.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1291 8.73% 81.43% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 918 6.20% 87.63% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 680 4.60% 92.23% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 521 3.52% 95.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 349 2.36% 98.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 197 1.33% 99.44% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 55 0.37% 99.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle
390c401
< system.cpu.iq.issued_per_cycle::total 14796 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle
392,422c403,433
< system.cpu.iq.fu_full::IntAlu 21 15.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 82 58.57% 73.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 37 26.43% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 37 26.24% 100.00% # attempts to use FU when none available
426,456c437,467
< system.cpu.iq.FU_type_0::IntAlu 7188 66.64% 66.65% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2482 23.01% 89.69% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1112 10.31% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2475 22.97% 89.69% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1111 10.31% 100.00% # Type of FU issued
459,465c470,476
< system.cpu.iq.FU_type_0::total 10787 # Type of FU issued
< system.cpu.iq.rate 0.242421 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 140 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.012979 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 36506 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 19817 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 9751 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 10776 # Type of FU issued
> system.cpu.iq.rate 0.226610 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 141 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses
469c480
< system.cpu.iq.int_alu_accesses 10914 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses
473c484
< system.cpu.iew.lsq.thread0.squashedLoads 1654 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed
476c487
< system.cpu.iew.lsq.thread0.squashedStores 428 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed
480c491
< system.cpu.iew.lsq.thread0.cacheBlocked 89 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked
482,485c493,496
< system.cpu.iew.iewSquashCycles 448 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 1381 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 302 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 13180 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ
487,488c498,499
< system.cpu.iew.iewDispLoadInsts 2839 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1293 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions
491c502
< system.cpu.iew.iewLSQFullEvents 295 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall
496,498c507,509
< system.cpu.iew.iewExecutedInsts 10303 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2309 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 484 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute
501,511c512,522
< system.cpu.iew.exec_refs 3386 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1643 # Number of branches executed
< system.cpu.iew.exec_stores 1077 # Number of stores executed
< system.cpu.iew.exec_rate 0.231544 # Inst execution rate
< system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 9761 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 5150 # num instructions producing a value
< system.cpu.iew.wb_consumers 7013 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.219363 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.734350 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 6727 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 3376 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1642 # Number of branches executed
> system.cpu.iew.exec_stores 1076 # Number of stores executed
> system.cpu.iew.exec_rate 0.216390 # Inst execution rate
> system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 9755 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 5155 # num instructions producing a value
> system.cpu.iew.wb_consumers 7025 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit
513,516c524,527
< system.cpu.commit.branchMispredicts 407 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 13560 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.472124 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.390428 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle
518,526c529,537
< system.cpu.commit.committed_per_cycle::0 11134 82.11% 82.11% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1157 8.53% 90.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 469 3.46% 94.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 205 1.51% 95.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 133 0.98% 96.59% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 85 0.63% 97.22% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 96 0.71% 97.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 89 0.66% 98.58% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 192 1.42% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle
530c541
< system.cpu.commit.committed_per_cycle::total 13560 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle
577,578c588,589
< system.cpu.rob.rob_reads 26146 # The number of ROB reads
< system.cpu.rob.rob_writes 27511 # The number of ROB writes
---
> system.cpu.rob.rob_reads 26790 # The number of ROB reads
> system.cpu.rob.rob_writes 27482 # The number of ROB writes
580c591
< system.cpu.idleCycles 29701 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling
583,588c594,599
< system.cpu.cpi 6.968990 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.968990 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.143493 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.143493 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 12938 # number of integer regfile reads
< system.cpu.int_regfile_writes 7444 # number of integer regfile writes
---
> system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 12923 # number of integer regfile reads
> system.cpu.int_regfile_writes 7437 # number of integer regfile writes
593c604
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
595,596c606,607
< system.cpu.dcache.tags.tagsinuse 109.756228 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2407 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks.
598c609
< system.cpu.dcache.tags.avg_refs 13.913295 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks.
600,602c611,613
< system.cpu.dcache.tags.occ_blocks::cpu.data 109.756228 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.026796 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.026796 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy
604,605c615,616
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
607,611c618,622
< system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits
614,617c625,628
< system.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits
< system.cpu.dcache.overall_hits::total 2407 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits
> system.cpu.dcache.overall_hits::total 2402 # number of overall hits
626,635c637,646
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12910000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12910000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 24562475 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 24562475 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 37472475 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 37472475 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 37472475 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 37472475 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 2079 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 2079 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses)
638,643c649,654
< system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086580 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.086580 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses
646,658c657,669
< system.cpu.dcache.demand_miss_rate::cpu.data 0.182405 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.182405 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.182405 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.182405 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71722.222222 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 71722.222222 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68802.450980 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68802.450980 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 69781.145251 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 69781.145251 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 2459 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked
660c671
< system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked
662c673
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.186047 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked
680,689c691,700
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8568000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8568000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6031500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6031500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14599500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 14599500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14599500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 14599500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048581 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048581 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9401500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9401500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7013500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7013500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16415000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 16415000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16415000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 16415000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048698 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048698 # mshr miss rate for ReadReq accesses
692,704c703,715
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.058764 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.058764 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84831.683168 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84831.683168 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83770.833333 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83770.833333 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.058864 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.058864 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
706,707c717,718
< system.cpu.icache.tags.tagsinuse 159.084059 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1838 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 160.538154 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1837 # Total number of references to valid blocks.
709c720
< system.cpu.icache.tags.avg_refs 5.872204 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 5.869010 # Average number of references to valid blocks.
711,713c722,724
< system.cpu.icache.tags.occ_blocks::cpu.inst 159.084059 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.077678 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.077678 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 160.538154 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078388 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078388 # Average percentage of cache occupancy
715,716c726,727
< system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id
718,757c729,768
< system.cpu.icache.tags.tag_accesses 4901 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4901 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1838 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1838 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1838 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1838 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1838 # number of overall hits
< system.cpu.icache.overall_hits::total 1838 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 456 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 456 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 456 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 456 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 456 # number of overall misses
< system.cpu.icache.overall_misses::total 456 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32999500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32999500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32999500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32999500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32999500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32999500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2294 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2294 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2294 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2294 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2294 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2294 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198779 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.198779 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.198779 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.198779 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.198779 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.198779 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72367.324561 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 72367.324561 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 72367.324561 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 72367.324561 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 4903 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4903 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1837 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1837 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1837 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1837 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits
> system.cpu.icache.overall_hits::total 1837 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses
> system.cpu.icache.overall_misses::total 458 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked
761c772
< system.cpu.icache.avg_blocked_cycles::no_mshrs 56 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked
763,768c774,779
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits
775,793c786,804
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24573000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24573000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24573000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24573000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24573000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24573000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136443 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.136443 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.136443 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78507.987220 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78507.987220 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
795c806
< system.cpu.l2cache.tags.tagsinuse 268.962928 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use
800,804c811,815
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.125052 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 109.837876 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004856 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.003352 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.008208 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 110.259003 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004900 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.008265 # Average percentage of cache occupancy
806,807c817,818
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
811c822
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
830,841c841,852
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5920500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5920500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24090000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 24090000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8408000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 8408000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 24090000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 14328500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 38418500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 24090000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 14328500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 38418500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles
866,877c877,888
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82229.166667 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82229.166667 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77211.538462 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77211.538462 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83247.524752 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83247.524752 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79213.402062 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79213.402062 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency
896,907c907,918
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20970000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20970000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7398000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7398000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20970000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12598500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 33568500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20970000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12598500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 33568500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles
920,931c931,942
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72229.166667 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72229.166667 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67211.538462 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67211.538462 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73247.524752 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73247.524752 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
938c949
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
964c975
< system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
---
> system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
966c977
< system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
968c979
< system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
975c986
< system.membus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
996,999c1007,1010
< system.membus.reqLayer0.occupancy 591500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2578750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 11.6 # Layer utilization (%)
---
> system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 10.8 # Layer utilization (%)