7,11c7,11
< host_inst_rate 43231 # Simulator instruction rate (inst/s)
< host_op_rate 43225 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 148545474 # Simulator tick rate (ticks/s)
< host_mem_usage 289772 # Number of bytes of host memory used
< host_seconds 0.15 # Real time elapsed on the host
---
> host_inst_rate 94413 # Simulator instruction rate (inst/s)
> host_op_rate 94393 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 324370159 # Simulator tick rate (ticks/s)
> host_mem_usage 297000 # Number of bytes of host memory used
> host_seconds 0.07 # Real time elapsed on the host
701c701
< system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use
706c706
< system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor
727,732c727,732
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32352500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32352500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32352500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32352500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32352500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32352500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles
745,750c745,750
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70484.749455 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 70484.749455 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 70484.749455 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 70484.749455 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency
771,776c771,776
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23859500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23859500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23859500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23859500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23859500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23859500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles
783,788c783,788
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76718.649518 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76718.649518 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency
929a930,935
> system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
943,944c949,950
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram
946,947c952,953
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram
950c956
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< host_inst_rate 43231 # Simulator instruction rate (inst/s)
< host_op_rate 43225 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 148545474 # Simulator tick rate (ticks/s)
< host_mem_usage 289772 # Number of bytes of host memory used
< host_seconds 0.15 # Real time elapsed on the host
---
> host_inst_rate 94413 # Simulator instruction rate (inst/s)
> host_op_rate 94393 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 324370159 # Simulator tick rate (ticks/s)
> host_mem_usage 297000 # Number of bytes of host memory used
> host_seconds 0.07 # Real time elapsed on the host
701c701
< system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use
706c706
< system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor
727,732c727,732
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32352500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32352500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32352500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32352500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32352500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32352500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles
745,750c745,750
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70484.749455 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 70484.749455 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 70484.749455 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 70484.749455 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency
771,776c771,776
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23859500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23859500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23859500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23859500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23859500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23859500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles
783,788c783,788
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76718.649518 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76718.649518 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency
929a930,935
> system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
943,944c949,950
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram
946,947c952,953
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram
950c956
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram