4,5c4,5
< sim_ticks 21078000 # Number of ticks simulated
< final_tick 21078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 21025000 # Number of ticks simulated
> final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 72140 # Simulator instruction rate (inst/s)
< host_op_rate 72127 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 238549554 # Simulator tick rate (ticks/s)
< host_mem_usage 265696 # Number of bytes of host memory used
---
> host_inst_rate 72274 # Simulator instruction rate (inst/s)
> host_op_rate 72262 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 238397605 # Simulator tick rate (ticks/s)
> host_mem_usage 265716 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 950374798 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 528323370 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1478698169 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 950374798 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 950374798 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 950374798 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 528323370 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1478698169 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 21045000 # Total gap between requests
---
> system.physmem.totGap 20992000 # Total gap between requests
93c93
< system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
95,96c95,96
< system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
189,202c189,204
< system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 328.393443 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 194.167058 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 347.898610 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21 34.43% 34.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 16 26.23% 60.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6 9.84% 70.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 4 6.56% 77.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.92% 81.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.64% 83.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10 16.39% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation
< system.physmem.totQLat 3243750 # Total ticks spent queuing
< system.physmem.totMemAccLat 13328750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 224.218426 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.360278 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 24.05% 50.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
> system.physmem.totQLat 4394750 # Total ticks spent queuing
> system.physmem.totMemAccLat 13544750 # Total ticks spent from burst creation until serviced by the DRAM
204,206c206
< system.physmem.totBankLat 7645000 # Total ticks spent accessing banks
< system.physmem.avgQLat 6647.03 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 15665.98 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 9005.64 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 27313.01 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1481.73 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27755.64 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1481.73 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 11.58 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.61 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads
217c217
< system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
223c223
< system.physmem.avgGap 43125.00 # Average gap between requests
---
> system.physmem.avgGap 43016.39 # Average gap between requests
225,226c225,230
< system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1478698169 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 22000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15304250 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1482425684 # Throughput (bytes/s)
237c241
< system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 618500 # Layer occupancy (ticks)
239,240c243,244
< system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 21.6 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 4556750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 21.7 # Layer utilization (%)
255c259
< system.cpu.dtb.read_hits 2078 # DTB read hits
---
> system.cpu.dtb.read_hits 2077 # DTB read hits
258c262
< system.cpu.dtb.read_accesses 2125 # DTB read accesses
---
> system.cpu.dtb.read_accesses 2124 # DTB read accesses
263c267
< system.cpu.dtb.data_hits 3140 # DTB hits
---
> system.cpu.dtb.data_hits 3139 # DTB hits
266,267c270,271
< system.cpu.dtb.data_accesses 3218 # DTB accesses
< system.cpu.itb.fetch_hits 2388 # ITB hits
---
> system.cpu.dtb.data_accesses 3217 # DTB accesses
> system.cpu.itb.fetch_hits 2387 # ITB hits
270c274
< system.cpu.itb.fetch_accesses 2427 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2426 # ITB accesses
284c288
< system.cpu.numCycles 42157 # number of cpu cycles simulated
---
> system.cpu.numCycles 42051 # number of cpu cycles simulated
287,288c291,292
< system.cpu.fetch.icacheStallCycles 8510 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 16605 # Number of instructions fetch has processed
---
> system.cpu.fetch.icacheStallCycles 8515 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 16590 # Number of instructions fetch has processed
291c295
< system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 2968 # Number of cycles fetch has run and was not squashing or blocked
293c297
< system.cpu.fetch.BlockedCycles 1405 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 1438 # Number of cycles fetch has spent blocked
296,300c300,304
< system.cpu.fetch.CacheLines 2388 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 14964 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.109663 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.506678 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 15000 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.106000 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.503194 # Number of instructions fetched each cycle (Total)
302,310c306,314
< system.cpu.fetch.rateDist::0 11994 80.15% 80.15% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 318 2.13% 82.28% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 234 1.56% 83.84% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 214 1.43% 85.27% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 255 1.70% 86.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 241 1.61% 88.59% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 264 1.76% 90.35% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 184 1.23% 91.58% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1260 8.42% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 12032 80.21% 80.21% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 318 2.12% 82.33% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 234 1.56% 83.89% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 214 1.43% 85.32% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 255 1.70% 87.02% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 241 1.61% 88.63% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 264 1.76% 90.39% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 183 1.22% 91.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1259 8.39% 100.00% # Number of instructions fetched each cycle (Total)
314,319c318,323
< system.cpu.fetch.rateDist::total 14964 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.068648 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.393885 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 9327 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 1567 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2770 # Number of cycles decode is running
---
> system.cpu.fetch.rateDist::total 15000 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.068821 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.394521 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 9332 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 1599 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2769 # Number of cycles decode is running
324c328
< system.cpu.decode.DecodedInsts 15343 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 15335 # Number of instructions handled by decode
327,332c331,336
< system.cpu.rename.IdleCycles 9537 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 678 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2628 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 341 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 14637 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 9542 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 708 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2627 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 344 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 14630 # Number of instructions processed by rename
335,338c339,342
< system.cpu.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 10979 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 18262 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 18253 # Number of integer rename lookups
---
> system.cpu.rename.LSQFullEvents 301 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 10973 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 18255 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 18246 # Number of integer rename lookups
341c345
< system.cpu.rename.UndoneMaps 6409 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 6403 # Number of HB maps that are undone due to squashing
344,345c348,349
< system.cpu.rename.skidInsts 843 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 874 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 2768 # Number of loads inserted to the mem dependence unit.
349c353
< system.cpu.iq.iqInstsAdded 12974 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 12973 # Number of instructions added to the IQ (excludes non-spec)
351c355
< system.cpu.iq.iqInstsIssued 10780 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 10779 # Number of instructions issued
353,354c357,358
< system.cpu.iq.iqSquashedInstsExamined 6201 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 6200 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3613 # Number of squashed operands that are examined and possibly removed from graph
356,358c360,362
< system.cpu.iq.issued_per_cycle::samples 14964 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.720396 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.363744 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15000 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.718600 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.361398 # Number of insts issued each cycle
360,366c364,370
< system.cpu.iq.issued_per_cycle::0 10463 69.92% 69.92% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1623 10.85% 80.77% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1158 7.74% 88.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 756 5.05% 93.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 501 3.35% 96.91% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 270 1.80% 98.71% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 146 0.98% 99.69% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10485 69.90% 69.90% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1646 10.97% 80.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1153 7.69% 88.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 753 5.02% 93.58% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 501 3.34% 96.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 269 1.79% 98.71% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle
372c376
< system.cpu.iq.issued_per_cycle::total 14964 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15000 # Number of insts issued each cycle
408c412
< system.cpu.iq.FU_type_0::IntAlu 7243 67.19% 67.21% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 7243 67.20% 67.21% # Type of FU issued
437c441
< system.cpu.iq.FU_type_0::MemRead 2399 22.25% 89.49% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 2398 22.25% 89.49% # Type of FU issued
441,442c445,446
< system.cpu.iq.FU_type_0::total 10780 # Type of FU issued
< system.cpu.iq.rate 0.255711 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 10779 # Type of FU issued
> system.cpu.iq.rate 0.256332 # Inst issue rate
444,446c448,450
< system.cpu.iq.fu_busy_rate 0.010390 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 36671 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 19208 # Number of integer instruction queue writes
---
> system.cpu.iq.fu_busy_rate 0.010391 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 36705 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 19206 # Number of integer instruction queue writes
451c455
< system.cpu.iq.int_alu_accesses 10879 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 10878 # Number of integer alu accesses
455c459
< system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1585 # Number of loads squashed
462c466
< system.cpu.iew.lsq.thread0.cacheBlocked 127 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 132 # Number of times an access to memory failed due to the cache being blocked
467c471
< system.cpu.iew.iewDispatchedInsts 13092 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 13091 # Number of instructions dispatched to IQ
469c473
< system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 2768 # Number of dispatched load instructions
478,479c482,483
< system.cpu.iew.iewExecutedInsts 10072 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
---
> system.cpu.iew.iewExecutedInsts 10071 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed
483c487
< system.cpu.iew.exec_refs 3231 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 3230 # number of memory reference insts executed
486c490
< system.cpu.iew.exec_rate 0.238916 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.239495 # Inst execution rate
489,490c493,494
< system.cpu.iew.wb_producers 5080 # num instructions producing a value
< system.cpu.iew.wb_consumers 6838 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 5069 # num instructions producing a value
> system.cpu.iew.wb_consumers 6811 # num instructions consuming a value
492,493c496,497
< system.cpu.iew.wb_rate 0.228005 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.742907 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.228580 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.744237 # average fanout of values written-back
495c499
< system.cpu.commit.commitSquashedInsts 6701 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 6700 # The number of squashed insts skipped by commit
498,500c502,504
< system.cpu.commit.committed_per_cycle::samples 13738 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.465060 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.277866 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 13774 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.463845 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.273398 # Number of insts commited each cycle
502,509c506,513
< system.cpu.commit.committed_per_cycle::0 10960 79.78% 79.78% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1479 10.77% 90.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 519 3.78% 94.32% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 236 1.72% 96.04% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 157 1.14% 97.18% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 106 0.77% 97.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 104 0.76% 98.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 34 0.25% 98.96% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 10981 79.72% 79.72% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1489 10.81% 90.53% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 532 3.86% 94.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 235 1.71% 96.10% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 155 1.13% 97.23% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 100 0.73% 97.95% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 106 0.77% 98.72% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 33 0.24% 98.96% # Number of insts commited each cycle
514c518
< system.cpu.commit.committed_per_cycle::total 13738 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 13774 # Number of insts commited each cycle
524a529,563
> system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
527,528c566,567
< system.cpu.rob.rob_reads 26334 # The number of ROB reads
< system.cpu.rob.rob_writes 27415 # The number of ROB writes
---
> system.cpu.rob.rob_reads 26369 # The number of ROB reads
> system.cpu.rob.rob_writes 27413 # The number of ROB writes
530c569
< system.cpu.idleCycles 27193 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 27051 # Total number of cycles that the CPU has spent unscheduled due to idling
534,538c573,577
< system.cpu.cpi 6.615976 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.615976 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.151149 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.151149 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 12785 # number of integer regfile reads
---
> system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 12784 # number of integer regfile reads
544c583
< system.cpu.toL2Bus.throughput 1481734510 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s)
559c598
< system.cpu.toL2Bus.respLayer0.occupancy 528000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks)
561c600
< system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 278250 # Layer occupancy (ticks)
564,565c603,604
< system.cpu.icache.tags.tagsinuse 159.411930 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1899 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 159.423717 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks.
567c606
< system.cpu.icache.tags.avg_refs 6.047771 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks.
569,571c608,610
< system.cpu.icache.tags.occ_blocks::cpu.inst 159.411930 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.077838 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.077838 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 159.423717 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.077844 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.077844 # Average percentage of cache occupancy
576,583c615,622
< system.cpu.icache.tags.tag_accesses 5090 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 5090 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1899 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1899 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1899 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1899 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1899 # number of overall hits
< system.cpu.icache.overall_hits::total 1899 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 5088 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 5088 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits
> system.cpu.icache.overall_hits::total 1898 # number of overall hits
590,613c629,652
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31431750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31431750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31431750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31431750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31431750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31431750 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2388 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2388 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2388 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2388 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2388 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2388 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204774 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.204774 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.204774 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.204774 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.204774 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.204774 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64277.607362 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 64277.607362 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 64277.607362 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 64277.607362 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31330250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31330250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31330250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31330250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31330250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31330250 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 64070.040900 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 64070.040900 # average overall miss latency
634,651c673,690
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22098000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22098000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22098000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22098000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22098000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22098000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131910 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.131910 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.131910 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70152.380952 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70152.380952 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22016000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22016000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22016000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22016000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22016000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22016000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency
654c693
< system.cpu.l2cache.tags.tagsinuse 219.244506 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 219.258059 # Cycle average of tags in use
659,661c698,700
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.494883 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 59.749622 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004867 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.507047 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 59.751013 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy
687,697c726,736
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21772000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7725500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 29497500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5467500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5467500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21772000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13193000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34965000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21772000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13193000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34965000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21690000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 29408000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21690000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13435750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 35125750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21690000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13435750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 35125750 # number of overall miss cycles
720,730c759,769
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69337.579618 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76490.099010 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.313253 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74897.260274 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74897.260274 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 71649.590164 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 71649.590164 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902 # average overall miss latency
750,760c789,799
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17823000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6485500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4573000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4573000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17823000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11058500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 28881500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17823000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11058500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 28881500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17737500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6477000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24214500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4818250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4818250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17737500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11295250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29032750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17737500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11295250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 29032750 # number of overall MSHR miss cycles
772,782c811,821
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56761.146497 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64212.871287 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58574.698795 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62643.835616 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62643.835616 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58348.192771 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66003.424658 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66003.424658 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency
785,786c824,825
< system.cpu.dcache.tags.tagsinuse 107.267771 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 107.231811 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2229 # Total number of references to valid blocks.
788c827
< system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 12.810345 # Average number of references to valid blocks.
790,792c829,831
< system.cpu.dcache.tags.occ_blocks::cpu.data 107.267771 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.026188 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.026188 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 107.231811 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.026180 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.026180 # Average percentage of cache occupancy
797,800c836,839
< system.cpu.dcache.tags.tag_accesses 5694 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5694 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits
803,806c842,845
< system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits
< system.cpu.dcache.overall_hits::total 2230 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 2229 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2229 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2229 # number of overall hits
> system.cpu.dcache.overall_hits::total 2229 # number of overall hits
815,824c854,863
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11467500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11467500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 23223733 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 23223733 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34691233 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34691233 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34691233 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34691233 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11460500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11460500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 25449978 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 25449978 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 36910478 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 36910478 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 36910478 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 36910478 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses)
827,832c866,871
< system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090237 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.090237 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090285 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.090285 # miss rate for ReadReq accesses
835,847c874,886
< system.cpu.dcache.demand_miss_rate::cpu.data 0.192029 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.192029 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.192029 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.192029 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 65455.156604 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 65455.156604 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 1533 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.192099 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.192099 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.192099 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.192099 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 69642.411321 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 69642.411321 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 1529 # number of cycles access was blocked
849c888
< system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
851c890
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.862069 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.970588 # average number of cycles each access was blocked
871,880c910,919
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7915000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7915000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5462500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5462500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13377500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13377500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13377500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13377500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7907500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7907500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5712750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5712750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13620250 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13620250 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13620250 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13620250 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053854 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053854 # mshr miss rate for ReadReq accesses
883,894c922,933
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.063043 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.063043 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency
< sim_ticks 21078000 # Number of ticks simulated
< final_tick 21078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 21025000 # Number of ticks simulated
> final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 72140 # Simulator instruction rate (inst/s)
< host_op_rate 72127 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 238549554 # Simulator tick rate (ticks/s)
< host_mem_usage 265696 # Number of bytes of host memory used
---
> host_inst_rate 72274 # Simulator instruction rate (inst/s)
> host_op_rate 72262 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 238397605 # Simulator tick rate (ticks/s)
> host_mem_usage 265716 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 950374798 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 528323370 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1478698169 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 950374798 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 950374798 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 950374798 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 528323370 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1478698169 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 21045000 # Total gap between requests
---
> system.physmem.totGap 20992000 # Total gap between requests
93c93
< system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
95,96c95,96
< system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
189,202c189,204
< system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 328.393443 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 194.167058 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 347.898610 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 21 34.43% 34.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 16 26.23% 60.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6 9.84% 70.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 4 6.56% 77.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.92% 81.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.64% 83.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10 16.39% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation
< system.physmem.totQLat 3243750 # Total ticks spent queuing
< system.physmem.totMemAccLat 13328750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 224.218426 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.360278 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 24.05% 50.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
> system.physmem.totQLat 4394750 # Total ticks spent queuing
> system.physmem.totMemAccLat 13544750 # Total ticks spent from burst creation until serviced by the DRAM
204,206c206
< system.physmem.totBankLat 7645000 # Total ticks spent accessing banks
< system.physmem.avgQLat 6647.03 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 15665.98 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 9005.64 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 27313.01 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1481.73 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 27755.64 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1481.73 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 11.58 # Data bus utilization in percentage
< system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 11.61 # Data bus utilization in percentage
> system.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads
217c217
< system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
223c223
< system.physmem.avgGap 43125.00 # Average gap between requests
---
> system.physmem.avgGap 43016.39 # Average gap between requests
225,226c225,230
< system.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1478698169 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 22000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15304250 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1482425684 # Throughput (bytes/s)
237c241
< system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 618500 # Layer occupancy (ticks)
239,240c243,244
< system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 21.6 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 4556750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 21.7 # Layer utilization (%)
255c259
< system.cpu.dtb.read_hits 2078 # DTB read hits
---
> system.cpu.dtb.read_hits 2077 # DTB read hits
258c262
< system.cpu.dtb.read_accesses 2125 # DTB read accesses
---
> system.cpu.dtb.read_accesses 2124 # DTB read accesses
263c267
< system.cpu.dtb.data_hits 3140 # DTB hits
---
> system.cpu.dtb.data_hits 3139 # DTB hits
266,267c270,271
< system.cpu.dtb.data_accesses 3218 # DTB accesses
< system.cpu.itb.fetch_hits 2388 # ITB hits
---
> system.cpu.dtb.data_accesses 3217 # DTB accesses
> system.cpu.itb.fetch_hits 2387 # ITB hits
270c274
< system.cpu.itb.fetch_accesses 2427 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2426 # ITB accesses
284c288
< system.cpu.numCycles 42157 # number of cpu cycles simulated
---
> system.cpu.numCycles 42051 # number of cpu cycles simulated
287,288c291,292
< system.cpu.fetch.icacheStallCycles 8510 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 16605 # Number of instructions fetch has processed
---
> system.cpu.fetch.icacheStallCycles 8515 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 16590 # Number of instructions fetch has processed
291c295
< system.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 2968 # Number of cycles fetch has run and was not squashing or blocked
293c297
< system.cpu.fetch.BlockedCycles 1405 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 1438 # Number of cycles fetch has spent blocked
296,300c300,304
< system.cpu.fetch.CacheLines 2388 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 14964 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.109663 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.506678 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 2387 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 384 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 15000 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.106000 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.503194 # Number of instructions fetched each cycle (Total)
302,310c306,314
< system.cpu.fetch.rateDist::0 11994 80.15% 80.15% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 318 2.13% 82.28% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 234 1.56% 83.84% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 214 1.43% 85.27% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 255 1.70% 86.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 241 1.61% 88.59% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 264 1.76% 90.35% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 184 1.23% 91.58% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1260 8.42% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 12032 80.21% 80.21% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 318 2.12% 82.33% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 234 1.56% 83.89% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 214 1.43% 85.32% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 255 1.70% 87.02% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 241 1.61% 88.63% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 264 1.76% 90.39% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 183 1.22% 91.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1259 8.39% 100.00% # Number of instructions fetched each cycle (Total)
314,319c318,323
< system.cpu.fetch.rateDist::total 14964 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.068648 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.393885 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 9327 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 1567 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2770 # Number of cycles decode is running
---
> system.cpu.fetch.rateDist::total 15000 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.068821 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.394521 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 9332 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 1599 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2769 # Number of cycles decode is running
324c328
< system.cpu.decode.DecodedInsts 15343 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 15335 # Number of instructions handled by decode
327,332c331,336
< system.cpu.rename.IdleCycles 9537 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 678 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2628 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 341 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 14637 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 9542 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 708 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2627 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 344 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 14630 # Number of instructions processed by rename
335,338c339,342
< system.cpu.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.RenamedOperands 10979 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 18262 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 18253 # Number of integer rename lookups
---
> system.cpu.rename.LSQFullEvents 301 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.RenamedOperands 10973 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 18255 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 18246 # Number of integer rename lookups
341c345
< system.cpu.rename.UndoneMaps 6409 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 6403 # Number of HB maps that are undone due to squashing
344,345c348,349
< system.cpu.rename.skidInsts 843 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 874 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 2768 # Number of loads inserted to the mem dependence unit.
349c353
< system.cpu.iq.iqInstsAdded 12974 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 12973 # Number of instructions added to the IQ (excludes non-spec)
351c355
< system.cpu.iq.iqInstsIssued 10780 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 10779 # Number of instructions issued
353,354c357,358
< system.cpu.iq.iqSquashedInstsExamined 6201 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 6200 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 3613 # Number of squashed operands that are examined and possibly removed from graph
356,358c360,362
< system.cpu.iq.issued_per_cycle::samples 14964 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.720396 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.363744 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15000 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.718600 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.361398 # Number of insts issued each cycle
360,366c364,370
< system.cpu.iq.issued_per_cycle::0 10463 69.92% 69.92% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1623 10.85% 80.77% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1158 7.74% 88.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 756 5.05% 93.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 501 3.35% 96.91% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 270 1.80% 98.71% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 146 0.98% 99.69% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10485 69.90% 69.90% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1646 10.97% 80.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1153 7.69% 88.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 753 5.02% 93.58% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 501 3.34% 96.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 269 1.79% 98.71% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle
372c376
< system.cpu.iq.issued_per_cycle::total 14964 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15000 # Number of insts issued each cycle
408c412
< system.cpu.iq.FU_type_0::IntAlu 7243 67.19% 67.21% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 7243 67.20% 67.21% # Type of FU issued
437c441
< system.cpu.iq.FU_type_0::MemRead 2399 22.25% 89.49% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 2398 22.25% 89.49% # Type of FU issued
441,442c445,446
< system.cpu.iq.FU_type_0::total 10780 # Type of FU issued
< system.cpu.iq.rate 0.255711 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 10779 # Type of FU issued
> system.cpu.iq.rate 0.256332 # Inst issue rate
444,446c448,450
< system.cpu.iq.fu_busy_rate 0.010390 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 36671 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 19208 # Number of integer instruction queue writes
---
> system.cpu.iq.fu_busy_rate 0.010391 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 36705 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 19206 # Number of integer instruction queue writes
451c455
< system.cpu.iq.int_alu_accesses 10879 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 10878 # Number of integer alu accesses
455c459
< system.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1585 # Number of loads squashed
462c466
< system.cpu.iew.lsq.thread0.cacheBlocked 127 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 132 # Number of times an access to memory failed due to the cache being blocked
467c471
< system.cpu.iew.iewDispatchedInsts 13092 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 13091 # Number of instructions dispatched to IQ
469c473
< system.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions
---
> system.cpu.iew.iewDispLoadInsts 2768 # Number of dispatched load instructions
478,479c482,483
< system.cpu.iew.iewExecutedInsts 10072 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
---
> system.cpu.iew.iewExecutedInsts 10071 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed
483c487
< system.cpu.iew.exec_refs 3231 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 3230 # number of memory reference insts executed
486c490
< system.cpu.iew.exec_rate 0.238916 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.239495 # Inst execution rate
489,490c493,494
< system.cpu.iew.wb_producers 5080 # num instructions producing a value
< system.cpu.iew.wb_consumers 6838 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 5069 # num instructions producing a value
> system.cpu.iew.wb_consumers 6811 # num instructions consuming a value
492,493c496,497
< system.cpu.iew.wb_rate 0.228005 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.742907 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.228580 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.744237 # average fanout of values written-back
495c499
< system.cpu.commit.commitSquashedInsts 6701 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 6700 # The number of squashed insts skipped by commit
498,500c502,504
< system.cpu.commit.committed_per_cycle::samples 13738 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.465060 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.277866 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 13774 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.463845 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.273398 # Number of insts commited each cycle
502,509c506,513
< system.cpu.commit.committed_per_cycle::0 10960 79.78% 79.78% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1479 10.77% 90.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 519 3.78% 94.32% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 236 1.72% 96.04% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 157 1.14% 97.18% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 106 0.77% 97.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 104 0.76% 98.71% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 34 0.25% 98.96% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 10981 79.72% 79.72% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1489 10.81% 90.53% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 532 3.86% 94.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 235 1.71% 96.10% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 155 1.13% 97.23% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 100 0.73% 97.95% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 106 0.77% 98.72% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 33 0.24% 98.96% # Number of insts commited each cycle
514c518
< system.cpu.commit.committed_per_cycle::total 13738 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 13774 # Number of insts commited each cycle
524a529,563
> system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
527,528c566,567
< system.cpu.rob.rob_reads 26334 # The number of ROB reads
< system.cpu.rob.rob_writes 27415 # The number of ROB writes
---
> system.cpu.rob.rob_reads 26369 # The number of ROB reads
> system.cpu.rob.rob_writes 27413 # The number of ROB writes
530c569
< system.cpu.idleCycles 27193 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 27051 # Total number of cycles that the CPU has spent unscheduled due to idling
534,538c573,577
< system.cpu.cpi 6.615976 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 6.615976 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.151149 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.151149 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 12785 # number of integer regfile reads
---
> system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 12784 # number of integer regfile reads
544c583
< system.cpu.toL2Bus.throughput 1481734510 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s)
559c598
< system.cpu.toL2Bus.respLayer0.occupancy 528000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks)
561c600
< system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 278250 # Layer occupancy (ticks)
564,565c603,604
< system.cpu.icache.tags.tagsinuse 159.411930 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1899 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 159.423717 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks.
567c606
< system.cpu.icache.tags.avg_refs 6.047771 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks.
569,571c608,610
< system.cpu.icache.tags.occ_blocks::cpu.inst 159.411930 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.077838 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.077838 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 159.423717 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.077844 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.077844 # Average percentage of cache occupancy
576,583c615,622
< system.cpu.icache.tags.tag_accesses 5090 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 5090 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1899 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1899 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1899 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1899 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1899 # number of overall hits
< system.cpu.icache.overall_hits::total 1899 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 5088 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 5088 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits
> system.cpu.icache.overall_hits::total 1898 # number of overall hits
590,613c629,652
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31431750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31431750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31431750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31431750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31431750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31431750 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2388 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2388 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2388 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2388 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2388 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2388 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204774 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.204774 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.204774 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.204774 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.204774 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.204774 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64277.607362 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 64277.607362 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 64277.607362 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 64277.607362 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 64277.607362 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31330250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31330250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31330250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31330250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31330250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31330250 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64070.040900 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 64070.040900 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 64070.040900 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 64070.040900 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 64070.040900 # average overall miss latency
634,651c673,690
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22098000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22098000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22098000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22098000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22098000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22098000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131910 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.131910 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131910 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.131910 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70152.380952 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70152.380952 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70152.380952 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 70152.380952 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22016000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22016000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22016000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22016000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22016000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22016000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69892.063492 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69892.063492 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69892.063492 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 69892.063492 # average overall mshr miss latency
654c693
< system.cpu.l2cache.tags.tagsinuse 219.244506 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 219.258059 # Cycle average of tags in use
659,661c698,700
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.494883 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 59.749622 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004867 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.507047 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 59.751013 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy
687,697c726,736
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21772000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7725500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 29497500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5467500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5467500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21772000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 13193000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34965000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21772000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 13193000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34965000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21690000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 29408000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21690000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 13435750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 35125750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21690000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 13435750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 35125750 # number of overall miss cycles
720,730c759,769
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69337.579618 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76490.099010 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.313253 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74897.260274 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74897.260274 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 71649.590164 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69337.579618 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75821.839080 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 71649.590164 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69076.433121 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76415.841584 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 70862.650602 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78325.342466 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78325.342466 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 71978.995902 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69076.433121 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77216.954023 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 71978.995902 # average overall miss latency
750,760c789,799
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17823000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6485500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4573000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4573000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17823000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11058500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 28881500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17823000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11058500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 28881500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17737500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6477000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24214500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4818250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4818250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17737500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11295250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29032750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17737500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11295250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 29032750 # number of overall MSHR miss cycles
772,782c811,821
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56761.146497 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64212.871287 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58574.698795 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62643.835616 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62643.835616 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56761.146497 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63554.597701 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59183.401639 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56488.853503 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64128.712871 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58348.192771 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66003.424658 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66003.424658 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56488.853503 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64915.229885 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59493.340164 # average overall mshr miss latency
785,786c824,825
< system.cpu.dcache.tags.tagsinuse 107.267771 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 107.231811 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2229 # Total number of references to valid blocks.
788c827
< system.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 12.810345 # Average number of references to valid blocks.
790,792c829,831
< system.cpu.dcache.tags.occ_blocks::cpu.data 107.267771 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.026188 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.026188 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 107.231811 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.026180 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.026180 # Average percentage of cache occupancy
797,800c836,839
< system.cpu.dcache.tags.tag_accesses 5694 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5694 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 5692 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5692 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits
803,806c842,845
< system.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits
< system.cpu.dcache.overall_hits::total 2230 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 2229 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2229 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2229 # number of overall hits
> system.cpu.dcache.overall_hits::total 2229 # number of overall hits
815,824c854,863
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11467500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11467500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 23223733 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 23223733 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34691233 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34691233 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34691233 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34691233 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11460500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11460500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 25449978 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 25449978 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 36910478 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 36910478 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 36910478 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 36910478 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses)
827,832c866,871
< system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090237 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.090237 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090285 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.090285 # miss rate for ReadReq accesses
835,847c874,886
< system.cpu.dcache.demand_miss_rate::cpu.data 0.192029 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.192029 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.192029 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.192029 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 65455.156604 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 65455.156604 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 1533 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.192099 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.192099 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.192099 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.192099 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67020.467836 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 67020.467836 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70891.303621 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 70891.303621 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 69642.411321 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 69642.411321 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 69642.411321 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 1529 # number of cycles access was blocked
849c888
< system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
851c890
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.862069 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.970588 # average number of cycles each access was blocked
871,880c910,919
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7915000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7915000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5462500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5462500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13377500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13377500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13377500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13377500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7907500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7907500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5712750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5712750 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13620250 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13620250 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13620250 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13620250 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053854 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053854 # mshr miss rate for ReadReq accesses
883,894c922,933
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.063043 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063043 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.063043 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77524.509804 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77524.509804 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79343.750000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78277.298851 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 78277.298851 # average overall mshr miss latency