1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000012 # Number of seconds simulated
4sim_ticks 12450500 # Number of ticks simulated
5final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 42940 # Simulator instruction rate (inst/s)
8host_op_rate 42933 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 83690683 # Simulator tick rate (ticks/s)
10host_mem_usage 215012 # Number of bytes of host memory used
11host_seconds 0.15 # Real time elapsed on the host
12sim_insts 6386 # Number of instructions simulated
13sim_ops 6386 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 31360 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 490 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.fetch_hits 0 # ITB hits
24system.cpu.dtb.fetch_misses 0 # ITB misses
25system.cpu.dtb.fetch_acv 0 # ITB acv
26system.cpu.dtb.fetch_accesses 0 # ITB accesses
27system.cpu.dtb.read_hits 1943 # DTB read hits
28system.cpu.dtb.read_misses 53 # DTB read misses
29system.cpu.dtb.read_acv 0 # DTB read access violations
30system.cpu.dtb.read_accesses 1996 # DTB read accesses
--- 320 unchanged lines hidden (view full) ---
351system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles
352system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses)
353system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses)
354system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses
355system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses
356system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses
357system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses
358system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses
359system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses
360system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses
361system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency
362system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency
363system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency
364system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
365system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
366system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
367system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
368system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
369system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
370system.cpu.icache.fast_writes 0 # number of fast writes performed
371system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
383system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses
384system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles
385system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles
386system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles
387system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles
388system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles
389system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles
390system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses
391system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses
392system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses
393system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency
394system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency
395system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency
396system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
397system.cpu.dcache.replacements 0 # number of replacements
398system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use
399system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks.
400system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks.
401system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks.
402system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
403system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
431system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses)
432system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
433system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
434system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses
435system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses
436system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses
437system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses
438system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses
439system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
440system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses
441system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses
442system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency
443system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency
444system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency
445system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency
446system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
447system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
448system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
449system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
450system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
451system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
452system.cpu.dcache.fast_writes 0 # number of fast writes performed
453system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 17 unchanged lines hidden (view full) ---
471system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles
472system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles
473system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles
474system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles
475system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles
476system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles
477system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles
478system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses
479system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
480system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses
481system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses
482system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency
483system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency
484system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency
485system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency
486system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
487system.cpu.l2cache.replacements 0 # number of replacements
488system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use
489system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
490system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks.
491system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks.
492system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
493system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor
--- 37 unchanged lines hidden (view full) ---
531system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses
532system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses
533system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses
534system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses
535system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses
536system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses
537system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses
538system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
539system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
540system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses
541system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
542system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses
543system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
544system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency
545system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency
546system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency
547system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency
548system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency
549system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency
550system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency
551system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
552system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
553system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
554system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
555system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
556system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
557system.cpu.l2cache.fast_writes 0 # number of fast writes performed
558system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 16 unchanged lines hidden (view full) ---
575system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles
576system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles
577system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles
578system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles
579system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles
580system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles
581system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses
582system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
583system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
584system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses
585system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
586system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses
587system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency
589system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency
595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
596
597---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000012 # Number of seconds simulated
4sim_ticks 12450500 # Number of ticks simulated
5final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 42940 # Simulator instruction rate (inst/s)
8host_op_rate 42933 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 83690683 # Simulator tick rate (ticks/s)
10host_mem_usage 215012 # Number of bytes of host memory used
11host_seconds 0.15 # Real time elapsed on the host
12sim_insts 6386 # Number of instructions simulated
13sim_ops 6386 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 31360 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 490 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.fetch_hits 0 # ITB hits
24system.cpu.dtb.fetch_misses 0 # ITB misses
25system.cpu.dtb.fetch_acv 0 # ITB acv
26system.cpu.dtb.fetch_accesses 0 # ITB accesses
27system.cpu.dtb.read_hits 1943 # DTB read hits
28system.cpu.dtb.read_misses 53 # DTB read misses
29system.cpu.dtb.read_acv 0 # DTB read access violations
30system.cpu.dtb.read_accesses 1996 # DTB read accesses
--- 320 unchanged lines hidden (view full) ---
351system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles
352system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses)
353system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses)
354system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses
355system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses
356system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses
357system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses
358system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses
359system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses
360system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses
361system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency
362system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency
363system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency
364system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
365system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
366system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
367system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
368system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
369system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
370system.cpu.icache.fast_writes 0 # number of fast writes performed
371system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
383system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses
384system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles
385system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles
386system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles
387system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles
388system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles
389system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles
390system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses
391system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses
392system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses
393system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency
394system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency
395system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency
396system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
397system.cpu.dcache.replacements 0 # number of replacements
398system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use
399system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks.
400system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks.
401system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks.
402system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
403system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
431system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses)
432system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
433system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
434system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses
435system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses
436system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses
437system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses
438system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses
439system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
440system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses
441system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses
442system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency
443system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency
444system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency
445system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency
446system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
447system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
448system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
449system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
450system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
451system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
452system.cpu.dcache.fast_writes 0 # number of fast writes performed
453system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 17 unchanged lines hidden (view full) ---
471system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles
472system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles
473system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles
474system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles
475system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles
476system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles
477system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles
478system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses
479system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
480system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses
481system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses
482system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency
483system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency
484system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency
485system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency
486system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
487system.cpu.l2cache.replacements 0 # number of replacements
488system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use
489system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
490system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks.
491system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks.
492system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
493system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor
--- 37 unchanged lines hidden (view full) ---
531system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses
532system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses
533system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses
534system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses
535system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses
536system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses
537system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses
538system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
539system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
540system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses
541system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
542system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses
543system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
544system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency
545system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency
546system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency
547system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency
548system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency
549system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency
550system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency
551system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
552system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
553system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
554system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
555system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
556system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
557system.cpu.l2cache.fast_writes 0 # number of fast writes performed
558system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 16 unchanged lines hidden (view full) ---
575system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles
576system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles
577system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles
578system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles
579system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles
580system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles
581system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses
582system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
583system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
584system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses
585system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
586system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses
587system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency
589system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency
595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
596
597---------- End Simulation Statistics ----------