| config.ini (9924:31ef410b6843) | config.ini (9988:0b2e590c85be) |
|---|---|
| 1[root] 2type=Root 3children=system | 1[root] 2type=Root 3children=system |
| 4eventq_index=0 |
|
| 4full_system=false | 5full_system=false |
| 6sim_quantum=0 |
|
| 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain | 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17eventq_index=0 |
|
| 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= --- 5 unchanged lines hidden (view full) --- 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 | 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= --- 5 unchanged lines hidden (view full) --- 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 |
| 39eventq_index=0 |
|
| 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb | 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb |
| 71eventq_index=0 72fetchBufferSize=64 |
|
| 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 123 124[system.cpu.branchPred] 125type=BranchPredictor 126BTBEntries=4096 127BTBTagSize=16 128RASSize=16 129choiceCtrBits=2 130choicePredictorSize=8192 | 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 129 130[system.cpu.branchPred] 131type=BranchPredictor 132BTBEntries=4096 133BTBTagSize=16 134RASSize=16 135choiceCtrBits=2 136choicePredictorSize=8192 |
| 137eventq_index=0 |
|
| 131globalCtrBits=2 132globalPredictorSize=8192 133instShiftAmt=2 134localCtrBits=2 135localHistoryTableSize=2048 136localPredictorSize=2048 137numThreads=1 138predType=tournament 139 140[system.cpu.dcache] 141type=BaseCache 142children=tags 143addr_ranges=0:18446744073709551615 144assoc=2 145clk_domain=system.cpu_clk_domain | 138globalCtrBits=2 139globalPredictorSize=8192 140instShiftAmt=2 141localCtrBits=2 142localHistoryTableSize=2048 143localPredictorSize=2048 144numThreads=1 145predType=tournament 146 147[system.cpu.dcache] 148type=BaseCache 149children=tags 150addr_ranges=0:18446744073709551615 151assoc=2 152clk_domain=system.cpu_clk_domain |
| 153eventq_index=0 |
|
| 146forward_snoops=true 147hit_latency=2 148is_top_level=true 149max_miss_count=0 150mshrs=4 151prefetch_on_access=false 152prefetcher=Null 153response_latency=2 --- 6 unchanged lines hidden (view full) --- 160cpu_side=system.cpu.dcache_port 161mem_side=system.cpu.toL2Bus.slave[1] 162 163[system.cpu.dcache.tags] 164type=LRU 165assoc=2 166block_size=64 167clk_domain=system.cpu_clk_domain | 154forward_snoops=true 155hit_latency=2 156is_top_level=true 157max_miss_count=0 158mshrs=4 159prefetch_on_access=false 160prefetcher=Null 161response_latency=2 --- 6 unchanged lines hidden (view full) --- 168cpu_side=system.cpu.dcache_port 169mem_side=system.cpu.toL2Bus.slave[1] 170 171[system.cpu.dcache.tags] 172type=LRU 173assoc=2 174block_size=64 175clk_domain=system.cpu_clk_domain |
| 176eventq_index=0 |
|
| 168hit_latency=2 169size=262144 170 171[system.cpu.dtb] 172type=AlphaTLB | 177hit_latency=2 178size=262144 179 180[system.cpu.dtb] 181type=AlphaTLB |
| 182eventq_index=0 |
|
| 173size=64 174 175[system.cpu.fuPool] 176type=FUPool 177children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 178FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 | 183size=64 184 185[system.cpu.fuPool] 186type=FUPool 187children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 188FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 |
| 189eventq_index=0 |
|
| 179 180[system.cpu.fuPool.FUList0] 181type=FUDesc 182children=opList 183count=6 | 190 191[system.cpu.fuPool.FUList0] 192type=FUDesc 193children=opList 194count=6 |
| 195eventq_index=0 |
|
| 184opList=system.cpu.fuPool.FUList0.opList 185 186[system.cpu.fuPool.FUList0.opList] 187type=OpDesc | 196opList=system.cpu.fuPool.FUList0.opList 197 198[system.cpu.fuPool.FUList0.opList] 199type=OpDesc |
| 200eventq_index=0 |
|
| 188issueLat=1 189opClass=IntAlu 190opLat=1 191 192[system.cpu.fuPool.FUList1] 193type=FUDesc 194children=opList0 opList1 195count=2 | 201issueLat=1 202opClass=IntAlu 203opLat=1 204 205[system.cpu.fuPool.FUList1] 206type=FUDesc 207children=opList0 opList1 208count=2 |
| 209eventq_index=0 |
|
| 196opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 197 198[system.cpu.fuPool.FUList1.opList0] 199type=OpDesc | 210opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 211 212[system.cpu.fuPool.FUList1.opList0] 213type=OpDesc |
| 214eventq_index=0 |
|
| 200issueLat=1 201opClass=IntMult 202opLat=3 203 204[system.cpu.fuPool.FUList1.opList1] 205type=OpDesc | 215issueLat=1 216opClass=IntMult 217opLat=3 218 219[system.cpu.fuPool.FUList1.opList1] 220type=OpDesc |
| 221eventq_index=0 |
|
| 206issueLat=19 207opClass=IntDiv 208opLat=20 209 210[system.cpu.fuPool.FUList2] 211type=FUDesc 212children=opList0 opList1 opList2 213count=4 | 222issueLat=19 223opClass=IntDiv 224opLat=20 225 226[system.cpu.fuPool.FUList2] 227type=FUDesc 228children=opList0 opList1 opList2 229count=4 |
| 230eventq_index=0 |
|
| 214opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 215 216[system.cpu.fuPool.FUList2.opList0] 217type=OpDesc | 231opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 232 233[system.cpu.fuPool.FUList2.opList0] 234type=OpDesc |
| 235eventq_index=0 |
|
| 218issueLat=1 219opClass=FloatAdd 220opLat=2 221 222[system.cpu.fuPool.FUList2.opList1] 223type=OpDesc | 236issueLat=1 237opClass=FloatAdd 238opLat=2 239 240[system.cpu.fuPool.FUList2.opList1] 241type=OpDesc |
| 242eventq_index=0 |
|
| 224issueLat=1 225opClass=FloatCmp 226opLat=2 227 228[system.cpu.fuPool.FUList2.opList2] 229type=OpDesc | 243issueLat=1 244opClass=FloatCmp 245opLat=2 246 247[system.cpu.fuPool.FUList2.opList2] 248type=OpDesc |
| 249eventq_index=0 |
|
| 230issueLat=1 231opClass=FloatCvt 232opLat=2 233 234[system.cpu.fuPool.FUList3] 235type=FUDesc 236children=opList0 opList1 opList2 237count=2 | 250issueLat=1 251opClass=FloatCvt 252opLat=2 253 254[system.cpu.fuPool.FUList3] 255type=FUDesc 256children=opList0 opList1 opList2 257count=2 |
| 258eventq_index=0 |
|
| 238opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 239 240[system.cpu.fuPool.FUList3.opList0] 241type=OpDesc | 259opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 260 261[system.cpu.fuPool.FUList3.opList0] 262type=OpDesc |
| 263eventq_index=0 |
|
| 242issueLat=1 243opClass=FloatMult 244opLat=4 245 246[system.cpu.fuPool.FUList3.opList1] 247type=OpDesc | 264issueLat=1 265opClass=FloatMult 266opLat=4 267 268[system.cpu.fuPool.FUList3.opList1] 269type=OpDesc |
| 270eventq_index=0 |
|
| 248issueLat=12 249opClass=FloatDiv 250opLat=12 251 252[system.cpu.fuPool.FUList3.opList2] 253type=OpDesc | 271issueLat=12 272opClass=FloatDiv 273opLat=12 274 275[system.cpu.fuPool.FUList3.opList2] 276type=OpDesc |
| 277eventq_index=0 |
|
| 254issueLat=24 255opClass=FloatSqrt 256opLat=24 257 258[system.cpu.fuPool.FUList4] 259type=FUDesc 260children=opList 261count=0 | 278issueLat=24 279opClass=FloatSqrt 280opLat=24 281 282[system.cpu.fuPool.FUList4] 283type=FUDesc 284children=opList 285count=0 |
| 286eventq_index=0 |
|
| 262opList=system.cpu.fuPool.FUList4.opList 263 264[system.cpu.fuPool.FUList4.opList] 265type=OpDesc | 287opList=system.cpu.fuPool.FUList4.opList 288 289[system.cpu.fuPool.FUList4.opList] 290type=OpDesc |
| 291eventq_index=0 |
|
| 266issueLat=1 267opClass=MemRead 268opLat=1 269 270[system.cpu.fuPool.FUList5] 271type=FUDesc 272children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 273count=4 | 292issueLat=1 293opClass=MemRead 294opLat=1 295 296[system.cpu.fuPool.FUList5] 297type=FUDesc 298children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 299count=4 |
| 300eventq_index=0 |
|
| 274opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 275 276[system.cpu.fuPool.FUList5.opList00] 277type=OpDesc | 301opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 302 303[system.cpu.fuPool.FUList5.opList00] 304type=OpDesc |
| 305eventq_index=0 |
|
| 278issueLat=1 279opClass=SimdAdd 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList01] 283type=OpDesc | 306issueLat=1 307opClass=SimdAdd 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList01] 311type=OpDesc |
| 312eventq_index=0 |
|
| 284issueLat=1 285opClass=SimdAddAcc 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList02] 289type=OpDesc | 313issueLat=1 314opClass=SimdAddAcc 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList02] 318type=OpDesc |
| 319eventq_index=0 |
|
| 290issueLat=1 291opClass=SimdAlu 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList03] 295type=OpDesc | 320issueLat=1 321opClass=SimdAlu 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList03] 325type=OpDesc |
| 326eventq_index=0 |
|
| 296issueLat=1 297opClass=SimdCmp 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList04] 301type=OpDesc | 327issueLat=1 328opClass=SimdCmp 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList04] 332type=OpDesc |
| 333eventq_index=0 |
|
| 302issueLat=1 303opClass=SimdCvt 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList05] 307type=OpDesc | 334issueLat=1 335opClass=SimdCvt 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList05] 339type=OpDesc |
| 340eventq_index=0 |
|
| 308issueLat=1 309opClass=SimdMisc 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList06] 313type=OpDesc | 341issueLat=1 342opClass=SimdMisc 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList06] 346type=OpDesc |
| 347eventq_index=0 |
|
| 314issueLat=1 315opClass=SimdMult 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList07] 319type=OpDesc | 348issueLat=1 349opClass=SimdMult 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList07] 353type=OpDesc |
| 354eventq_index=0 |
|
| 320issueLat=1 321opClass=SimdMultAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList08] 325type=OpDesc | 355issueLat=1 356opClass=SimdMultAcc 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList08] 360type=OpDesc |
| 361eventq_index=0 |
|
| 326issueLat=1 327opClass=SimdShift 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList09] 331type=OpDesc | 362issueLat=1 363opClass=SimdShift 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList09] 367type=OpDesc |
| 368eventq_index=0 |
|
| 332issueLat=1 333opClass=SimdShiftAcc 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList10] 337type=OpDesc | 369issueLat=1 370opClass=SimdShiftAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList10] 374type=OpDesc |
| 375eventq_index=0 |
|
| 338issueLat=1 339opClass=SimdSqrt 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList11] 343type=OpDesc | 376issueLat=1 377opClass=SimdSqrt 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList11] 381type=OpDesc |
| 382eventq_index=0 |
|
| 344issueLat=1 345opClass=SimdFloatAdd 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList12] 349type=OpDesc | 383issueLat=1 384opClass=SimdFloatAdd 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList12] 388type=OpDesc |
| 389eventq_index=0 |
|
| 350issueLat=1 351opClass=SimdFloatAlu 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList13] 355type=OpDesc | 390issueLat=1 391opClass=SimdFloatAlu 392opLat=1 393 394[system.cpu.fuPool.FUList5.opList13] 395type=OpDesc |
| 396eventq_index=0 |
|
| 356issueLat=1 357opClass=SimdFloatCmp 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList14] 361type=OpDesc | 397issueLat=1 398opClass=SimdFloatCmp 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList14] 402type=OpDesc |
| 403eventq_index=0 |
|
| 362issueLat=1 363opClass=SimdFloatCvt 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList15] 367type=OpDesc | 404issueLat=1 405opClass=SimdFloatCvt 406opLat=1 407 408[system.cpu.fuPool.FUList5.opList15] 409type=OpDesc |
| 410eventq_index=0 |
|
| 368issueLat=1 369opClass=SimdFloatDiv 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList16] 373type=OpDesc | 411issueLat=1 412opClass=SimdFloatDiv 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList16] 416type=OpDesc |
| 417eventq_index=0 |
|
| 374issueLat=1 375opClass=SimdFloatMisc 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList17] 379type=OpDesc | 418issueLat=1 419opClass=SimdFloatMisc 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList17] 423type=OpDesc |
| 424eventq_index=0 |
|
| 380issueLat=1 381opClass=SimdFloatMult 382opLat=1 383 384[system.cpu.fuPool.FUList5.opList18] 385type=OpDesc | 425issueLat=1 426opClass=SimdFloatMult 427opLat=1 428 429[system.cpu.fuPool.FUList5.opList18] 430type=OpDesc |
| 431eventq_index=0 |
|
| 386issueLat=1 387opClass=SimdFloatMultAcc 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList19] 391type=OpDesc | 432issueLat=1 433opClass=SimdFloatMultAcc 434opLat=1 435 436[system.cpu.fuPool.FUList5.opList19] 437type=OpDesc |
| 438eventq_index=0 |
|
| 392issueLat=1 393opClass=SimdFloatSqrt 394opLat=1 395 396[system.cpu.fuPool.FUList6] 397type=FUDesc 398children=opList 399count=0 | 439issueLat=1 440opClass=SimdFloatSqrt 441opLat=1 442 443[system.cpu.fuPool.FUList6] 444type=FUDesc 445children=opList 446count=0 |
| 447eventq_index=0 |
|
| 400opList=system.cpu.fuPool.FUList6.opList 401 402[system.cpu.fuPool.FUList6.opList] 403type=OpDesc | 448opList=system.cpu.fuPool.FUList6.opList 449 450[system.cpu.fuPool.FUList6.opList] 451type=OpDesc |
| 452eventq_index=0 |
|
| 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu.fuPool.FUList7] 409type=FUDesc 410children=opList0 opList1 411count=4 | 453issueLat=1 454opClass=MemWrite 455opLat=1 456 457[system.cpu.fuPool.FUList7] 458type=FUDesc 459children=opList0 opList1 460count=4 |
| 461eventq_index=0 |
|
| 412opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 413 414[system.cpu.fuPool.FUList7.opList0] 415type=OpDesc | 462opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 463 464[system.cpu.fuPool.FUList7.opList0] 465type=OpDesc |
| 466eventq_index=0 |
|
| 416issueLat=1 417opClass=MemRead 418opLat=1 419 420[system.cpu.fuPool.FUList7.opList1] 421type=OpDesc | 467issueLat=1 468opClass=MemRead 469opLat=1 470 471[system.cpu.fuPool.FUList7.opList1] 472type=OpDesc |
| 473eventq_index=0 |
|
| 422issueLat=1 423opClass=MemWrite 424opLat=1 425 426[system.cpu.fuPool.FUList8] 427type=FUDesc 428children=opList 429count=1 | 474issueLat=1 475opClass=MemWrite 476opLat=1 477 478[system.cpu.fuPool.FUList8] 479type=FUDesc 480children=opList 481count=1 |
| 482eventq_index=0 |
|
| 430opList=system.cpu.fuPool.FUList8.opList 431 432[system.cpu.fuPool.FUList8.opList] 433type=OpDesc | 483opList=system.cpu.fuPool.FUList8.opList 484 485[system.cpu.fuPool.FUList8.opList] 486type=OpDesc |
| 487eventq_index=0 |
|
| 434issueLat=3 435opClass=IprAccess 436opLat=3 437 438[system.cpu.icache] 439type=BaseCache 440children=tags 441addr_ranges=0:18446744073709551615 442assoc=2 443clk_domain=system.cpu_clk_domain | 488issueLat=3 489opClass=IprAccess 490opLat=3 491 492[system.cpu.icache] 493type=BaseCache 494children=tags 495addr_ranges=0:18446744073709551615 496assoc=2 497clk_domain=system.cpu_clk_domain |
| 498eventq_index=0 |
|
| 444forward_snoops=true 445hit_latency=2 446is_top_level=true 447max_miss_count=0 448mshrs=4 449prefetch_on_access=false 450prefetcher=Null 451response_latency=2 --- 6 unchanged lines hidden (view full) --- 458cpu_side=system.cpu.icache_port 459mem_side=system.cpu.toL2Bus.slave[0] 460 461[system.cpu.icache.tags] 462type=LRU 463assoc=2 464block_size=64 465clk_domain=system.cpu_clk_domain | 499forward_snoops=true 500hit_latency=2 501is_top_level=true 502max_miss_count=0 503mshrs=4 504prefetch_on_access=false 505prefetcher=Null 506response_latency=2 --- 6 unchanged lines hidden (view full) --- 513cpu_side=system.cpu.icache_port 514mem_side=system.cpu.toL2Bus.slave[0] 515 516[system.cpu.icache.tags] 517type=LRU 518assoc=2 519block_size=64 520clk_domain=system.cpu_clk_domain |
| 521eventq_index=0 |
|
| 466hit_latency=2 467size=131072 468 469[system.cpu.interrupts] 470type=AlphaInterrupts | 522hit_latency=2 523size=131072 524 525[system.cpu.interrupts] 526type=AlphaInterrupts |
| 527eventq_index=0 |
|
| 471 472[system.cpu.isa] 473type=AlphaISA | 528 529[system.cpu.isa] 530type=AlphaISA |
| 531eventq_index=0 |
|
| 474 475[system.cpu.itb] 476type=AlphaTLB | 532 533[system.cpu.itb] 534type=AlphaTLB |
| 535eventq_index=0 |
|
| 477size=48 478 479[system.cpu.l2cache] 480type=BaseCache 481children=tags 482addr_ranges=0:18446744073709551615 483assoc=8 484clk_domain=system.cpu_clk_domain | 536size=48 537 538[system.cpu.l2cache] 539type=BaseCache 540children=tags 541addr_ranges=0:18446744073709551615 542assoc=8 543clk_domain=system.cpu_clk_domain |
| 544eventq_index=0 |
|
| 485forward_snoops=true 486hit_latency=20 487is_top_level=false 488max_miss_count=0 489mshrs=20 490prefetch_on_access=false 491prefetcher=Null 492response_latency=20 --- 6 unchanged lines hidden (view full) --- 499cpu_side=system.cpu.toL2Bus.master[0] 500mem_side=system.membus.slave[1] 501 502[system.cpu.l2cache.tags] 503type=LRU 504assoc=8 505block_size=64 506clk_domain=system.cpu_clk_domain | 545forward_snoops=true 546hit_latency=20 547is_top_level=false 548max_miss_count=0 549mshrs=20 550prefetch_on_access=false 551prefetcher=Null 552response_latency=20 --- 6 unchanged lines hidden (view full) --- 559cpu_side=system.cpu.toL2Bus.master[0] 560mem_side=system.membus.slave[1] 561 562[system.cpu.l2cache.tags] 563type=LRU 564assoc=8 565block_size=64 566clk_domain=system.cpu_clk_domain |
| 567eventq_index=0 |
|
| 507hit_latency=20 508size=2097152 509 510[system.cpu.toL2Bus] 511type=CoherentBus 512clk_domain=system.cpu_clk_domain | 568hit_latency=20 569size=2097152 570 571[system.cpu.toL2Bus] 572type=CoherentBus 573clk_domain=system.cpu_clk_domain |
| 574eventq_index=0 |
|
| 513header_cycles=1 514system=system 515use_default_range=false 516width=32 517master=system.cpu.l2cache.cpu_side 518slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 519 520[system.cpu.tracer] 521type=ExeTracer | 575header_cycles=1 576system=system 577use_default_range=false 578width=32 579master=system.cpu.l2cache.cpu_side 580slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 581 582[system.cpu.tracer] 583type=ExeTracer |
| 584eventq_index=0 |
|
| 522 523[system.cpu.workload] 524type=LiveProcess 525cmd=hello 526cwd= 527egid=100 528env= 529errout=cerr 530euid=100 | 585 586[system.cpu.workload] 587type=LiveProcess 588cmd=hello 589cwd= 590egid=100 591env= 592errout=cerr 593euid=100 |
| 531executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello | 594eventq_index=0 595executable=tests/test-progs/hello/bin/alpha/linux/hello |
| 532gid=100 533input=cin 534max_stack_size=67108864 535output=cout 536pid=100 537ppid=99 538simpoint=0 539system=system 540uid=100 541 542[system.cpu_clk_domain] 543type=SrcClockDomain 544clock=500 | 596gid=100 597input=cin 598max_stack_size=67108864 599output=cout 600pid=100 601ppid=99 602simpoint=0 603system=system 604uid=100 605 606[system.cpu_clk_domain] 607type=SrcClockDomain 608clock=500 |
| 609eventq_index=0 |
|
| 545voltage_domain=system.voltage_domain 546 547[system.membus] 548type=CoherentBus 549clk_domain=system.clk_domain | 610voltage_domain=system.voltage_domain 611 612[system.membus] 613type=CoherentBus 614clk_domain=system.clk_domain |
| 615eventq_index=0 |
|
| 550header_cycles=1 551system=system 552use_default_range=false 553width=8 554master=system.physmem.port 555slave=system.system_port system.cpu.l2cache.mem_side 556 557[system.physmem] 558type=SimpleDRAM 559activation_limit=4 560addr_mapping=RaBaChCo 561banks_per_rank=8 562burst_length=8 563channels=1 564clk_domain=system.clk_domain 565conf_table_reported=true 566device_bus_width=8 567device_rowbuffer_size=1024 568devices_per_rank=8 | 616header_cycles=1 617system=system 618use_default_range=false 619width=8 620master=system.physmem.port 621slave=system.system_port system.cpu.l2cache.mem_side 622 623[system.physmem] 624type=SimpleDRAM 625activation_limit=4 626addr_mapping=RaBaChCo 627banks_per_rank=8 628burst_length=8 629channels=1 630clk_domain=system.clk_domain 631conf_table_reported=true 632device_bus_width=8 633device_rowbuffer_size=1024 634devices_per_rank=8 |
| 635eventq_index=0 |
|
| 569in_addr_map=true 570mem_sched_policy=frfcfs 571null=false 572page_policy=open 573range=0:134217727 574ranks_per_channel=2 575read_buffer_size=32 576static_backend_latency=10000 577static_frontend_latency=10000 578tBURST=5000 579tCL=13750 | 636in_addr_map=true 637mem_sched_policy=frfcfs 638null=false 639page_policy=open 640range=0:134217727 641ranks_per_channel=2 642read_buffer_size=32 643static_backend_latency=10000 644static_frontend_latency=10000 645tBURST=5000 646tCL=13750 |
| 647tRAS=35000 |
|
| 580tRCD=13750 581tREFI=7800000 582tRFC=300000 583tRP=13750 | 648tRCD=13750 649tREFI=7800000 650tRFC=300000 651tRP=13750 |
| 652tRRD=6250 |
|
| 584tWTR=7500 585tXAW=40000 586write_buffer_size=32 | 653tWTR=7500 654tXAW=40000 655write_buffer_size=32 |
| 587write_thresh_perc=70 | 656write_high_thresh_perc=70 657write_low_thresh_perc=0 |
| 588port=system.membus.master[0] 589 590[system.voltage_domain] 591type=VoltageDomain | 658port=system.membus.master[0] 659 660[system.voltage_domain] 661type=VoltageDomain |
| 662eventq_index=0 |
|
| 592voltage=1.000000 593 | 663voltage=1.000000 664 |