| config.ini (9150:a2370fa5c793) | config.ini (9276:a5ede748a1d9) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a |
| 13clock=1 |
|
| 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= --- 69 unchanged lines hidden (view full) --- 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 | 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= --- 69 unchanged lines hidden (view full) --- 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 |
| 98phase=0 | |
| 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 --- 17 unchanged lines hidden (view full) --- 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 | 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 --- 17 unchanged lines hidden (view full) --- 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 |
| 132clock=1 |
|
| 132forward_snoops=true 133hash_delay=1 | 133forward_snoops=true 134hash_delay=1 |
| 135hit_latency=1000 |
|
| 134is_top_level=true | 136is_top_level=true |
| 135latency=1000 | |
| 136max_miss_count=0 137mshrs=10 138prefetch_on_access=false 139prefetcher=Null 140prioritizeRequests=false 141repl=Null | 137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null |
| 143response_latency=1000 |
|
| 142size=262144 143subblock_size=0 144system=system 145tgts_per_mshr=20 146trace_addr=0 147two_queue=false 148write_buffers=8 149cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 416opClass=IprAccess 417opLat=3 418 419[system.cpu.icache] 420type=BaseCache 421addr_ranges=0:18446744073709551615 422assoc=2 423block_size=64 | 144size=262144 145subblock_size=0 146system=system 147tgts_per_mshr=20 148trace_addr=0 149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 418opClass=IprAccess 419opLat=3 420 421[system.cpu.icache] 422type=BaseCache 423addr_ranges=0:18446744073709551615 424assoc=2 425block_size=64 |
| 426clock=1 |
|
| 424forward_snoops=true 425hash_delay=1 | 427forward_snoops=true 428hash_delay=1 |
| 429hit_latency=1000 |
|
| 426is_top_level=true | 430is_top_level=true |
| 427latency=1000 | |
| 428max_miss_count=0 429mshrs=10 430prefetch_on_access=false 431prefetcher=Null 432prioritizeRequests=false 433repl=Null | 431max_miss_count=0 432mshrs=10 433prefetch_on_access=false 434prefetcher=Null 435prioritizeRequests=false 436repl=Null |
| 437response_latency=1000 |
|
| 434size=131072 435subblock_size=0 436system=system 437tgts_per_mshr=20 438trace_addr=0 439two_queue=false 440write_buffers=8 441cpu_side=system.cpu.icache_port --- 6 unchanged lines hidden (view full) --- 448type=AlphaTLB 449size=48 450 451[system.cpu.l2cache] 452type=BaseCache 453addr_ranges=0:18446744073709551615 454assoc=2 455block_size=64 | 438size=131072 439subblock_size=0 440system=system 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port --- 6 unchanged lines hidden (view full) --- 452type=AlphaTLB 453size=48 454 455[system.cpu.l2cache] 456type=BaseCache 457addr_ranges=0:18446744073709551615 458assoc=2 459block_size=64 |
| 460clock=1 |
|
| 456forward_snoops=true 457hash_delay=1 | 461forward_snoops=true 462hash_delay=1 |
| 463hit_latency=1000 |
|
| 458is_top_level=false | 464is_top_level=false |
| 459latency=1000 | |
| 460max_miss_count=0 461mshrs=10 462prefetch_on_access=false 463prefetcher=Null 464prioritizeRequests=false 465repl=Null | 465max_miss_count=0 466mshrs=10 467prefetch_on_access=false 468prefetcher=Null 469prioritizeRequests=false 470repl=Null |
| 471response_latency=1000 |
|
| 466size=2097152 467subblock_size=0 468system=system 469tgts_per_mshr=5 470trace_addr=0 471two_queue=false 472write_buffers=8 473cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 489[system.cpu.workload] 490type=LiveProcess 491cmd=hello 492cwd= 493egid=100 494env= 495errout=cerr 496euid=100 | 472size=2097152 473subblock_size=0 474system=system 475tgts_per_mshr=5 476trace_addr=0 477two_queue=false 478write_buffers=8 479cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 495[system.cpu.workload] 496type=LiveProcess 497cmd=hello 498cwd= 499egid=100 500env= 501errout=cerr 502euid=100 |
| 497executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello | 503executable=tests/test-progs/hello/bin/alpha/linux/hello |
| 498gid=100 499input=cin 500max_stack_size=67108864 501output=cout 502pid=100 503ppid=99 504simpoint=0 505system=system --- 6 unchanged lines hidden (view full) --- 512header_cycles=1 513use_default_range=false 514width=8 515master=system.physmem.port 516slave=system.system_port system.cpu.l2cache.mem_side 517 518[system.physmem] 519type=SimpleMemory | 504gid=100 505input=cin 506max_stack_size=67108864 507output=cout 508pid=100 509ppid=99 510simpoint=0 511system=system --- 6 unchanged lines hidden (view full) --- 518header_cycles=1 519use_default_range=false 520width=8 521master=system.physmem.port 522slave=system.system_port system.cpu.l2cache.mem_side 523 524[system.physmem] 525type=SimpleMemory |
| 526bandwidth=73.000000 527clock=1 |
|
| 520conf_table_reported=false | 528conf_table_reported=false |
| 521file= | |
| 522in_addr_map=true 523latency=30000 524latency_var=0 525null=false 526range=0:134217727 527zero=false 528port=system.membus.master[0] 529 | 529in_addr_map=true 530latency=30000 531latency_var=0 532null=false 533range=0:134217727 534zero=false 535port=system.membus.master[0] 536 |