config.ini (10636:9ac724889705) config.ini (10736:4433fb00fa7d)
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

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18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=timing
24mem_ranges=
25memories=system.physmem
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 9 unchanged lines hidden (view full) ---

18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=timing
24mem_ranges=
25memories=system.physmem
26mmap_using_noreserve=false
26num_work_ids=16
27readfile=
28symbolfile=
29work_begin_ckpt_count=0
30work_begin_cpu_id_exit=-1
31work_begin_exit_count=0
32work_cpus_ckpt_count=0
33work_end_ckpt_count=0

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582hit_latency=20
583sequential_access=false
584size=2097152
585
586[system.cpu.toL2Bus]
587type=CoherentXBar
588clk_domain=system.cpu_clk_domain
589eventq_index=0
27num_work_ids=16
28readfile=
29symbolfile=
30work_begin_ckpt_count=0
31work_begin_cpu_id_exit=-1
32work_begin_exit_count=0
33work_cpus_ckpt_count=0
34work_end_ckpt_count=0

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583hit_latency=20
584sequential_access=false
585size=2097152
586
587[system.cpu.toL2Bus]
588type=CoherentXBar
589clk_domain=system.cpu_clk_domain
590eventq_index=0
590header_cycles=1
591forward_latency=0
592frontend_latency=1
593response_latency=1
591snoop_filter=Null
594snoop_filter=Null
595snoop_response_latency=1
592system=system
593use_default_range=false
594width=32
595master=system.cpu.l2cache.cpu_side
596slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
597
598[system.cpu.tracer]
599type=ExeTracer

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637eventq_index=0
638sys_clk_domain=system.clk_domain
639transition_latency=100000000
640
641[system.membus]
642type=CoherentXBar
643clk_domain=system.clk_domain
644eventq_index=0
596system=system
597use_default_range=false
598width=32
599master=system.cpu.l2cache.cpu_side
600slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
601
602[system.cpu.tracer]
603type=ExeTracer

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641eventq_index=0
642sys_clk_domain=system.clk_domain
643transition_latency=100000000
644
645[system.membus]
646type=CoherentXBar
647clk_domain=system.clk_domain
648eventq_index=0
645header_cycles=1
649forward_latency=4
650frontend_latency=3
651response_latency=2
646snoop_filter=Null
652snoop_filter=Null
653snoop_response_latency=4
647system=system
648use_default_range=false
654system=system
655use_default_range=false
649width=8
656width=16
650master=system.physmem.port
651slave=system.system_port system.cpu.l2cache.mem_side
652
653[system.physmem]
654type=DRAMCtrl
655IDD0=0.075000
656IDD02=0.000000
657IDD2N=0.050000

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672IDD4W2=0.000000
673IDD5=0.220000
674IDD52=0.000000
675IDD6=0.000000
676IDD62=0.000000
677VDD=1.500000
678VDD2=0.000000
679activation_limit=4
657master=system.physmem.port
658slave=system.system_port system.cpu.l2cache.mem_side
659
660[system.physmem]
661type=DRAMCtrl
662IDD0=0.075000
663IDD02=0.000000
664IDD2N=0.050000

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679IDD4W2=0.000000
680IDD5=0.220000
681IDD52=0.000000
682IDD6=0.000000
683IDD62=0.000000
684VDD=1.500000
685VDD2=0.000000
686activation_limit=4
680addr_mapping=RoRaBaChCo
687addr_mapping=RoRaBaCoCh
681bank_groups_per_rank=0
682banks_per_rank=8
683burst_length=8
684channels=1
685clk_domain=system.clk_domain
686conf_table_reported=true
687device_bus_width=8
688device_rowbuffer_size=1024

--- 46 unchanged lines hidden ---
688bank_groups_per_rank=0
689banks_per_rank=8
690burst_length=8
691channels=1
692clk_domain=system.clk_domain
693conf_table_reported=true
694device_bus_width=8
695device_rowbuffer_size=1024

--- 46 unchanged lines hidden ---