19d18
< physmem=system.physmem
29c28
< system_port=system.membus.port[0]
---
> system_port=system.membus.slave[0]
130c129
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
151c150
< mem_side=system.cpu.toL2Bus.port[1]
---
> mem_side=system.cpu.toL2Bus.slave[1]
422c421
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
443c442
< mem_side=system.cpu.toL2Bus.port[0]
---
> mem_side=system.cpu.toL2Bus.slave[0]
454c453
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
474,475c473,474
< cpu_side=system.cpu.toL2Bus.port[2]
< mem_side=system.membus.port[2]
---
> cpu_side=system.cpu.toL2Bus.master[0]
> mem_side=system.membus.slave[1]
485c484,485
< port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
---
> master=system.cpu.l2cache.cpu_side
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
517c517,518
< port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
---
> master=system.physmem.port[0]
> slave=system.system_port system.cpu.l2cache.mem_side
520c521,522
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
521a524
> in_addr_map=true
527c530
< port=system.membus.port[1]
---
> port=system.membus.master[0]