Cross Reference: /gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini

Deleted Added

sdiff udiff text old ( 9276:a5ede748a1d9 ) new ( 9348:44d31345e360 )

full compact

config.ini (9276:a5ede748a1d9)	config.ini (9348:44d31345e360)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a
13clock=1	13clock=1000
14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU	14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU
33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload	33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts	34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts
	81isa=system.cpu.isa
81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64	82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64
132clock=1	133clock=500
133forward_snoops=true 134hash_delay=1	134forward_snoops=true 135hash_delay=1
135hit_latency=1000	136hit_latency=2
136is_top_level=true 137max_miss_count=0	137is_top_level=true 138max_miss_count=0
138mshrs=10	139mshrs=4
139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null	140prefetch_on_access=false 141prefetcher=Null 142prioritizeRequests=false 143repl=Null
143response_latency=1000	144response_latency=2
144size=262144 145subblock_size=0 146system=system 147tgts_per_mshr=20 148trace_addr=0 149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port 152mem_side=system.cpu.toL2Bus.slave[1] 153 154[system.cpu.dtb] 155type=AlphaTLB 156size=64 157 158[system.cpu.fuPool] 159type=FUPool 160children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 161FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 162 163[system.cpu.fuPool.FUList0] 164type=FUDesc 165children=opList 166count=6 167opList=system.cpu.fuPool.FUList0.opList 168 169[system.cpu.fuPool.FUList0.opList] 170type=OpDesc 171issueLat=1 172opClass=IntAlu 173opLat=1 174 175[system.cpu.fuPool.FUList1] 176type=FUDesc 177children=opList0 opList1 178count=2 179opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 180 181[system.cpu.fuPool.FUList1.opList0] 182type=OpDesc 183issueLat=1 184opClass=IntMult 185opLat=3 186 187[system.cpu.fuPool.FUList1.opList1] 188type=OpDesc 189issueLat=19 190opClass=IntDiv 191opLat=20 192 193[system.cpu.fuPool.FUList2] 194type=FUDesc 195children=opList0 opList1 opList2 196count=4 197opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 198 199[system.cpu.fuPool.FUList2.opList0] 200type=OpDesc 201issueLat=1 202opClass=FloatAdd 203opLat=2 204 205[system.cpu.fuPool.FUList2.opList1] 206type=OpDesc 207issueLat=1 208opClass=FloatCmp 209opLat=2 210 211[system.cpu.fuPool.FUList2.opList2] 212type=OpDesc 213issueLat=1 214opClass=FloatCvt 215opLat=2 216 217[system.cpu.fuPool.FUList3] 218type=FUDesc 219children=opList0 opList1 opList2 220count=2 221opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 222 223[system.cpu.fuPool.FUList3.opList0] 224type=OpDesc 225issueLat=1 226opClass=FloatMult 227opLat=4 228 229[system.cpu.fuPool.FUList3.opList1] 230type=OpDesc 231issueLat=12 232opClass=FloatDiv 233opLat=12 234 235[system.cpu.fuPool.FUList3.opList2] 236type=OpDesc 237issueLat=24 238opClass=FloatSqrt 239opLat=24 240 241[system.cpu.fuPool.FUList4] 242type=FUDesc 243children=opList 244count=0 245opList=system.cpu.fuPool.FUList4.opList 246 247[system.cpu.fuPool.FUList4.opList] 248type=OpDesc 249issueLat=1 250opClass=MemRead 251opLat=1 252 253[system.cpu.fuPool.FUList5] 254type=FUDesc 255children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 256count=4 257opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 258 259[system.cpu.fuPool.FUList5.opList00] 260type=OpDesc 261issueLat=1 262opClass=SimdAdd 263opLat=1 264 265[system.cpu.fuPool.FUList5.opList01] 266type=OpDesc 267issueLat=1 268opClass=SimdAddAcc 269opLat=1 270 271[system.cpu.fuPool.FUList5.opList02] 272type=OpDesc 273issueLat=1 274opClass=SimdAlu 275opLat=1 276 277[system.cpu.fuPool.FUList5.opList03] 278type=OpDesc 279issueLat=1 280opClass=SimdCmp 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList04] 284type=OpDesc 285issueLat=1 286opClass=SimdCvt 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList05] 290type=OpDesc 291issueLat=1 292opClass=SimdMisc 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList06] 296type=OpDesc 297issueLat=1 298opClass=SimdMult 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList07] 302type=OpDesc 303issueLat=1 304opClass=SimdMultAcc 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList08] 308type=OpDesc 309issueLat=1 310opClass=SimdShift 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList09] 314type=OpDesc 315issueLat=1 316opClass=SimdShiftAcc 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList10] 320type=OpDesc 321issueLat=1 322opClass=SimdSqrt 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList11] 326type=OpDesc 327issueLat=1 328opClass=SimdFloatAdd 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList12] 332type=OpDesc 333issueLat=1 334opClass=SimdFloatAlu 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList13] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatCmp 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList14] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatCvt 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList15] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatDiv 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList16] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList17] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatMult 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList18] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatMultAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList19] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatSqrt 377opLat=1 378 379[system.cpu.fuPool.FUList6] 380type=FUDesc 381children=opList 382count=0 383opList=system.cpu.fuPool.FUList6.opList 384 385[system.cpu.fuPool.FUList6.opList] 386type=OpDesc 387issueLat=1 388opClass=MemWrite 389opLat=1 390 391[system.cpu.fuPool.FUList7] 392type=FUDesc 393children=opList0 opList1 394count=4 395opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 396 397[system.cpu.fuPool.FUList7.opList0] 398type=OpDesc 399issueLat=1 400opClass=MemRead 401opLat=1 402 403[system.cpu.fuPool.FUList7.opList1] 404type=OpDesc 405issueLat=1 406opClass=MemWrite 407opLat=1 408 409[system.cpu.fuPool.FUList8] 410type=FUDesc 411children=opList 412count=1 413opList=system.cpu.fuPool.FUList8.opList 414 415[system.cpu.fuPool.FUList8.opList] 416type=OpDesc 417issueLat=3 418opClass=IprAccess 419opLat=3 420 421[system.cpu.icache] 422type=BaseCache 423addr_ranges=0:18446744073709551615 424assoc=2 425block_size=64	145size=262144 146subblock_size=0 147system=system 148tgts_per_mshr=20 149trace_addr=0 150two_queue=false 151write_buffers=8 152cpu_side=system.cpu.dcache_port 153mem_side=system.cpu.toL2Bus.slave[1] 154 155[system.cpu.dtb] 156type=AlphaTLB 157size=64 158 159[system.cpu.fuPool] 160type=FUPool 161children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 162FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 163 164[system.cpu.fuPool.FUList0] 165type=FUDesc 166children=opList 167count=6 168opList=system.cpu.fuPool.FUList0.opList 169 170[system.cpu.fuPool.FUList0.opList] 171type=OpDesc 172issueLat=1 173opClass=IntAlu 174opLat=1 175 176[system.cpu.fuPool.FUList1] 177type=FUDesc 178children=opList0 opList1 179count=2 180opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 181 182[system.cpu.fuPool.FUList1.opList0] 183type=OpDesc 184issueLat=1 185opClass=IntMult 186opLat=3 187 188[system.cpu.fuPool.FUList1.opList1] 189type=OpDesc 190issueLat=19 191opClass=IntDiv 192opLat=20 193 194[system.cpu.fuPool.FUList2] 195type=FUDesc 196children=opList0 opList1 opList2 197count=4 198opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 199 200[system.cpu.fuPool.FUList2.opList0] 201type=OpDesc 202issueLat=1 203opClass=FloatAdd 204opLat=2 205 206[system.cpu.fuPool.FUList2.opList1] 207type=OpDesc 208issueLat=1 209opClass=FloatCmp 210opLat=2 211 212[system.cpu.fuPool.FUList2.opList2] 213type=OpDesc 214issueLat=1 215opClass=FloatCvt 216opLat=2 217 218[system.cpu.fuPool.FUList3] 219type=FUDesc 220children=opList0 opList1 opList2 221count=2 222opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 223 224[system.cpu.fuPool.FUList3.opList0] 225type=OpDesc 226issueLat=1 227opClass=FloatMult 228opLat=4 229 230[system.cpu.fuPool.FUList3.opList1] 231type=OpDesc 232issueLat=12 233opClass=FloatDiv 234opLat=12 235 236[system.cpu.fuPool.FUList3.opList2] 237type=OpDesc 238issueLat=24 239opClass=FloatSqrt 240opLat=24 241 242[system.cpu.fuPool.FUList4] 243type=FUDesc 244children=opList 245count=0 246opList=system.cpu.fuPool.FUList4.opList 247 248[system.cpu.fuPool.FUList4.opList] 249type=OpDesc 250issueLat=1 251opClass=MemRead 252opLat=1 253 254[system.cpu.fuPool.FUList5] 255type=FUDesc 256children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 257count=4 258opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 259 260[system.cpu.fuPool.FUList5.opList00] 261type=OpDesc 262issueLat=1 263opClass=SimdAdd 264opLat=1 265 266[system.cpu.fuPool.FUList5.opList01] 267type=OpDesc 268issueLat=1 269opClass=SimdAddAcc 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList02] 273type=OpDesc 274issueLat=1 275opClass=SimdAlu 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList03] 279type=OpDesc 280issueLat=1 281opClass=SimdCmp 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList04] 285type=OpDesc 286issueLat=1 287opClass=SimdCvt 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList05] 291type=OpDesc 292issueLat=1 293opClass=SimdMisc 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList06] 297type=OpDesc 298issueLat=1 299opClass=SimdMult 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList07] 303type=OpDesc 304issueLat=1 305opClass=SimdMultAcc 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList08] 309type=OpDesc 310issueLat=1 311opClass=SimdShift 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList09] 315type=OpDesc 316issueLat=1 317opClass=SimdShiftAcc 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList10] 321type=OpDesc 322issueLat=1 323opClass=SimdSqrt 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList11] 327type=OpDesc 328issueLat=1 329opClass=SimdFloatAdd 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList12] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatAlu 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList13] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatCmp 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList14] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatCvt 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList15] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatDiv 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList16] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatMisc 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList17] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMult 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList18] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatMultAcc 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList19] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatSqrt 378opLat=1 379 380[system.cpu.fuPool.FUList6] 381type=FUDesc 382children=opList 383count=0 384opList=system.cpu.fuPool.FUList6.opList 385 386[system.cpu.fuPool.FUList6.opList] 387type=OpDesc 388issueLat=1 389opClass=MemWrite 390opLat=1 391 392[system.cpu.fuPool.FUList7] 393type=FUDesc 394children=opList0 opList1 395count=4 396opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 397 398[system.cpu.fuPool.FUList7.opList0] 399type=OpDesc 400issueLat=1 401opClass=MemRead 402opLat=1 403 404[system.cpu.fuPool.FUList7.opList1] 405type=OpDesc 406issueLat=1 407opClass=MemWrite 408opLat=1 409 410[system.cpu.fuPool.FUList8] 411type=FUDesc 412children=opList 413count=1 414opList=system.cpu.fuPool.FUList8.opList 415 416[system.cpu.fuPool.FUList8.opList] 417type=OpDesc 418issueLat=3 419opClass=IprAccess 420opLat=3 421 422[system.cpu.icache] 423type=BaseCache 424addr_ranges=0:18446744073709551615 425assoc=2 426block_size=64
426clock=1	427clock=500
427forward_snoops=true 428hash_delay=1	428forward_snoops=true 429hash_delay=1
429hit_latency=1000	430hit_latency=2
430is_top_level=true 431max_miss_count=0	431is_top_level=true 432max_miss_count=0
432mshrs=10	433mshrs=4
433prefetch_on_access=false 434prefetcher=Null 435prioritizeRequests=false 436repl=Null	434prefetch_on_access=false 435prefetcher=Null 436prioritizeRequests=false 437repl=Null
437response_latency=1000	438response_latency=2
438size=131072 439subblock_size=0 440system=system 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port 446mem_side=system.cpu.toL2Bus.slave[0] 447 448[system.cpu.interrupts] 449type=AlphaInterrupts 450	439size=131072 440subblock_size=0 441system=system 442tgts_per_mshr=20 443trace_addr=0 444two_queue=false 445write_buffers=8 446cpu_side=system.cpu.icache_port 447mem_side=system.cpu.toL2Bus.slave[0] 448 449[system.cpu.interrupts] 450type=AlphaInterrupts 451
	452[system.cpu.isa] 453type=AlphaISA 454
451[system.cpu.itb] 452type=AlphaTLB 453size=48 454 455[system.cpu.l2cache] 456type=BaseCache 457addr_ranges=0:18446744073709551615	455[system.cpu.itb] 456type=AlphaTLB 457size=48 458 459[system.cpu.l2cache] 460type=BaseCache 461addr_ranges=0:18446744073709551615
458assoc=2	462assoc=8
459block_size=64	463block_size=64
460clock=1	464clock=500
461forward_snoops=true 462hash_delay=1	465forward_snoops=true 466hash_delay=1
463hit_latency=1000	467hit_latency=20
464is_top_level=false 465max_miss_count=0	468is_top_level=false 469max_miss_count=0
466mshrs=10	470mshrs=20
467prefetch_on_access=false 468prefetcher=Null 469prioritizeRequests=false 470repl=Null	471prefetch_on_access=false 472prefetcher=Null 473prioritizeRequests=false 474repl=Null
471response_latency=1000	475response_latency=20
472size=2097152 473subblock_size=0 474system=system	476size=2097152 477subblock_size=0 478system=system
475tgts_per_mshr=5	479tgts_per_mshr=12
476trace_addr=0 477two_queue=false 478write_buffers=8 479cpu_side=system.cpu.toL2Bus.master[0] 480mem_side=system.membus.slave[1] 481 482[system.cpu.toL2Bus] 483type=CoherentBus 484block_size=64	480trace_addr=0 481two_queue=false 482write_buffers=8 483cpu_side=system.cpu.toL2Bus.master[0] 484mem_side=system.membus.slave[1] 485 486[system.cpu.toL2Bus] 487type=CoherentBus 488block_size=64
485clock=1000	489clock=500
486header_cycles=1 487use_default_range=false	490header_cycles=1 491use_default_range=false
488width=8	492width=32
489master=system.cpu.l2cache.cpu_side 490slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 491 492[system.cpu.tracer] 493type=ExeTracer 494 495[system.cpu.workload] 496type=LiveProcess 497cmd=hello 498cwd= 499egid=100 500env= 501errout=cerr 502euid=100	493master=system.cpu.l2cache.cpu_side 494slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 495 496[system.cpu.tracer] 497type=ExeTracer 498 499[system.cpu.workload] 500type=LiveProcess 501cmd=hello 502cwd= 503egid=100 504env= 505errout=cerr 506euid=100
503executable=tests/test-progs/hello/bin/alpha/linux/hello	507executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
504gid=100 505input=cin 506max_stack_size=67108864 507output=cout 508pid=100 509ppid=99 510simpoint=0 511system=system 512uid=100 513 514[system.membus] 515type=CoherentBus 516block_size=64 517clock=1000 518header_cycles=1 519use_default_range=false 520width=8 521master=system.physmem.port 522slave=system.system_port system.cpu.l2cache.mem_side 523 524[system.physmem]	508gid=100 509input=cin 510max_stack_size=67108864 511output=cout 512pid=100 513ppid=99 514simpoint=0 515system=system 516uid=100 517 518[system.membus] 519type=CoherentBus 520block_size=64 521clock=1000 522header_cycles=1 523use_default_range=false 524width=8 525master=system.physmem.port 526slave=system.system_port system.cpu.l2cache.mem_side 527 528[system.physmem]
525type=SimpleMemory 526bandwidth=73.000000 527clock=1	529type=SimpleDRAM 530addr_mapping=openmap 531banks_per_rank=8 532clock=1000
528conf_table_reported=false 529in_addr_map=true	533conf_table_reported=false 534in_addr_map=true
530latency=30000 531latency_var=0	535lines_per_rowbuffer=64 536mem_sched_policy=fcfs
532null=false	537null=false
	538page_policy=open
533range=0:134217727	539range=0:134217727
	540ranks_per_channel=2 541read_buffer_size=32 542tBURST=4000 543tCL=14000 544tRCD=14000 545tREFI=7800000 546tRFC=300000 547tRP=14000 548tWTR=1000 549write_buffer_size=32 550write_thresh_perc=70
534zero=false 535port=system.membus.master[0] 536	551zero=false 552port=system.membus.master[0] 553