Cross Reference: /gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini

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config.ini (9150:a2370fa5c793)	config.ini (9276:a5ede748a1d9)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a
	13clock=1
13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 28system_port=system.membus.slave[0] 29 30[system.cpu] 31type=DerivO3CPU 32children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39RASSize=16 40SQEntries=32 41SSITSize=1024 42activity=0 43backComSize=5 44cachePorts=200 45checker=Null 46choiceCtrBits=2 47choicePredictorSize=8192 48clock=500 49commitToDecodeDelay=1 50commitToFetchDelay=1 51commitToIEWDelay=1 52commitToRenameDelay=1 53commitWidth=8 54cpu_id=0 55decodeToFetchDelay=1 56decodeToRenameDelay=1 57decodeWidth=8 58defer_registration=false 59dispatchWidth=8 60do_checkpoint_insts=true 61do_quiesce=true 62do_statistics_insts=true 63dtb=system.cpu.dtb 64fetchToDecodeDelay=1 65fetchTrapLatency=1 66fetchWidth=8 67forwardComSize=5 68fuPool=system.cpu.fuPool 69function_trace=false 70function_trace_start=0 71globalCtrBits=2 72globalHistoryBits=13 73globalPredictorSize=8192 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78instShiftAmt=2 79interrupts=system.cpu.interrupts 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83localCtrBits=2 84localHistoryBits=11 85localHistoryTableSize=2048 86localPredictorSize=2048 87max_insts_all_threads=0 88max_insts_any_thread=0 89max_loads_all_threads=0 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1	14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1
98phase=0
99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64	99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64
	132clock=1
132forward_snoops=true 133hash_delay=1	133forward_snoops=true 134hash_delay=1
	135hit_latency=1000
134is_top_level=true	136is_top_level=true
135latency=1000
136max_miss_count=0 137mshrs=10 138prefetch_on_access=false 139prefetcher=Null 140prioritizeRequests=false 141repl=Null	137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null
	143response_latency=1000
142size=262144 143subblock_size=0 144system=system 145tgts_per_mshr=20 146trace_addr=0 147two_queue=false 148write_buffers=8 149cpu_side=system.cpu.dcache_port 150mem_side=system.cpu.toL2Bus.slave[1] 151 152[system.cpu.dtb] 153type=AlphaTLB 154size=64 155 156[system.cpu.fuPool] 157type=FUPool 158children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 159FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 160 161[system.cpu.fuPool.FUList0] 162type=FUDesc 163children=opList 164count=6 165opList=system.cpu.fuPool.FUList0.opList 166 167[system.cpu.fuPool.FUList0.opList] 168type=OpDesc 169issueLat=1 170opClass=IntAlu 171opLat=1 172 173[system.cpu.fuPool.FUList1] 174type=FUDesc 175children=opList0 opList1 176count=2 177opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 178 179[system.cpu.fuPool.FUList1.opList0] 180type=OpDesc 181issueLat=1 182opClass=IntMult 183opLat=3 184 185[system.cpu.fuPool.FUList1.opList1] 186type=OpDesc 187issueLat=19 188opClass=IntDiv 189opLat=20 190 191[system.cpu.fuPool.FUList2] 192type=FUDesc 193children=opList0 opList1 opList2 194count=4 195opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 196 197[system.cpu.fuPool.FUList2.opList0] 198type=OpDesc 199issueLat=1 200opClass=FloatAdd 201opLat=2 202 203[system.cpu.fuPool.FUList2.opList1] 204type=OpDesc 205issueLat=1 206opClass=FloatCmp 207opLat=2 208 209[system.cpu.fuPool.FUList2.opList2] 210type=OpDesc 211issueLat=1 212opClass=FloatCvt 213opLat=2 214 215[system.cpu.fuPool.FUList3] 216type=FUDesc 217children=opList0 opList1 opList2 218count=2 219opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 220 221[system.cpu.fuPool.FUList3.opList0] 222type=OpDesc 223issueLat=1 224opClass=FloatMult 225opLat=4 226 227[system.cpu.fuPool.FUList3.opList1] 228type=OpDesc 229issueLat=12 230opClass=FloatDiv 231opLat=12 232 233[system.cpu.fuPool.FUList3.opList2] 234type=OpDesc 235issueLat=24 236opClass=FloatSqrt 237opLat=24 238 239[system.cpu.fuPool.FUList4] 240type=FUDesc 241children=opList 242count=0 243opList=system.cpu.fuPool.FUList4.opList 244 245[system.cpu.fuPool.FUList4.opList] 246type=OpDesc 247issueLat=1 248opClass=MemRead 249opLat=1 250 251[system.cpu.fuPool.FUList5] 252type=FUDesc 253children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 254count=4 255opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 256 257[system.cpu.fuPool.FUList5.opList00] 258type=OpDesc 259issueLat=1 260opClass=SimdAdd 261opLat=1 262 263[system.cpu.fuPool.FUList5.opList01] 264type=OpDesc 265issueLat=1 266opClass=SimdAddAcc 267opLat=1 268 269[system.cpu.fuPool.FUList5.opList02] 270type=OpDesc 271issueLat=1 272opClass=SimdAlu 273opLat=1 274 275[system.cpu.fuPool.FUList5.opList03] 276type=OpDesc 277issueLat=1 278opClass=SimdCmp 279opLat=1 280 281[system.cpu.fuPool.FUList5.opList04] 282type=OpDesc 283issueLat=1 284opClass=SimdCvt 285opLat=1 286 287[system.cpu.fuPool.FUList5.opList05] 288type=OpDesc 289issueLat=1 290opClass=SimdMisc 291opLat=1 292 293[system.cpu.fuPool.FUList5.opList06] 294type=OpDesc 295issueLat=1 296opClass=SimdMult 297opLat=1 298 299[system.cpu.fuPool.FUList5.opList07] 300type=OpDesc 301issueLat=1 302opClass=SimdMultAcc 303opLat=1 304 305[system.cpu.fuPool.FUList5.opList08] 306type=OpDesc 307issueLat=1 308opClass=SimdShift 309opLat=1 310 311[system.cpu.fuPool.FUList5.opList09] 312type=OpDesc 313issueLat=1 314opClass=SimdShiftAcc 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList10] 318type=OpDesc 319issueLat=1 320opClass=SimdSqrt 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList11] 324type=OpDesc 325issueLat=1 326opClass=SimdFloatAdd 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList12] 330type=OpDesc 331issueLat=1 332opClass=SimdFloatAlu 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList13] 336type=OpDesc 337issueLat=1 338opClass=SimdFloatCmp 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList14] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatCvt 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList15] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatDiv 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList16] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatMisc 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList17] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatMult 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList18] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatMultAcc 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList19] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatSqrt 375opLat=1 376 377[system.cpu.fuPool.FUList6] 378type=FUDesc 379children=opList 380count=0 381opList=system.cpu.fuPool.FUList6.opList 382 383[system.cpu.fuPool.FUList6.opList] 384type=OpDesc 385issueLat=1 386opClass=MemWrite 387opLat=1 388 389[system.cpu.fuPool.FUList7] 390type=FUDesc 391children=opList0 opList1 392count=4 393opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 394 395[system.cpu.fuPool.FUList7.opList0] 396type=OpDesc 397issueLat=1 398opClass=MemRead 399opLat=1 400 401[system.cpu.fuPool.FUList7.opList1] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu.fuPool.FUList8] 408type=FUDesc 409children=opList 410count=1 411opList=system.cpu.fuPool.FUList8.opList 412 413[system.cpu.fuPool.FUList8.opList] 414type=OpDesc 415issueLat=3 416opClass=IprAccess 417opLat=3 418 419[system.cpu.icache] 420type=BaseCache 421addr_ranges=0:18446744073709551615 422assoc=2 423block_size=64	144size=262144 145subblock_size=0 146system=system 147tgts_per_mshr=20 148trace_addr=0 149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port 152mem_side=system.cpu.toL2Bus.slave[1] 153 154[system.cpu.dtb] 155type=AlphaTLB 156size=64 157 158[system.cpu.fuPool] 159type=FUPool 160children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 161FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 162 163[system.cpu.fuPool.FUList0] 164type=FUDesc 165children=opList 166count=6 167opList=system.cpu.fuPool.FUList0.opList 168 169[system.cpu.fuPool.FUList0.opList] 170type=OpDesc 171issueLat=1 172opClass=IntAlu 173opLat=1 174 175[system.cpu.fuPool.FUList1] 176type=FUDesc 177children=opList0 opList1 178count=2 179opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 180 181[system.cpu.fuPool.FUList1.opList0] 182type=OpDesc 183issueLat=1 184opClass=IntMult 185opLat=3 186 187[system.cpu.fuPool.FUList1.opList1] 188type=OpDesc 189issueLat=19 190opClass=IntDiv 191opLat=20 192 193[system.cpu.fuPool.FUList2] 194type=FUDesc 195children=opList0 opList1 opList2 196count=4 197opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 198 199[system.cpu.fuPool.FUList2.opList0] 200type=OpDesc 201issueLat=1 202opClass=FloatAdd 203opLat=2 204 205[system.cpu.fuPool.FUList2.opList1] 206type=OpDesc 207issueLat=1 208opClass=FloatCmp 209opLat=2 210 211[system.cpu.fuPool.FUList2.opList2] 212type=OpDesc 213issueLat=1 214opClass=FloatCvt 215opLat=2 216 217[system.cpu.fuPool.FUList3] 218type=FUDesc 219children=opList0 opList1 opList2 220count=2 221opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 222 223[system.cpu.fuPool.FUList3.opList0] 224type=OpDesc 225issueLat=1 226opClass=FloatMult 227opLat=4 228 229[system.cpu.fuPool.FUList3.opList1] 230type=OpDesc 231issueLat=12 232opClass=FloatDiv 233opLat=12 234 235[system.cpu.fuPool.FUList3.opList2] 236type=OpDesc 237issueLat=24 238opClass=FloatSqrt 239opLat=24 240 241[system.cpu.fuPool.FUList4] 242type=FUDesc 243children=opList 244count=0 245opList=system.cpu.fuPool.FUList4.opList 246 247[system.cpu.fuPool.FUList4.opList] 248type=OpDesc 249issueLat=1 250opClass=MemRead 251opLat=1 252 253[system.cpu.fuPool.FUList5] 254type=FUDesc 255children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 256count=4 257opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 258 259[system.cpu.fuPool.FUList5.opList00] 260type=OpDesc 261issueLat=1 262opClass=SimdAdd 263opLat=1 264 265[system.cpu.fuPool.FUList5.opList01] 266type=OpDesc 267issueLat=1 268opClass=SimdAddAcc 269opLat=1 270 271[system.cpu.fuPool.FUList5.opList02] 272type=OpDesc 273issueLat=1 274opClass=SimdAlu 275opLat=1 276 277[system.cpu.fuPool.FUList5.opList03] 278type=OpDesc 279issueLat=1 280opClass=SimdCmp 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList04] 284type=OpDesc 285issueLat=1 286opClass=SimdCvt 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList05] 290type=OpDesc 291issueLat=1 292opClass=SimdMisc 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList06] 296type=OpDesc 297issueLat=1 298opClass=SimdMult 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList07] 302type=OpDesc 303issueLat=1 304opClass=SimdMultAcc 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList08] 308type=OpDesc 309issueLat=1 310opClass=SimdShift 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList09] 314type=OpDesc 315issueLat=1 316opClass=SimdShiftAcc 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList10] 320type=OpDesc 321issueLat=1 322opClass=SimdSqrt 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList11] 326type=OpDesc 327issueLat=1 328opClass=SimdFloatAdd 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList12] 332type=OpDesc 333issueLat=1 334opClass=SimdFloatAlu 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList13] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatCmp 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList14] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatCvt 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList15] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatDiv 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList16] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList17] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatMult 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList18] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatMultAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList19] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatSqrt 377opLat=1 378 379[system.cpu.fuPool.FUList6] 380type=FUDesc 381children=opList 382count=0 383opList=system.cpu.fuPool.FUList6.opList 384 385[system.cpu.fuPool.FUList6.opList] 386type=OpDesc 387issueLat=1 388opClass=MemWrite 389opLat=1 390 391[system.cpu.fuPool.FUList7] 392type=FUDesc 393children=opList0 opList1 394count=4 395opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 396 397[system.cpu.fuPool.FUList7.opList0] 398type=OpDesc 399issueLat=1 400opClass=MemRead 401opLat=1 402 403[system.cpu.fuPool.FUList7.opList1] 404type=OpDesc 405issueLat=1 406opClass=MemWrite 407opLat=1 408 409[system.cpu.fuPool.FUList8] 410type=FUDesc 411children=opList 412count=1 413opList=system.cpu.fuPool.FUList8.opList 414 415[system.cpu.fuPool.FUList8.opList] 416type=OpDesc 417issueLat=3 418opClass=IprAccess 419opLat=3 420 421[system.cpu.icache] 422type=BaseCache 423addr_ranges=0:18446744073709551615 424assoc=2 425block_size=64
	426clock=1
424forward_snoops=true 425hash_delay=1	427forward_snoops=true 428hash_delay=1
	429hit_latency=1000
426is_top_level=true	430is_top_level=true
427latency=1000
428max_miss_count=0 429mshrs=10 430prefetch_on_access=false 431prefetcher=Null 432prioritizeRequests=false 433repl=Null	431max_miss_count=0 432mshrs=10 433prefetch_on_access=false 434prefetcher=Null 435prioritizeRequests=false 436repl=Null
	437response_latency=1000
434size=131072 435subblock_size=0 436system=system 437tgts_per_mshr=20 438trace_addr=0 439two_queue=false 440write_buffers=8 441cpu_side=system.cpu.icache_port 442mem_side=system.cpu.toL2Bus.slave[0] 443 444[system.cpu.interrupts] 445type=AlphaInterrupts 446 447[system.cpu.itb] 448type=AlphaTLB 449size=48 450 451[system.cpu.l2cache] 452type=BaseCache 453addr_ranges=0:18446744073709551615 454assoc=2 455block_size=64	438size=131072 439subblock_size=0 440system=system 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port 446mem_side=system.cpu.toL2Bus.slave[0] 447 448[system.cpu.interrupts] 449type=AlphaInterrupts 450 451[system.cpu.itb] 452type=AlphaTLB 453size=48 454 455[system.cpu.l2cache] 456type=BaseCache 457addr_ranges=0:18446744073709551615 458assoc=2 459block_size=64
	460clock=1
456forward_snoops=true 457hash_delay=1	461forward_snoops=true 462hash_delay=1
	463hit_latency=1000
458is_top_level=false	464is_top_level=false
459latency=1000
460max_miss_count=0 461mshrs=10 462prefetch_on_access=false 463prefetcher=Null 464prioritizeRequests=false 465repl=Null	465max_miss_count=0 466mshrs=10 467prefetch_on_access=false 468prefetcher=Null 469prioritizeRequests=false 470repl=Null
	471response_latency=1000
466size=2097152 467subblock_size=0 468system=system 469tgts_per_mshr=5 470trace_addr=0 471two_queue=false 472write_buffers=8 473cpu_side=system.cpu.toL2Bus.master[0] 474mem_side=system.membus.slave[1] 475 476[system.cpu.toL2Bus] 477type=CoherentBus 478block_size=64 479clock=1000 480header_cycles=1 481use_default_range=false 482width=8 483master=system.cpu.l2cache.cpu_side 484slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 485 486[system.cpu.tracer] 487type=ExeTracer 488 489[system.cpu.workload] 490type=LiveProcess 491cmd=hello 492cwd= 493egid=100 494env= 495errout=cerr 496euid=100	472size=2097152 473subblock_size=0 474system=system 475tgts_per_mshr=5 476trace_addr=0 477two_queue=false 478write_buffers=8 479cpu_side=system.cpu.toL2Bus.master[0] 480mem_side=system.membus.slave[1] 481 482[system.cpu.toL2Bus] 483type=CoherentBus 484block_size=64 485clock=1000 486header_cycles=1 487use_default_range=false 488width=8 489master=system.cpu.l2cache.cpu_side 490slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 491 492[system.cpu.tracer] 493type=ExeTracer 494 495[system.cpu.workload] 496type=LiveProcess 497cmd=hello 498cwd= 499egid=100 500env= 501errout=cerr 502euid=100
497executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello	503executable=tests/test-progs/hello/bin/alpha/linux/hello
498gid=100 499input=cin 500max_stack_size=67108864 501output=cout 502pid=100 503ppid=99 504simpoint=0 505system=system 506uid=100 507 508[system.membus] 509type=CoherentBus 510block_size=64 511clock=1000 512header_cycles=1 513use_default_range=false 514width=8 515master=system.physmem.port 516slave=system.system_port system.cpu.l2cache.mem_side 517 518[system.physmem] 519type=SimpleMemory	504gid=100 505input=cin 506max_stack_size=67108864 507output=cout 508pid=100 509ppid=99 510simpoint=0 511system=system 512uid=100 513 514[system.membus] 515type=CoherentBus 516block_size=64 517clock=1000 518header_cycles=1 519use_default_range=false 520width=8 521master=system.physmem.port 522slave=system.system_port system.cpu.l2cache.mem_side 523 524[system.physmem] 525type=SimpleMemory
	526bandwidth=73.000000 527clock=1
520conf_table_reported=false	528conf_table_reported=false
521file=
522in_addr_map=true 523latency=30000 524latency_var=0 525null=false 526range=0:134217727 527zero=false 528port=system.membus.master[0] 529	529in_addr_map=true 530latency=30000 531latency_var=0 532null=false 533range=0:134217727 534zero=false 535port=system.membus.master[0] 536