Cross Reference: /gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini

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config.ini (11680:b4d943429dc6)	config.ini (11731:c473ca7cc650)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts 101isa=system.cpu.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142system=system 143tracer=system.cpu.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu.workload 147dcache_port=system.cpu.dcache.cpu_side 148icache_port=system.cpu.icache.cpu_side 149 150[system.cpu.branchPred] 151type=TournamentBP 152BTBEntries=4096 153BTBTagSize=16 154RASSize=16 155choiceCtrBits=2 156choicePredictorSize=8192 157eventq_index=0 158globalCtrBits=2 159globalPredictorSize=8192 160indirectHashGHR=true 161indirectHashTargets=true 162indirectPathLength=3 163indirectSets=256 164indirectTagSize=16 165indirectWays=2 166instShiftAmt=2 167localCtrBits=2 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171useIndirect=true 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 80default_p_state=UNDEFINED 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts 101isa=system.cpu.isa 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=1 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142system=system 143tracer=system.cpu.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu.workload 147dcache_port=system.cpu.dcache.cpu_side 148icache_port=system.cpu.icache.cpu_side 149 150[system.cpu.branchPred] 151type=TournamentBP 152BTBEntries=4096 153BTBTagSize=16 154RASSize=16 155choiceCtrBits=2 156choicePredictorSize=8192 157eventq_index=0 158globalCtrBits=2 159globalPredictorSize=8192 160indirectHashGHR=true 161indirectHashTargets=true 162indirectPathLength=3 163indirectSets=256 164indirectTagSize=16 165indirectWays=2 166instShiftAmt=2 167localCtrBits=2 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171useIndirect=true 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl
	180data_latency=2
180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0	181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0
183hit_latency=2
184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=262144 196system=system	184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=262144 196system=system
	197tag_latency=2
197tags=system.cpu.dcache.tags 198tgts_per_mshr=20 199write_buffers=8 200writeback_clean=false 201cpu_side=system.cpu.dcache_port 202mem_side=system.cpu.toL2Bus.slave[1] 203 204[system.cpu.dcache.tags] 205type=LRU 206assoc=2 207block_size=64 208clk_domain=system.cpu_clk_domain	198tags=system.cpu.dcache.tags 199tgts_per_mshr=20 200write_buffers=8 201writeback_clean=false 202cpu_side=system.cpu.dcache_port 203mem_side=system.cpu.toL2Bus.slave[1] 204 205[system.cpu.dcache.tags] 206type=LRU 207assoc=2 208block_size=64 209clk_domain=system.cpu_clk_domain
	210data_latency=2
209default_p_state=UNDEFINED 210eventq_index=0	211default_p_state=UNDEFINED 212eventq_index=0
211hit_latency=2
212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null 216sequential_access=false 217size=262144	213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=262144
	219tag_latency=2
218 219[system.cpu.dtb] 220type=AlphaTLB 221eventq_index=0 222size=64 223 224[system.cpu.fuPool] 225type=FUPool 226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 227FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 228eventq_index=0 229 230[system.cpu.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 234eventq_index=0 235opList=system.cpu.fuPool.FUList0.opList 236 237[system.cpu.fuPool.FUList0.opList] 238type=OpDesc 239eventq_index=0 240opClass=IntAlu 241opLat=1 242pipelined=true 243 244[system.cpu.fuPool.FUList1] 245type=FUDesc 246children=opList0 opList1 247count=2 248eventq_index=0 249opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 250 251[system.cpu.fuPool.FUList1.opList0] 252type=OpDesc 253eventq_index=0 254opClass=IntMult 255opLat=3 256pipelined=true 257 258[system.cpu.fuPool.FUList1.opList1] 259type=OpDesc 260eventq_index=0 261opClass=IntDiv 262opLat=20 263pipelined=false 264 265[system.cpu.fuPool.FUList2] 266type=FUDesc 267children=opList0 opList1 opList2 268count=4 269eventq_index=0 270opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 271 272[system.cpu.fuPool.FUList2.opList0] 273type=OpDesc 274eventq_index=0 275opClass=FloatAdd 276opLat=2 277pipelined=true 278 279[system.cpu.fuPool.FUList2.opList1] 280type=OpDesc 281eventq_index=0 282opClass=FloatCmp 283opLat=2 284pipelined=true 285 286[system.cpu.fuPool.FUList2.opList2] 287type=OpDesc 288eventq_index=0 289opClass=FloatCvt 290opLat=2 291pipelined=true 292 293[system.cpu.fuPool.FUList3] 294type=FUDesc	220 221[system.cpu.dtb] 222type=AlphaTLB 223eventq_index=0 224size=64 225 226[system.cpu.fuPool] 227type=FUPool 228children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 229FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 230eventq_index=0 231 232[system.cpu.fuPool.FUList0] 233type=FUDesc 234children=opList 235count=6 236eventq_index=0 237opList=system.cpu.fuPool.FUList0.opList 238 239[system.cpu.fuPool.FUList0.opList] 240type=OpDesc 241eventq_index=0 242opClass=IntAlu 243opLat=1 244pipelined=true 245 246[system.cpu.fuPool.FUList1] 247type=FUDesc 248children=opList0 opList1 249count=2 250eventq_index=0 251opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 252 253[system.cpu.fuPool.FUList1.opList0] 254type=OpDesc 255eventq_index=0 256opClass=IntMult 257opLat=3 258pipelined=true 259 260[system.cpu.fuPool.FUList1.opList1] 261type=OpDesc 262eventq_index=0 263opClass=IntDiv 264opLat=20 265pipelined=false 266 267[system.cpu.fuPool.FUList2] 268type=FUDesc 269children=opList0 opList1 opList2 270count=4 271eventq_index=0 272opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 273 274[system.cpu.fuPool.FUList2.opList0] 275type=OpDesc 276eventq_index=0 277opClass=FloatAdd 278opLat=2 279pipelined=true 280 281[system.cpu.fuPool.FUList2.opList1] 282type=OpDesc 283eventq_index=0 284opClass=FloatCmp 285opLat=2 286pipelined=true 287 288[system.cpu.fuPool.FUList2.opList2] 289type=OpDesc 290eventq_index=0 291opClass=FloatCvt 292opLat=2 293pipelined=true 294 295[system.cpu.fuPool.FUList3] 296type=FUDesc
295children=opList0 opList1 opList2	297children=opList0 opList1 opList2 opList3 opList4
296count=2 297eventq_index=0	298count=2 299eventq_index=0
298opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2	300opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
299 300[system.cpu.fuPool.FUList3.opList0] 301type=OpDesc 302eventq_index=0 303opClass=FloatMult 304opLat=4 305pipelined=true 306 307[system.cpu.fuPool.FUList3.opList1] 308type=OpDesc 309eventq_index=0	301 302[system.cpu.fuPool.FUList3.opList0] 303type=OpDesc 304eventq_index=0 305opClass=FloatMult 306opLat=4 307pipelined=true 308 309[system.cpu.fuPool.FUList3.opList1] 310type=OpDesc 311eventq_index=0
	312opClass=FloatMultAcc 313opLat=5 314pipelined=true 315 316[system.cpu.fuPool.FUList3.opList2] 317type=OpDesc 318eventq_index=0 319opClass=FloatMisc 320opLat=3 321pipelined=true 322 323[system.cpu.fuPool.FUList3.opList3] 324type=OpDesc 325eventq_index=0
310opClass=FloatDiv 311opLat=12 312pipelined=false 313	326opClass=FloatDiv 327opLat=12 328pipelined=false 329
314[system.cpu.fuPool.FUList3.opList2]	330[system.cpu.fuPool.FUList3.opList4]
315type=OpDesc 316eventq_index=0 317opClass=FloatSqrt 318opLat=24 319pipelined=false 320 321[system.cpu.fuPool.FUList4] 322type=FUDesc	331type=OpDesc 332eventq_index=0 333opClass=FloatSqrt 334opLat=24 335pipelined=false 336 337[system.cpu.fuPool.FUList4] 338type=FUDesc
323children=opList	339children=opList0 opList1
324count=0 325eventq_index=0	340count=0 341eventq_index=0
326opList=system.cpu.fuPool.FUList4.opList	342opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
327	343
328[system.cpu.fuPool.FUList4.opList]	344[system.cpu.fuPool.FUList4.opList0]
329type=OpDesc 330eventq_index=0 331opClass=MemRead 332opLat=1 333pipelined=true 334	345type=OpDesc 346eventq_index=0 347opClass=MemRead 348opLat=1 349pipelined=true 350
	351[system.cpu.fuPool.FUList4.opList1] 352type=OpDesc 353eventq_index=0 354opClass=FloatMemRead 355opLat=1 356pipelined=true 357
335[system.cpu.fuPool.FUList5] 336type=FUDesc 337children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 338count=4 339eventq_index=0 340opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 341 342[system.cpu.fuPool.FUList5.opList00] 343type=OpDesc 344eventq_index=0 345opClass=SimdAdd 346opLat=1 347pipelined=true 348 349[system.cpu.fuPool.FUList5.opList01] 350type=OpDesc 351eventq_index=0 352opClass=SimdAddAcc 353opLat=1 354pipelined=true 355 356[system.cpu.fuPool.FUList5.opList02] 357type=OpDesc 358eventq_index=0 359opClass=SimdAlu 360opLat=1 361pipelined=true 362 363[system.cpu.fuPool.FUList5.opList03] 364type=OpDesc 365eventq_index=0 366opClass=SimdCmp 367opLat=1 368pipelined=true 369 370[system.cpu.fuPool.FUList5.opList04] 371type=OpDesc 372eventq_index=0 373opClass=SimdCvt 374opLat=1 375pipelined=true 376 377[system.cpu.fuPool.FUList5.opList05] 378type=OpDesc 379eventq_index=0 380opClass=SimdMisc 381opLat=1 382pipelined=true 383 384[system.cpu.fuPool.FUList5.opList06] 385type=OpDesc 386eventq_index=0 387opClass=SimdMult 388opLat=1 389pipelined=true 390 391[system.cpu.fuPool.FUList5.opList07] 392type=OpDesc 393eventq_index=0 394opClass=SimdMultAcc 395opLat=1 396pipelined=true 397 398[system.cpu.fuPool.FUList5.opList08] 399type=OpDesc 400eventq_index=0 401opClass=SimdShift 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList5.opList09] 406type=OpDesc 407eventq_index=0 408opClass=SimdShiftAcc 409opLat=1 410pipelined=true 411 412[system.cpu.fuPool.FUList5.opList10] 413type=OpDesc 414eventq_index=0 415opClass=SimdSqrt 416opLat=1 417pipelined=true 418 419[system.cpu.fuPool.FUList5.opList11] 420type=OpDesc 421eventq_index=0 422opClass=SimdFloatAdd 423opLat=1 424pipelined=true 425 426[system.cpu.fuPool.FUList5.opList12] 427type=OpDesc 428eventq_index=0 429opClass=SimdFloatAlu 430opLat=1 431pipelined=true 432 433[system.cpu.fuPool.FUList5.opList13] 434type=OpDesc 435eventq_index=0 436opClass=SimdFloatCmp 437opLat=1 438pipelined=true 439 440[system.cpu.fuPool.FUList5.opList14] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatCvt 444opLat=1 445pipelined=true 446 447[system.cpu.fuPool.FUList5.opList15] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatDiv 451opLat=1 452pipelined=true 453 454[system.cpu.fuPool.FUList5.opList16] 455type=OpDesc 456eventq_index=0 457opClass=SimdFloatMisc 458opLat=1 459pipelined=true 460 461[system.cpu.fuPool.FUList5.opList17] 462type=OpDesc 463eventq_index=0 464opClass=SimdFloatMult 465opLat=1 466pipelined=true 467 468[system.cpu.fuPool.FUList5.opList18] 469type=OpDesc 470eventq_index=0 471opClass=SimdFloatMultAcc 472opLat=1 473pipelined=true 474 475[system.cpu.fuPool.FUList5.opList19] 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatSqrt 479opLat=1 480pipelined=true 481 482[system.cpu.fuPool.FUList6] 483type=FUDesc	358[system.cpu.fuPool.FUList5] 359type=FUDesc 360children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 361count=4 362eventq_index=0 363opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 364 365[system.cpu.fuPool.FUList5.opList00] 366type=OpDesc 367eventq_index=0 368opClass=SimdAdd 369opLat=1 370pipelined=true 371 372[system.cpu.fuPool.FUList5.opList01] 373type=OpDesc 374eventq_index=0 375opClass=SimdAddAcc 376opLat=1 377pipelined=true 378 379[system.cpu.fuPool.FUList5.opList02] 380type=OpDesc 381eventq_index=0 382opClass=SimdAlu 383opLat=1 384pipelined=true 385 386[system.cpu.fuPool.FUList5.opList03] 387type=OpDesc 388eventq_index=0 389opClass=SimdCmp 390opLat=1 391pipelined=true 392 393[system.cpu.fuPool.FUList5.opList04] 394type=OpDesc 395eventq_index=0 396opClass=SimdCvt 397opLat=1 398pipelined=true 399 400[system.cpu.fuPool.FUList5.opList05] 401type=OpDesc 402eventq_index=0 403opClass=SimdMisc 404opLat=1 405pipelined=true 406 407[system.cpu.fuPool.FUList5.opList06] 408type=OpDesc 409eventq_index=0 410opClass=SimdMult 411opLat=1 412pipelined=true 413 414[system.cpu.fuPool.FUList5.opList07] 415type=OpDesc 416eventq_index=0 417opClass=SimdMultAcc 418opLat=1 419pipelined=true 420 421[system.cpu.fuPool.FUList5.opList08] 422type=OpDesc 423eventq_index=0 424opClass=SimdShift 425opLat=1 426pipelined=true 427 428[system.cpu.fuPool.FUList5.opList09] 429type=OpDesc 430eventq_index=0 431opClass=SimdShiftAcc 432opLat=1 433pipelined=true 434 435[system.cpu.fuPool.FUList5.opList10] 436type=OpDesc 437eventq_index=0 438opClass=SimdSqrt 439opLat=1 440pipelined=true 441 442[system.cpu.fuPool.FUList5.opList11] 443type=OpDesc 444eventq_index=0 445opClass=SimdFloatAdd 446opLat=1 447pipelined=true 448 449[system.cpu.fuPool.FUList5.opList12] 450type=OpDesc 451eventq_index=0 452opClass=SimdFloatAlu 453opLat=1 454pipelined=true 455 456[system.cpu.fuPool.FUList5.opList13] 457type=OpDesc 458eventq_index=0 459opClass=SimdFloatCmp 460opLat=1 461pipelined=true 462 463[system.cpu.fuPool.FUList5.opList14] 464type=OpDesc 465eventq_index=0 466opClass=SimdFloatCvt 467opLat=1 468pipelined=true 469 470[system.cpu.fuPool.FUList5.opList15] 471type=OpDesc 472eventq_index=0 473opClass=SimdFloatDiv 474opLat=1 475pipelined=true 476 477[system.cpu.fuPool.FUList5.opList16] 478type=OpDesc 479eventq_index=0 480opClass=SimdFloatMisc 481opLat=1 482pipelined=true 483 484[system.cpu.fuPool.FUList5.opList17] 485type=OpDesc 486eventq_index=0 487opClass=SimdFloatMult 488opLat=1 489pipelined=true 490 491[system.cpu.fuPool.FUList5.opList18] 492type=OpDesc 493eventq_index=0 494opClass=SimdFloatMultAcc 495opLat=1 496pipelined=true 497 498[system.cpu.fuPool.FUList5.opList19] 499type=OpDesc 500eventq_index=0 501opClass=SimdFloatSqrt 502opLat=1 503pipelined=true 504 505[system.cpu.fuPool.FUList6] 506type=FUDesc
484children=opList	507children=opList0 opList1
485count=0 486eventq_index=0	508count=0 509eventq_index=0
487opList=system.cpu.fuPool.FUList6.opList	510opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
488	511
489[system.cpu.fuPool.FUList6.opList]	512[system.cpu.fuPool.FUList6.opList0]
490type=OpDesc 491eventq_index=0 492opClass=MemWrite 493opLat=1 494pipelined=true 495	513type=OpDesc 514eventq_index=0 515opClass=MemWrite 516opLat=1 517pipelined=true 518
	519[system.cpu.fuPool.FUList6.opList1] 520type=OpDesc 521eventq_index=0 522opClass=FloatMemWrite 523opLat=1 524pipelined=true 525
496[system.cpu.fuPool.FUList7] 497type=FUDesc	526[system.cpu.fuPool.FUList7] 527type=FUDesc
498children=opList0 opList1	528children=opList0 opList1 opList2 opList3
499count=4 500eventq_index=0	529count=4 530eventq_index=0
501opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1	531opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
502 503[system.cpu.fuPool.FUList7.opList0] 504type=OpDesc 505eventq_index=0 506opClass=MemRead 507opLat=1 508pipelined=true 509 510[system.cpu.fuPool.FUList7.opList1] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516	532 533[system.cpu.fuPool.FUList7.opList0] 534type=OpDesc 535eventq_index=0 536opClass=MemRead 537opLat=1 538pipelined=true 539 540[system.cpu.fuPool.FUList7.opList1] 541type=OpDesc 542eventq_index=0 543opClass=MemWrite 544opLat=1 545pipelined=true 546
	547[system.cpu.fuPool.FUList7.opList2] 548type=OpDesc 549eventq_index=0 550opClass=FloatMemRead 551opLat=1 552pipelined=true 553 554[system.cpu.fuPool.FUList7.opList3] 555type=OpDesc 556eventq_index=0 557opClass=FloatMemWrite 558opLat=1 559pipelined=true 560
517[system.cpu.fuPool.FUList8] 518type=FUDesc 519children=opList 520count=1 521eventq_index=0 522opList=system.cpu.fuPool.FUList8.opList 523 524[system.cpu.fuPool.FUList8.opList] 525type=OpDesc 526eventq_index=0 527opClass=IprAccess 528opLat=3 529pipelined=false 530 531[system.cpu.icache] 532type=Cache 533children=tags 534addr_ranges=0:18446744073709551615:0:0:0:0 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl	561[system.cpu.fuPool.FUList8] 562type=FUDesc 563children=opList 564count=1 565eventq_index=0 566opList=system.cpu.fuPool.FUList8.opList 567 568[system.cpu.fuPool.FUList8.opList] 569type=OpDesc 570eventq_index=0 571opClass=IprAccess 572opLat=3 573pipelined=false 574 575[system.cpu.icache] 576type=Cache 577children=tags 578addr_ranges=0:18446744073709551615:0:0:0:0 579assoc=2 580clk_domain=system.cpu_clk_domain 581clusivity=mostly_incl
	582data_latency=2
538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0	583default_p_state=UNDEFINED 584demand_mshr_reserve=1 585eventq_index=0
541hit_latency=2
542is_read_only=true 543max_miss_count=0 544mshrs=4 545p_state_clk_gate_bins=20 546p_state_clk_gate_max=1000000000000 547p_state_clk_gate_min=1000 548power_model=Null 549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=131072 554system=system	586is_read_only=true 587max_miss_count=0 588mshrs=4 589p_state_clk_gate_bins=20 590p_state_clk_gate_max=1000000000000 591p_state_clk_gate_min=1000 592power_model=Null 593prefetch_on_access=false 594prefetcher=Null 595response_latency=2 596sequential_access=false 597size=131072 598system=system
	599tag_latency=2
555tags=system.cpu.icache.tags 556tgts_per_mshr=20 557write_buffers=8 558writeback_clean=true 559cpu_side=system.cpu.icache_port 560mem_side=system.cpu.toL2Bus.slave[0] 561 562[system.cpu.icache.tags] 563type=LRU 564assoc=2 565block_size=64 566clk_domain=system.cpu_clk_domain	600tags=system.cpu.icache.tags 601tgts_per_mshr=20 602write_buffers=8 603writeback_clean=true 604cpu_side=system.cpu.icache_port 605mem_side=system.cpu.toL2Bus.slave[0] 606 607[system.cpu.icache.tags] 608type=LRU 609assoc=2 610block_size=64 611clk_domain=system.cpu_clk_domain
	612data_latency=2
567default_p_state=UNDEFINED 568eventq_index=0	613default_p_state=UNDEFINED 614eventq_index=0
569hit_latency=2
570p_state_clk_gate_bins=20 571p_state_clk_gate_max=1000000000000 572p_state_clk_gate_min=1000 573power_model=Null 574sequential_access=false 575size=131072	615p_state_clk_gate_bins=20 616p_state_clk_gate_max=1000000000000 617p_state_clk_gate_min=1000 618power_model=Null 619sequential_access=false 620size=131072
	621tag_latency=2
576 577[system.cpu.interrupts] 578type=AlphaInterrupts 579eventq_index=0 580 581[system.cpu.isa] 582type=AlphaISA 583eventq_index=0 584system=system 585 586[system.cpu.itb] 587type=AlphaTLB 588eventq_index=0 589size=48 590 591[system.cpu.l2cache] 592type=Cache 593children=tags 594addr_ranges=0:18446744073709551615:0:0:0:0 595assoc=8 596clk_domain=system.cpu_clk_domain 597clusivity=mostly_incl	622 623[system.cpu.interrupts] 624type=AlphaInterrupts 625eventq_index=0 626 627[system.cpu.isa] 628type=AlphaISA 629eventq_index=0 630system=system 631 632[system.cpu.itb] 633type=AlphaTLB 634eventq_index=0 635size=48 636 637[system.cpu.l2cache] 638type=Cache 639children=tags 640addr_ranges=0:18446744073709551615:0:0:0:0 641assoc=8 642clk_domain=system.cpu_clk_domain 643clusivity=mostly_incl
	644data_latency=20
598default_p_state=UNDEFINED 599demand_mshr_reserve=1 600eventq_index=0	645default_p_state=UNDEFINED 646demand_mshr_reserve=1 647eventq_index=0
601hit_latency=20
602is_read_only=false 603max_miss_count=0 604mshrs=20 605p_state_clk_gate_bins=20 606p_state_clk_gate_max=1000000000000 607p_state_clk_gate_min=1000 608power_model=Null 609prefetch_on_access=false 610prefetcher=Null 611response_latency=20 612sequential_access=false 613size=2097152 614system=system	648is_read_only=false 649max_miss_count=0 650mshrs=20 651p_state_clk_gate_bins=20 652p_state_clk_gate_max=1000000000000 653p_state_clk_gate_min=1000 654power_model=Null 655prefetch_on_access=false 656prefetcher=Null 657response_latency=20 658sequential_access=false 659size=2097152 660system=system
	661tag_latency=20
615tags=system.cpu.l2cache.tags 616tgts_per_mshr=12 617write_buffers=8 618writeback_clean=false 619cpu_side=system.cpu.toL2Bus.master[0] 620mem_side=system.membus.slave[1] 621 622[system.cpu.l2cache.tags] 623type=LRU 624assoc=8 625block_size=64 626clk_domain=system.cpu_clk_domain	662tags=system.cpu.l2cache.tags 663tgts_per_mshr=12 664write_buffers=8 665writeback_clean=false 666cpu_side=system.cpu.toL2Bus.master[0] 667mem_side=system.membus.slave[1] 668 669[system.cpu.l2cache.tags] 670type=LRU 671assoc=8 672block_size=64 673clk_domain=system.cpu_clk_domain
	674data_latency=20
627default_p_state=UNDEFINED 628eventq_index=0	675default_p_state=UNDEFINED 676eventq_index=0
629hit_latency=20
630p_state_clk_gate_bins=20 631p_state_clk_gate_max=1000000000000 632p_state_clk_gate_min=1000 633power_model=Null 634sequential_access=false 635size=2097152	677p_state_clk_gate_bins=20 678p_state_clk_gate_max=1000000000000 679p_state_clk_gate_min=1000 680power_model=Null 681sequential_access=false 682size=2097152
	683tag_latency=20
636 637[system.cpu.toL2Bus] 638type=CoherentXBar 639children=snoop_filter 640clk_domain=system.cpu_clk_domain 641default_p_state=UNDEFINED 642eventq_index=0 643forward_latency=0 644frontend_latency=1 645p_state_clk_gate_bins=20 646p_state_clk_gate_max=1000000000000 647p_state_clk_gate_min=1000 648point_of_coherency=false 649power_model=Null 650response_latency=1 651snoop_filter=system.cpu.toL2Bus.snoop_filter 652snoop_response_latency=1 653system=system 654use_default_range=false 655width=32 656master=system.cpu.l2cache.cpu_side 657slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 658 659[system.cpu.toL2Bus.snoop_filter] 660type=SnoopFilter 661eventq_index=0 662lookup_latency=0 663max_capacity=8388608 664system=system 665 666[system.cpu.tracer] 667type=ExeTracer 668eventq_index=0 669 670[system.cpu.workload] 671type=LiveProcess 672cmd=hello 673cwd= 674drivers= 675egid=100 676env= 677errout=cerr 678euid=100 679eventq_index=0	684 685[system.cpu.toL2Bus] 686type=CoherentXBar 687children=snoop_filter 688clk_domain=system.cpu_clk_domain 689default_p_state=UNDEFINED 690eventq_index=0 691forward_latency=0 692frontend_latency=1 693p_state_clk_gate_bins=20 694p_state_clk_gate_max=1000000000000 695p_state_clk_gate_min=1000 696point_of_coherency=false 697power_model=Null 698response_latency=1 699snoop_filter=system.cpu.toL2Bus.snoop_filter 700snoop_response_latency=1 701system=system 702use_default_range=false 703width=32 704master=system.cpu.l2cache.cpu_side 705slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 706 707[system.cpu.toL2Bus.snoop_filter] 708type=SnoopFilter 709eventq_index=0 710lookup_latency=0 711max_capacity=8388608 712system=system 713 714[system.cpu.tracer] 715type=ExeTracer 716eventq_index=0 717 718[system.cpu.workload] 719type=LiveProcess 720cmd=hello 721cwd= 722drivers= 723egid=100 724env= 725errout=cerr 726euid=100 727eventq_index=0
680executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello	728executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
681gid=100 682input=cin 683kvmInSE=false 684max_stack_size=67108864 685output=cout 686pid=100 687ppid=99 688simpoint=0 689system=system 690uid=100 691useArchPT=false 692 693[system.cpu_clk_domain] 694type=SrcClockDomain 695clock=500 696domain_id=-1 697eventq_index=0 698init_perf_level=0 699voltage_domain=system.voltage_domain 700 701[system.dvfs_handler] 702type=DVFSHandler 703domains= 704enable=false 705eventq_index=0 706sys_clk_domain=system.clk_domain 707transition_latency=100000000 708 709[system.membus] 710type=CoherentXBar 711children=snoop_filter 712clk_domain=system.clk_domain 713default_p_state=UNDEFINED 714eventq_index=0 715forward_latency=4 716frontend_latency=3 717p_state_clk_gate_bins=20 718p_state_clk_gate_max=1000000000000 719p_state_clk_gate_min=1000 720point_of_coherency=true 721power_model=Null 722response_latency=2 723snoop_filter=system.membus.snoop_filter 724snoop_response_latency=4 725system=system 726use_default_range=false 727width=16 728master=system.physmem.port 729slave=system.system_port system.cpu.l2cache.mem_side 730 731[system.membus.snoop_filter] 732type=SnoopFilter 733eventq_index=0 734lookup_latency=1 735max_capacity=8388608 736system=system 737 738[system.physmem] 739type=DRAMCtrl 740IDD0=0.055000 741IDD02=0.000000 742IDD2N=0.032000 743IDD2N2=0.000000 744IDD2P0=0.000000 745IDD2P02=0.000000 746IDD2P1=0.032000 747IDD2P12=0.000000 748IDD3N=0.038000 749IDD3N2=0.000000 750IDD3P0=0.000000 751IDD3P02=0.000000 752IDD3P1=0.038000 753IDD3P12=0.000000 754IDD4R=0.157000 755IDD4R2=0.000000 756IDD4W=0.125000 757IDD4W2=0.000000 758IDD5=0.235000 759IDD52=0.000000 760IDD6=0.020000 761IDD62=0.000000 762VDD=1.500000 763VDD2=0.000000 764activation_limit=4 765addr_mapping=RoRaBaCoCh 766bank_groups_per_rank=0 767banks_per_rank=8 768burst_length=8 769channels=1 770clk_domain=system.clk_domain 771conf_table_reported=true 772default_p_state=UNDEFINED 773device_bus_width=8 774device_rowbuffer_size=1024 775device_size=536870912 776devices_per_rank=8 777dll=true 778eventq_index=0 779in_addr_map=true 780kvm_map=true 781max_accesses_per_row=16 782mem_sched_policy=frfcfs 783min_writes_per_switch=16 784null=false 785p_state_clk_gate_bins=20 786p_state_clk_gate_max=1000000000000 787p_state_clk_gate_min=1000 788page_policy=open_adaptive 789power_model=Null 790range=0:134217727:0:0:0:0 791ranks_per_channel=2 792read_buffer_size=32 793static_backend_latency=10000 794static_frontend_latency=10000 795tBURST=5000 796tCCD_L=0 797tCK=1250 798tCL=13750 799tCS=2500 800tRAS=35000 801tRCD=13750 802tREFI=7800000 803tRFC=260000 804tRP=13750 805tRRD=6000 806tRRD_L=0 807tRTP=7500 808tRTW=2500 809tWR=15000 810tWTR=7500 811tXAW=30000 812tXP=6000 813tXPDLL=0 814tXS=270000 815tXSDLL=0 816write_buffer_size=64 817write_high_thresh_perc=85 818write_low_thresh_perc=50 819port=system.membus.master[0] 820 821[system.voltage_domain] 822type=VoltageDomain 823eventq_index=0 824voltage=1.000000 825	729gid=100 730input=cin 731kvmInSE=false 732max_stack_size=67108864 733output=cout 734pid=100 735ppid=99 736simpoint=0 737system=system 738uid=100 739useArchPT=false 740 741[system.cpu_clk_domain] 742type=SrcClockDomain 743clock=500 744domain_id=-1 745eventq_index=0 746init_perf_level=0 747voltage_domain=system.voltage_domain 748 749[system.dvfs_handler] 750type=DVFSHandler 751domains= 752enable=false 753eventq_index=0 754sys_clk_domain=system.clk_domain 755transition_latency=100000000 756 757[system.membus] 758type=CoherentXBar 759children=snoop_filter 760clk_domain=system.clk_domain 761default_p_state=UNDEFINED 762eventq_index=0 763forward_latency=4 764frontend_latency=3 765p_state_clk_gate_bins=20 766p_state_clk_gate_max=1000000000000 767p_state_clk_gate_min=1000 768point_of_coherency=true 769power_model=Null 770response_latency=2 771snoop_filter=system.membus.snoop_filter 772snoop_response_latency=4 773system=system 774use_default_range=false 775width=16 776master=system.physmem.port 777slave=system.system_port system.cpu.l2cache.mem_side 778 779[system.membus.snoop_filter] 780type=SnoopFilter 781eventq_index=0 782lookup_latency=1 783max_capacity=8388608 784system=system 785 786[system.physmem] 787type=DRAMCtrl 788IDD0=0.055000 789IDD02=0.000000 790IDD2N=0.032000 791IDD2N2=0.000000 792IDD2P0=0.000000 793IDD2P02=0.000000 794IDD2P1=0.032000 795IDD2P12=0.000000 796IDD3N=0.038000 797IDD3N2=0.000000 798IDD3P0=0.000000 799IDD3P02=0.000000 800IDD3P1=0.038000 801IDD3P12=0.000000 802IDD4R=0.157000 803IDD4R2=0.000000 804IDD4W=0.125000 805IDD4W2=0.000000 806IDD5=0.235000 807IDD52=0.000000 808IDD6=0.020000 809IDD62=0.000000 810VDD=1.500000 811VDD2=0.000000 812activation_limit=4 813addr_mapping=RoRaBaCoCh 814bank_groups_per_rank=0 815banks_per_rank=8 816burst_length=8 817channels=1 818clk_domain=system.clk_domain 819conf_table_reported=true 820default_p_state=UNDEFINED 821device_bus_width=8 822device_rowbuffer_size=1024 823device_size=536870912 824devices_per_rank=8 825dll=true 826eventq_index=0 827in_addr_map=true 828kvm_map=true 829max_accesses_per_row=16 830mem_sched_policy=frfcfs 831min_writes_per_switch=16 832null=false 833p_state_clk_gate_bins=20 834p_state_clk_gate_max=1000000000000 835p_state_clk_gate_min=1000 836page_policy=open_adaptive 837power_model=Null 838range=0:134217727:0:0:0:0 839ranks_per_channel=2 840read_buffer_size=32 841static_backend_latency=10000 842static_frontend_latency=10000 843tBURST=5000 844tCCD_L=0 845tCK=1250 846tCL=13750 847tCS=2500 848tRAS=35000 849tRCD=13750 850tREFI=7800000 851tRFC=260000 852tRP=13750 853tRRD=6000 854tRRD_L=0 855tRTP=7500 856tRTW=2500 857tWR=15000 858tWTR=7500 859tXAW=30000 860tXP=6000 861tXPDLL=0 862tXS=270000 863tXSDLL=0 864write_buffer_size=64 865write_high_thresh_perc=85 866write_low_thresh_perc=50 867port=system.membus.master[0] 868 869[system.voltage_domain] 870type=VoltageDomain 871eventq_index=0 872voltage=1.000000 873