1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 9 unchanged lines hidden (view full) ---

18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=timing
24mem_ranges=
25memories=system.physmem
26num_work_ids=16
27readfile=
28symbolfile=
29work_begin_ckpt_count=0
30work_begin_cpu_id_exit=-1
31work_begin_exit_count=0
32work_cpus_ckpt_count=0
33work_end_ckpt_count=0

--- 548 unchanged lines hidden (view full) ---

582hit_latency=20
583sequential_access=false
584size=2097152
585
586[system.cpu.toL2Bus]
587type=CoherentXBar
588clk_domain=system.cpu_clk_domain
589eventq_index=0
590header_cycles=1
591snoop_filter=Null
592system=system
593use_default_range=false
594width=32
595master=system.cpu.l2cache.cpu_side
596slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
597
598[system.cpu.tracer]
599type=ExeTracer

--- 37 unchanged lines hidden (view full) ---

637eventq_index=0
638sys_clk_domain=system.clk_domain
639transition_latency=100000000
640
641[system.membus]
642type=CoherentXBar
643clk_domain=system.clk_domain
644eventq_index=0
645header_cycles=1
646snoop_filter=Null
647system=system
648use_default_range=false
649width=8
650master=system.physmem.port
651slave=system.system_port system.cpu.l2cache.mem_side
652
653[system.physmem]
654type=DRAMCtrl
655IDD0=0.075000
656IDD02=0.000000
657IDD2N=0.050000

--- 14 unchanged lines hidden (view full) ---

672IDD4W2=0.000000
673IDD5=0.220000
674IDD52=0.000000
675IDD6=0.000000
676IDD62=0.000000
677VDD=1.500000
678VDD2=0.000000
679activation_limit=4
680addr_mapping=RoRaBaChCo
681bank_groups_per_rank=0
682banks_per_rank=8
683burst_length=8
684channels=1
685clk_domain=system.clk_domain
686conf_table_reported=true
687device_bus_width=8
688device_rowbuffer_size=1024

--- 46 unchanged lines hidden ---