Deleted Added
sdiff udiff text old ( 9276:a5ede748a1d9 ) new ( 9348:44d31345e360 )
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1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=System
11children=cpu membus physmem
12boot_osflags=a
13clock=1000
14init_param=0
15kernel=
16load_addr_mask=1099511627775
17mem_mode=atomic
18memories=system.physmem
19num_work_ids=16
20readfile=
21symbolfile=
22work_begin_ckpt_count=0
23work_begin_cpu_id_exit=-1
24work_begin_exit_count=0
25work_cpus_ckpt_count=0
26work_end_ckpt_count=0
27work_end_exit_count=0
28work_item_id=-1
29system_port=system.membus.slave[0]
30
31[system.cpu]
32type=DerivO3CPU
33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
34BTBEntries=4096
35BTBTagSize=16
36LFSTSize=1024
37LQEntries=32
38LSQCheckLoads=true
39LSQDepCheckShift=4
40RASSize=16
41SQEntries=32

--- 31 unchanged lines hidden (view full) ---

73globalHistoryBits=13
74globalPredictorSize=8192
75iewToCommitDelay=1
76iewToDecodeDelay=1
77iewToFetchDelay=1
78iewToRenameDelay=1
79instShiftAmt=2
80interrupts=system.cpu.interrupts
81isa=system.cpu.isa
82issueToExecuteDelay=1
83issueWidth=8
84itb=system.cpu.itb
85localCtrBits=2
86localHistoryBits=11
87localHistoryTableSize=2048
88localPredictorSize=2048
89max_insts_all_threads=0

--- 35 unchanged lines hidden (view full) ---

125dcache_port=system.cpu.dcache.cpu_side
126icache_port=system.cpu.icache.cpu_side
127
128[system.cpu.dcache]
129type=BaseCache
130addr_ranges=0:18446744073709551615
131assoc=2
132block_size=64
133clock=500
134forward_snoops=true
135hash_delay=1
136hit_latency=2
137is_top_level=true
138max_miss_count=0
139mshrs=4
140prefetch_on_access=false
141prefetcher=Null
142prioritizeRequests=false
143repl=Null
144response_latency=2
145size=262144
146subblock_size=0
147system=system
148tgts_per_mshr=20
149trace_addr=0
150two_queue=false
151write_buffers=8
152cpu_side=system.cpu.dcache_port

--- 266 unchanged lines hidden (view full) ---

419opClass=IprAccess
420opLat=3
421
422[system.cpu.icache]
423type=BaseCache
424addr_ranges=0:18446744073709551615
425assoc=2
426block_size=64
427clock=500
428forward_snoops=true
429hash_delay=1
430hit_latency=2
431is_top_level=true
432max_miss_count=0
433mshrs=4
434prefetch_on_access=false
435prefetcher=Null
436prioritizeRequests=false
437repl=Null
438response_latency=2
439size=131072
440subblock_size=0
441system=system
442tgts_per_mshr=20
443trace_addr=0
444two_queue=false
445write_buffers=8
446cpu_side=system.cpu.icache_port
447mem_side=system.cpu.toL2Bus.slave[0]
448
449[system.cpu.interrupts]
450type=AlphaInterrupts
451
452[system.cpu.isa]
453type=AlphaISA
454
455[system.cpu.itb]
456type=AlphaTLB
457size=48
458
459[system.cpu.l2cache]
460type=BaseCache
461addr_ranges=0:18446744073709551615
462assoc=8
463block_size=64
464clock=500
465forward_snoops=true
466hash_delay=1
467hit_latency=20
468is_top_level=false
469max_miss_count=0
470mshrs=20
471prefetch_on_access=false
472prefetcher=Null
473prioritizeRequests=false
474repl=Null
475response_latency=20
476size=2097152
477subblock_size=0
478system=system
479tgts_per_mshr=12
480trace_addr=0
481two_queue=false
482write_buffers=8
483cpu_side=system.cpu.toL2Bus.master[0]
484mem_side=system.membus.slave[1]
485
486[system.cpu.toL2Bus]
487type=CoherentBus
488block_size=64
489clock=500
490header_cycles=1
491use_default_range=false
492width=32
493master=system.cpu.l2cache.cpu_side
494slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
495
496[system.cpu.tracer]
497type=ExeTracer
498
499[system.cpu.workload]
500type=LiveProcess
501cmd=hello
502cwd=
503egid=100
504env=
505errout=cerr
506euid=100
507executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
508gid=100
509input=cin
510max_stack_size=67108864
511output=cout
512pid=100
513ppid=99
514simpoint=0
515system=system

--- 5 unchanged lines hidden (view full) ---

521clock=1000
522header_cycles=1
523use_default_range=false
524width=8
525master=system.physmem.port
526slave=system.system_port system.cpu.l2cache.mem_side
527
528[system.physmem]
529type=SimpleDRAM
530addr_mapping=openmap
531banks_per_rank=8
532clock=1000
533conf_table_reported=false
534in_addr_map=true
535lines_per_rowbuffer=64
536mem_sched_policy=fcfs
537null=false
538page_policy=open
539range=0:134217727
540ranks_per_channel=2
541read_buffer_size=32
542tBURST=4000
543tCL=14000
544tRCD=14000
545tREFI=7800000
546tRFC=300000
547tRP=14000
548tWTR=1000
549write_buffer_size=32
550write_thresh_perc=70
551zero=false
552port=system.membus.master[0]
553