1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 159 unchanged lines hidden (view full) ---

168localHistoryTableSize=2048
169localPredictorSize=2048
170numThreads=1
171useIndirect=true
172
173[system.cpu.dcache]
174type=Cache
175children=tags
176addr_ranges=0:18446744073709551615:0:0:0:0
177assoc=2
178clk_domain=system.cpu_clk_domain
179clusivity=mostly_incl
180default_p_state=UNDEFINED
181demand_mshr_reserve=1
182eventq_index=0
183hit_latency=2
184is_read_only=false

--- 341 unchanged lines hidden (view full) ---

526eventq_index=0
527opClass=IprAccess
528opLat=3
529pipelined=false
530
531[system.cpu.icache]
532type=Cache
533children=tags
534addr_ranges=0:18446744073709551615:0:0:0:0
535assoc=2
536clk_domain=system.cpu_clk_domain
537clusivity=mostly_incl
538default_p_state=UNDEFINED
539demand_mshr_reserve=1
540eventq_index=0
541hit_latency=2
542is_read_only=true

--- 43 unchanged lines hidden (view full) ---

586[system.cpu.itb]
587type=AlphaTLB
588eventq_index=0
589size=48
590
591[system.cpu.l2cache]
592type=Cache
593children=tags
594addr_ranges=0:18446744073709551615:0:0:0:0
595assoc=8
596clk_domain=system.cpu_clk_domain
597clusivity=mostly_incl
598default_p_state=UNDEFINED
599demand_mshr_reserve=1
600eventq_index=0
601hit_latency=20
602is_read_only=false

--- 100 unchanged lines hidden (view full) ---

703domains=
704enable=false
705eventq_index=0
706sys_clk_domain=system.clk_domain
707transition_latency=100000000
708
709[system.membus]
710type=CoherentXBar
711children=snoop_filter
712clk_domain=system.clk_domain
713default_p_state=UNDEFINED
714eventq_index=0
715forward_latency=4
716frontend_latency=3
717p_state_clk_gate_bins=20
718p_state_clk_gate_max=1000000000000
719p_state_clk_gate_min=1000
720point_of_coherency=true
721power_model=Null
722response_latency=2
723snoop_filter=system.membus.snoop_filter
724snoop_response_latency=4
725system=system
726use_default_range=false
727width=16
728master=system.physmem.port
729slave=system.system_port system.cpu.l2cache.mem_side
730
731[system.membus.snoop_filter]
732type=SnoopFilter
733eventq_index=0
734lookup_latency=1
735max_capacity=8388608
736system=system
737
738[system.physmem]
739type=DRAMCtrl
740IDD0=0.055000
741IDD02=0.000000
742IDD2N=0.032000
743IDD2N2=0.000000
744IDD2P0=0.000000
745IDD2P02=0.000000
746IDD2P1=0.032000
747IDD2P12=0.000000
748IDD3N=0.038000
749IDD3N2=0.000000
750IDD3P0=0.000000
751IDD3P02=0.000000
752IDD3P1=0.038000
753IDD3P12=0.000000
754IDD4R=0.157000
755IDD4R2=0.000000
756IDD4W=0.125000
757IDD4W2=0.000000
758IDD5=0.235000
759IDD52=0.000000
760IDD6=0.020000
761IDD62=0.000000
762VDD=1.500000
763VDD2=0.000000
764activation_limit=4
765addr_mapping=RoRaBaCoCh
766bank_groups_per_rank=0
767banks_per_rank=8
768burst_length=8
769channels=1
770clk_domain=system.clk_domain
771conf_table_reported=true
772default_p_state=UNDEFINED
773device_bus_width=8
774device_rowbuffer_size=1024
775device_size=536870912
776devices_per_rank=8
777dll=true
778eventq_index=0
779in_addr_map=true
780kvm_map=true
781max_accesses_per_row=16
782mem_sched_policy=frfcfs
783min_writes_per_switch=16
784null=false
785p_state_clk_gate_bins=20
786p_state_clk_gate_max=1000000000000
787p_state_clk_gate_min=1000
788page_policy=open_adaptive
789power_model=Null
790range=0:134217727:0:0:0:0
791ranks_per_channel=2
792read_buffer_size=32
793static_backend_latency=10000
794static_frontend_latency=10000
795tBURST=5000
796tCCD_L=0
797tCK=1250
798tCL=13750

--- 5 unchanged lines hidden (view full) ---

804tRP=13750
805tRRD=6000
806tRRD_L=0
807tRTP=7500
808tRTW=2500
809tWR=15000
810tWTR=7500
811tXAW=30000
812tXP=6000
813tXPDLL=0
814tXS=270000
815tXSDLL=0
816write_buffer_size=64
817write_high_thresh_perc=85
818write_low_thresh_perc=50
819port=system.membus.master[0]
820
821[system.voltage_domain]
822type=VoltageDomain
823eventq_index=0
824voltage=1.000000
825