Cross Reference: /gem5/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000041 # Number of seconds simulated
4sim_ticks 41083000 # Number of ticks simulated
5final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 217103 # Simulator instruction rate (inst/s)
8host_op_rate 217013 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1389706699 # Simulator tick rate (ticks/s)
10host_mem_usage 253264 # Number of bytes of host memory used

7host_inst_rate 202272 # Simulator instruction rate (inst/s)
8host_op_rate 202193 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1294825774 # Simulator tick rate (ticks/s)
10host_mem_usage 252636 # Number of bytes of host memory used

11host_seconds 0.03 # Real time elapsed on the host
12sim_insts 6413 # Number of instructions simulated
13sim_ops 6413 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory

--- 177 unchanged lines hidden (view full) ---

196system.physmem.bytesPerActivate::256-383 13 14.29% 62.64% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 8 8.79% 71.43% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 5 5.49% 76.92% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 4 4.40% 81.32% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation

204system.physmem.totQLat 6580250 # Total ticks spent queuing
205system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM

204system.physmem.totQLat 6584250 # Total ticks spent queuing
205system.physmem.totMemAccLat 16559250 # Total ticks spent from burst creation until serviced by the DRAM

206system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers

207system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst

207system.physmem.avgQLat 12376.41 # Average queueing delay per DRAM burst

208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

209system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst

209system.physmem.avgMemAccLat 31126.41 # Average memory access latency per DRAM burst

210system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 6.47 # Data bus utilization in percentage
216system.physmem.busUtilRead 6.47 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes

--- 24 unchanged lines hidden (view full) ---

242system.physmem_0.memoryStateTime::PRE_PDN 2418500 # Time in different power states
243system.physmem_0.memoryStateTime::ACT 7463000 # Time in different power states
244system.physmem_0.memoryStateTime::ACT_PDN 29862000 # Time in different power states
245system.physmem_1.actEnergy 421260 # Energy for activate commands per rank (pJ)
246system.physmem_1.preEnergy 208725 # Energy for precharge commands per rank (pJ)
247system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ)
248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)

250system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ)

250system.physmem_1.actBackEnergy 4023060 # Energy for active background per rank (pJ)

251system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ)

252system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ)

252system.physmem_1.actPowerDownEnergy 14292180 # Energy for active power-down per rank (pJ)

253system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ)
254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
255system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ)
256system.physmem_1.averagePower 589.365503 # Core power per rank (mW)
257system.physmem_1.totalIdleTime 31744250 # Total Idle time Per DRAM Rank
258system.physmem_1.memoryStateTime::IDLE 288500 # Time in different power states
259system.physmem_1.memoryStateTime::REF 1300000 # Time in different power states
260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
261system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states
262system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states
263system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states
264system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states

265system.cpu.branchPred.lookups 2003 # Number of BP lookups
266system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups

265system.cpu.branchPred.lookups 2002 # Number of BP lookups
266system.cpu.branchPred.condPredicted 1237 # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect 378 # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups 1602 # Number of BTB lookups

269system.cpu.branchPred.BTBHits 377 # Number of BTB hits
270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

271system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage
272system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target.

271system.cpu.branchPred.BTBHitPct 23.533084 # BTB Hit Percentage
272system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target.

273system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.

274system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses 322 # Number of indirect misses.
277system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches.

274system.cpu.branchPred.indirectLookups 333 # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits 14 # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses 319 # Number of indirect misses.
277system.cpu.branchPredindirectMispredicted 114 # Number of mispredicted indirect branches.

278system.cpu_clk_domain.clock 500 # Clock period in ticks
279system.cpu.dtb.fetch_hits 0 # ITB hits
280system.cpu.dtb.fetch_misses 0 # ITB misses
281system.cpu.dtb.fetch_acv 0 # ITB acv
282system.cpu.dtb.fetch_accesses 0 # ITB accesses
283system.cpu.dtb.read_hits 1365 # DTB read hits
284system.cpu.dtb.read_misses 11 # DTB read misses
285system.cpu.dtb.read_acv 0 # DTB read access violations
286system.cpu.dtb.read_accesses 1376 # DTB read accesses
287system.cpu.dtb.write_hits 884 # DTB write hits
288system.cpu.dtb.write_misses 3 # DTB write misses
289system.cpu.dtb.write_acv 0 # DTB write access violations
290system.cpu.dtb.write_accesses 887 # DTB write accesses
291system.cpu.dtb.data_hits 2249 # DTB hits
292system.cpu.dtb.data_misses 14 # DTB misses
293system.cpu.dtb.data_acv 0 # DTB access violations
294system.cpu.dtb.data_accesses 2263 # DTB accesses

295system.cpu.itb.fetch_hits 2686 # ITB hits

295system.cpu.itb.fetch_hits 2685 # ITB hits

296system.cpu.itb.fetch_misses 17 # ITB misses
297system.cpu.itb.fetch_acv 0 # ITB acv

298system.cpu.itb.fetch_accesses 2703 # ITB accesses

298system.cpu.itb.fetch_accesses 2702 # ITB accesses

299system.cpu.itb.read_hits 0 # DTB read hits
300system.cpu.itb.read_misses 0 # DTB read misses
301system.cpu.itb.read_acv 0 # DTB read access violations
302system.cpu.itb.read_accesses 0 # DTB read accesses
303system.cpu.itb.write_hits 0 # DTB write hits
304system.cpu.itb.write_misses 0 # DTB write misses
305system.cpu.itb.write_acv 0 # DTB write access violations
306system.cpu.itb.write_accesses 0 # DTB write accesses
307system.cpu.itb.data_hits 0 # DTB hits
308system.cpu.itb.data_misses 0 # DTB misses
309system.cpu.itb.data_acv 0 # DTB access violations
310system.cpu.itb.data_accesses 0 # DTB accesses
311system.cpu.workload.num_syscalls 17 # Number of system calls
312system.cpu.pwrStateResidencyTicks::ON 41083000 # Cumulative time (in ticks) in various power states
313system.cpu.numCycles 82166 # number of cpu cycles simulated
314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
316system.cpu.committedInsts 6413 # Number of instructions committed
317system.cpu.committedOps 6413 # Number of ops (including micro ops) committed

318system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit

318system.cpu.discardedOps 1093 # Number of ops (including micro ops) which were discarded before commit

319system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
320system.cpu.cpi 12.812412 # CPI: cycles per instruction
321system.cpu.ipc 0.078049 # IPC: instructions per cycle
322system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
323system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction
324system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction
325system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction
326system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction

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353system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction
354system.cpu.op_class_0::MemRead 1191 18.57% 86.45% # Class of committed instruction
355system.cpu.op_class_0::MemWrite 861 13.43% 99.88% # Class of committed instruction
356system.cpu.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
357system.cpu.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
358system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
359system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
360system.cpu.op_class_0::total 6413 # Class of committed instruction

361system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked
362system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped

361system.cpu.tickCycles 12637 # Number of cycles that the object actually ticked
362system.cpu.idleCycles 69529 # Total number of cycles that the object has spent stopped

363system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
364system.cpu.dcache.tags.replacements 0 # number of replacements

365system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use

365system.cpu.dcache.tags.tagsinuse 103.987673 # Cycle average of tags in use

366system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks.
367system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
368system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks.
369system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

370system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor
371system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy
372system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy

370system.cpu.dcache.tags.occ_blocks::cpu.data 103.987673 # Average occupied blocks per requestor
371system.cpu.dcache.tags.occ_percent::cpu.data 0.025388 # Average percentage of cache occupancy
372system.cpu.dcache.tags.occ_percent::total 0.025388 # Average percentage of cache occupancy

373system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
374system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
375system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
376system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
377system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses
378system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses
379system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
380system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits

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390system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses
391system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
392system.cpu.dcache.demand_misses::cpu.data 221 # number of demand (read+write) misses
393system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses
394system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses
395system.cpu.dcache.overall_misses::total 221 # number of overall misses
396system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles
397system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles

398system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles
399system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles
400system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles
401system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles
402system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles
403system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles

398system.cpu.dcache.WriteReq_miss_latency::cpu.data 10428500 # number of WriteReq miss cycles
399system.cpu.dcache.WriteReq_miss_latency::total 10428500 # number of WriteReq miss cycles
400system.cpu.dcache.demand_miss_latency::cpu.data 18974000 # number of demand (read+write) miss cycles
401system.cpu.dcache.demand_miss_latency::total 18974000 # number of demand (read+write) miss cycles
402system.cpu.dcache.overall_miss_latency::cpu.data 18974000 # number of overall miss cycles
403system.cpu.dcache.overall_miss_latency::total 18974000 # number of overall miss cycles

404system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses)
405system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses)
406system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
407system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
408system.cpu.dcache.demand_accesses::cpu.data 2211 # number of demand (read+write) accesses
409system.cpu.dcache.demand_accesses::total 2211 # number of demand (read+write) accesses
410system.cpu.dcache.overall_accesses::cpu.data 2211 # number of overall (read+write) accesses
411system.cpu.dcache.overall_accesses::total 2211 # number of overall (read+write) accesses
412system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071322 # miss rate for ReadReq accesses
413system.cpu.dcache.ReadReq_miss_rate::total 0.071322 # miss rate for ReadReq accesses
414system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses
415system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
416system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 # miss rate for demand accesses
417system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses
418system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses
419system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses
420system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency
421system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency

422system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency
423system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency
424system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
425system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency
426system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
427system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency

422system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83428 # average WriteReq miss latency
423system.cpu.dcache.WriteReq_avg_miss_latency::total 83428 # average WriteReq miss latency
424system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
425system.cpu.dcache.demand_avg_miss_latency::total 85855.203620 # average overall miss latency
426system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
427system.cpu.dcache.overall_avg_miss_latency::total 85855.203620 # average overall miss latency

428system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
429system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
430system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
431system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
432system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
433system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
434system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits
435system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits

--- 6 unchanged lines hidden (view full) ---

442system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
443system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
444system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses
445system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
446system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
447system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
448system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles
449system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles

450system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles
451system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles
452system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles
453system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles
454system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles
455system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles

450system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089000 # number of WriteReq MSHR miss cycles
451system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089000 # number of WriteReq MSHR miss cycles
452system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14538500 # number of demand (read+write) MSHR miss cycles
453system.cpu.dcache.demand_mshr_miss_latency::total 14538500 # number of demand (read+write) MSHR miss cycles
454system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14538500 # number of overall MSHR miss cycles
455system.cpu.dcache.overall_mshr_miss_latency::total 14538500 # number of overall MSHR miss cycles

456system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses
457system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses
458system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
459system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
460system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for demand accesses
461system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses
462system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses
463system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses
464system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency
465system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency

466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency
467system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency
468system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
469system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency
470system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
471system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency

466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904 # average WriteReq mshr miss latency
467system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904 # average WriteReq mshr miss latency
468system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
469system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency
470system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
471system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency

472system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
473system.cpu.icache.tags.replacements 0 # number of replacements

474system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use
475system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks.

474system.cpu.icache.tags.tagsinuse 175.158440 # Cycle average of tags in use
475system.cpu.icache.tags.total_refs 2321 # Total number of references to valid blocks.

476system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks.

477system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks.

477system.cpu.icache.tags.avg_refs 6.376374 # Average number of references to valid blocks.

478system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

479system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor
480system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy
481system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy

479system.cpu.icache.tags.occ_blocks::cpu.inst 175.158440 # Average occupied blocks per requestor
480system.cpu.icache.tags.occ_percent::cpu.inst 0.085527 # Average percentage of cache occupancy
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487system.cpu.icache.tags.data_accesses 5736 # Number of data accesses

486system.cpu.icache.tags.tag_accesses 5734 # Number of tag accesses
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494system.cpu.icache.overall_hits::total 2322 # number of overall hits

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490system.cpu.icache.ReadReq_hits::total 2321 # number of ReadReq hits
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494system.cpu.icache.overall_hits::total 2321 # number of overall hits

495system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
496system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
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499system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
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504system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles
505system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles
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523system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency
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504system.cpu.icache.demand_miss_latency::total 30321500 # number of demand (read+write) miss cycles
505system.cpu.icache.overall_miss_latency::cpu.inst 30321500 # number of overall miss cycles
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508system.cpu.icache.ReadReq_accesses::total 2685 # number of ReadReq accesses(hits+misses)
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510system.cpu.icache.demand_accesses::total 2685 # number of demand (read+write) accesses
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523system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency
524system.cpu.icache.overall_avg_miss_latency::total 83300.824176 # average overall miss latency

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530system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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536system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses

537system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles
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539system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles
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541system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles
542system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles
543system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses
544system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses
545system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses
546system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses
547system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses
548system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses
549system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency
550system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency
551system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
552system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency
553system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
554system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency

537system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29957500 # number of ReadReq MSHR miss cycles
538system.cpu.icache.ReadReq_mshr_miss_latency::total 29957500 # number of ReadReq MSHR miss cycles
539system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29957500 # number of demand (read+write) MSHR miss cycles
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541system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29957500 # number of overall MSHR miss cycles
542system.cpu.icache.overall_mshr_miss_latency::total 29957500 # number of overall MSHR miss cycles
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545system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for demand accesses
546system.cpu.icache.demand_mshr_miss_rate::total 0.135568 # mshr miss rate for demand accesses
547system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for overall accesses
548system.cpu.icache.overall_mshr_miss_rate::total 0.135568 # mshr miss rate for overall accesses
549system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176 # average ReadReq mshr miss latency
550system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176 # average ReadReq mshr miss latency
551system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
552system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency
553system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
554system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency

555system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
556system.cpu.l2cache.tags.replacements 0 # number of replacements

557system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use

557system.cpu.l2cache.tags.tagsinuse 279.188916 # Cycle average of tags in use

558system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
559system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks.
560system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks.
561system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

562system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor
563system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor

562system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.158050 # Average occupied blocks per requestor
563system.cpu.l2cache.tags.occ_blocks::cpu.data 104.030866 # Average occupied blocks per requestor

564system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy
565system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy
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567system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id
568system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
569system.cpu.l2cache.tags.age_task_id_blocks_1024::1 422 # Occupied blocks per task id
570system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id
571system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses

--- 12 unchanged lines hidden (view full) ---

584system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses
585system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses
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589system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
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598system.cpu.l2cache.demand_miss_latency::cpu.inst 29400000 # number of demand (read+write) miss cycles
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602system.cpu.l2cache.overall_miss_latency::cpu.data 14283500 # number of overall miss cycles
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604system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
605system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
606system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses)
607system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses)
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--- 8 unchanged lines hidden (view full) ---

620system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
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628system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency
629system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency
630system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency
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632system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency
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637system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency
638system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency
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637system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency
638system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency
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645system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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653system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses
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655system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
656system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
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661system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles

658system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5249500 # number of ReadExReq MSHR miss cycles
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661system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25770000 # number of ReadCleanReq MSHR miss cycles

662system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles
663system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles

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669system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles

664system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25770000 # number of demand (read+write) MSHR miss cycles
665system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12593500 # number of demand (read+write) MSHR miss cycles
666system.cpu.l2cache.demand_mshr_miss_latency::total 38363500 # number of demand (read+write) MSHR miss cycles
667system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25770000 # number of overall MSHR miss cycles
668system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12593500 # number of overall MSHR miss cycles
669system.cpu.l2cache.overall_mshr_miss_latency::total 38363500 # number of overall MSHR miss cycles

670system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
671system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
672system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses
673system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses
674system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
675system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
676system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses
677system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
678system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses
679system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses
680system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
681system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses

682system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency
683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency
684system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency
685system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency

682system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904 # average ReadExReq mshr miss latency
683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904 # average ReadExReq mshr miss latency
684system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537 # average ReadCleanReq mshr miss latency
685system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537 # average ReadCleanReq mshr miss latency

686system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency
687system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency

688system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
689system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
690system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency
691system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
692system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
693system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency

688system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
689system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
690system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency
691system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
692system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
693system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency

694system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter.
695system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
696system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
697system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
698system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
699system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
700system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
701system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution

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750system.membus.snoop_fanout::stdev 0 # Request fanout histogram
751system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
752system.membus.snoop_fanout::0 532 100.00% 100.00% # Request fanout histogram
753system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
754system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
755system.membus.snoop_fanout::min_value 0 # Request fanout histogram
756system.membus.snoop_fanout::max_value 0 # Request fanout histogram
757system.membus.snoop_fanout::total 532 # Request fanout histogram

758system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks)

758system.membus.reqLayer0.occupancy 607000 # Layer occupancy (ticks)