| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000038 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000038 # Number of seconds simulated |
| 4sim_ticks 37822000 # Number of ticks simulated 5final_tick 37822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 38282000 # Number of ticks simulated 5final_tick 38282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 100508 # Simulator instruction rate (inst/s) 8host_op_rate 100471 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 592356577 # Simulator tick rate (ticks/s) 10host_mem_usage 249008 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 159466 # Simulator instruction rate (inst/s) 8host_op_rate 159415 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 951356890 # Simulator tick rate (ticks/s) 10host_mem_usage 253388 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host |
| 12sim_insts 6413 # Number of instructions simulated 13sim_ops 6413 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 6413 # Number of instructions simulated 13sim_ops 6413 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 19system.physmem.bytes_read::total 34048 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 532 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 19system.physmem.bytes_read::total 34048 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 532 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 614245677 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 285971128 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 900216805 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 614245677 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 614245677 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 614245677 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 285971128 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 900216805 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 606864845 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 282534873 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 889399718 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 606864845 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 606864845 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 606864845 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 282534873 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 889399718 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 532 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 532 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 37718000 # Total gap between requests | 79system.physmem.totGap 38177000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 532 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 532 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 385.560976 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 252.880176 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 333.081835 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 17 20.73% 20.73% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 21 25.61% 46.34% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 9 10.98% 57.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 11 13.41% 70.73% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 4 4.88% 75.61% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 3.66% 79.27% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 3 3.66% 82.93% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 5 6.10% 89.02% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 10.98% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation 204system.physmem.totQLat 3215000 # Total ticks spent queuing 205system.physmem.totMemAccLat 13190000 # Total ticks spent from burst creation until serviced by the DRAM | 190system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 377.831325 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 247.256857 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 329.629090 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 20 24.10% 45.78% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 11 13.25% 59.04% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 11 13.25% 72.29% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 3 3.61% 75.90% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 4 4.82% 80.72% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 3 3.61% 84.34% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 4 4.82% 89.16% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 10.84% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation 204system.physmem.totQLat 3252000 # Total ticks spent queuing 205system.physmem.totMemAccLat 13227000 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 6043.23 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 6112.78 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 24793.23 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 900.22 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 24862.78 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 889.40 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 900.22 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 889.40 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 7.03 # Data bus utilization in percentage 216system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 6.95 # Data bus utilization in percentage 216system.physmem.busUtilRead 6.95 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 438 # Number of row buffer hits during reads | 220system.physmem.readRowHits 437 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 70898.50 # Average gap between requests 225system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined | 224system.physmem.avgGap 71761.28 # Average gap between requests 225system.physmem.pageHitRate 82.14 # Row buffer hit rate, read and write combined |
| 226system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) | 226system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) |
| 228system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) | 228system.physmem_0.readEnergy 2020200 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) 234system.physmem_0.averagePower 825.080242 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 366250 # Time in different power states | 231system.physmem_0.actBackEnergy 21270690 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 184500 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 25871865 # Total energy per rank (pJ) 234system.physmem_0.averagePower 823.813565 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 196750 # Time in different power states |
| 236system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 236system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT 30182000 # Time in different power states |
| 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 240system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) | 240system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 1505400 # Energy for read commands per rank (pJ) |
| 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 244system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) | 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 244system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) |
| 245system.physmem_1.actBackEnergy 20148930 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 1168500 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 25398495 # Total energy per rank (pJ) 248system.physmem_1.averagePower 808.740487 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 1794750 # Time in different power states | 245system.physmem_1.actBackEnergy 20078820 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 1230000 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 25385970 # Total energy per rank (pJ) 248system.physmem_1.averagePower 808.341665 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 2146500 # Time in different power states |
| 250system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 250system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT 28584000 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT 28481000 # Time in different power states |
| 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 254system.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 255system.cpu.branchPred.lookups 2005 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1239 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 1607 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 377 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 23.459863 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target. --- 31 unchanged lines hidden (view full) --- 294system.cpu.itb.write_misses 0 # DTB write misses 295system.cpu.itb.write_acv 0 # DTB write access violations 296system.cpu.itb.write_accesses 0 # DTB write accesses 297system.cpu.itb.data_hits 0 # DTB hits 298system.cpu.itb.data_misses 0 # DTB misses 299system.cpu.itb.data_acv 0 # DTB access violations 300system.cpu.itb.data_accesses 0 # DTB accesses 301system.cpu.workload.num_syscalls 17 # Number of system calls | 255system.cpu.branchPred.lookups 2005 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1239 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 1607 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 377 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 23.459863 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target. --- 31 unchanged lines hidden (view full) --- 294system.cpu.itb.write_misses 0 # DTB write misses 295system.cpu.itb.write_acv 0 # DTB write access violations 296system.cpu.itb.write_accesses 0 # DTB write accesses 297system.cpu.itb.data_hits 0 # DTB hits 298system.cpu.itb.data_misses 0 # DTB misses 299system.cpu.itb.data_acv 0 # DTB access violations 300system.cpu.itb.data_accesses 0 # DTB accesses 301system.cpu.workload.num_syscalls 17 # Number of system calls |
| 302system.cpu.pwrStateResidencyTicks::ON 37822000 # Cumulative time (in ticks) in various power states 303system.cpu.numCycles 75644 # number of cpu cycles simulated | 302system.cpu.pwrStateResidencyTicks::ON 38282000 # Cumulative time (in ticks) in various power states 303system.cpu.numCycles 76564 # number of cpu cycles simulated |
| 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 306system.cpu.committedInsts 6413 # Number of instructions committed 307system.cpu.committedOps 6413 # Number of ops (including micro ops) committed 308system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit 309system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 306system.cpu.committedInsts 6413 # Number of instructions committed 307system.cpu.committedOps 6413 # Number of ops (including micro ops) committed 308system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit 309system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 310system.cpu.cpi 11.795416 # CPI: cycles per instruction 311system.cpu.ipc 0.084779 # IPC: instructions per cycle | 310system.cpu.cpi 11.938874 # CPI: cycles per instruction 311system.cpu.ipc 0.083760 # IPC: instructions per cycle |
| 312system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 313system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction 314system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction 315system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction 316system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction 317system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction 318system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction 319system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction --- 20 unchanged lines hidden (view full) --- 340system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction 341system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction 342system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction 343system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 6413 # Class of committed instruction 347system.cpu.tickCycles 12651 # Number of cycles that the object actually ticked | 312system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 313system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction 314system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction 315system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction 316system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction 317system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction 318system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction 319system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction --- 20 unchanged lines hidden (view full) --- 340system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction 341system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction 342system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction 343system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 6413 # Class of committed instruction 347system.cpu.tickCycles 12651 # Number of cycles that the object actually ticked |
| 348system.cpu.idleCycles 62993 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 348system.cpu.idleCycles 63913 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 350system.cpu.dcache.tags.replacements 0 # number of replacements | 350system.cpu.dcache.tags.replacements 0 # number of replacements |
| 351system.cpu.dcache.tags.tagsinuse 103.701168 # Cycle average of tags in use | 351system.cpu.dcache.tags.tagsinuse 103.736314 # Cycle average of tags in use |
| 352system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. 353system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 354system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 352system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. 353system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 354system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 356system.cpu.dcache.tags.occ_blocks::cpu.data 103.701168 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.025318 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.025318 # Average percentage of cache occupancy | 356system.cpu.dcache.tags.occ_blocks::cpu.data 103.736314 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.025326 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.025326 # Average percentage of cache occupancy |
| 359system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id 362system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 363system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses 364system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses | 359system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id 362system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 363system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses 364system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses |
| 365system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 365system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 366system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits 367system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits 368system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits 369system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 370system.cpu.dcache.demand_hits::cpu.data 1990 # number of demand (read+write) hits 371system.cpu.dcache.demand_hits::total 1990 # number of demand (read+write) hits 372system.cpu.dcache.overall_hits::cpu.data 1990 # number of overall hits 373system.cpu.dcache.overall_hits::total 1990 # number of overall hits 374system.cpu.dcache.ReadReq_misses::cpu.data 96 # number of ReadReq misses 375system.cpu.dcache.ReadReq_misses::total 96 # number of ReadReq misses 376system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses 377system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 378system.cpu.dcache.demand_misses::cpu.data 221 # number of demand (read+write) misses 379system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses 380system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses 381system.cpu.dcache.overall_misses::total 221 # number of overall misses | 366system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits 367system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits 368system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits 369system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 370system.cpu.dcache.demand_hits::cpu.data 1990 # number of demand (read+write) hits 371system.cpu.dcache.demand_hits::total 1990 # number of demand (read+write) hits 372system.cpu.dcache.overall_hits::cpu.data 1990 # number of overall hits 373system.cpu.dcache.overall_hits::total 1990 # number of overall hits 374system.cpu.dcache.ReadReq_misses::cpu.data 96 # number of ReadReq misses 375system.cpu.dcache.ReadReq_misses::total 96 # number of ReadReq misses 376system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses 377system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 378system.cpu.dcache.demand_misses::cpu.data 221 # number of demand (read+write) misses 379system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses 380system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses 381system.cpu.dcache.overall_misses::total 221 # number of overall misses |
| 382system.cpu.dcache.ReadReq_miss_latency::cpu.data 7590000 # number of ReadReq miss cycles 383system.cpu.dcache.ReadReq_miss_latency::total 7590000 # number of ReadReq miss cycles 384system.cpu.dcache.WriteReq_miss_latency::cpu.data 9158000 # number of WriteReq miss cycles 385system.cpu.dcache.WriteReq_miss_latency::total 9158000 # number of WriteReq miss cycles 386system.cpu.dcache.demand_miss_latency::cpu.data 16748000 # number of demand (read+write) miss cycles 387system.cpu.dcache.demand_miss_latency::total 16748000 # number of demand (read+write) miss cycles 388system.cpu.dcache.overall_miss_latency::cpu.data 16748000 # number of overall miss cycles 389system.cpu.dcache.overall_miss_latency::total 16748000 # number of overall miss cycles | 382system.cpu.dcache.ReadReq_miss_latency::cpu.data 7713000 # number of ReadReq miss cycles 383system.cpu.dcache.ReadReq_miss_latency::total 7713000 # number of ReadReq miss cycles 384system.cpu.dcache.WriteReq_miss_latency::cpu.data 9281000 # number of WriteReq miss cycles 385system.cpu.dcache.WriteReq_miss_latency::total 9281000 # number of WriteReq miss cycles 386system.cpu.dcache.demand_miss_latency::cpu.data 16994000 # number of demand (read+write) miss cycles 387system.cpu.dcache.demand_miss_latency::total 16994000 # number of demand (read+write) miss cycles 388system.cpu.dcache.overall_miss_latency::cpu.data 16994000 # number of overall miss cycles 389system.cpu.dcache.overall_miss_latency::total 16994000 # number of overall miss cycles |
| 390system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) 391system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 393system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.demand_accesses::cpu.data 2211 # number of demand (read+write) accesses 395system.cpu.dcache.demand_accesses::total 2211 # number of demand (read+write) accesses 396system.cpu.dcache.overall_accesses::cpu.data 2211 # number of overall (read+write) accesses 397system.cpu.dcache.overall_accesses::total 2211 # number of overall (read+write) accesses 398system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071322 # miss rate for ReadReq accesses 399system.cpu.dcache.ReadReq_miss_rate::total 0.071322 # miss rate for ReadReq accesses 400system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses 401system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 402system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 # miss rate for demand accesses 403system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses 404system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses 405system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses | 390system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) 391system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 393system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.demand_accesses::cpu.data 2211 # number of demand (read+write) accesses 395system.cpu.dcache.demand_accesses::total 2211 # number of demand (read+write) accesses 396system.cpu.dcache.overall_accesses::cpu.data 2211 # number of overall (read+write) accesses 397system.cpu.dcache.overall_accesses::total 2211 # number of overall (read+write) accesses 398system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071322 # miss rate for ReadReq accesses 399system.cpu.dcache.ReadReq_miss_rate::total 0.071322 # miss rate for ReadReq accesses 400system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses 401system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 402system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 # miss rate for demand accesses 403system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses 404system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses 405system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses |
| 406system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79062.500000 # average ReadReq miss latency 407system.cpu.dcache.ReadReq_avg_miss_latency::total 79062.500000 # average ReadReq miss latency 408system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73264 # average WriteReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::total 73264 # average WriteReq miss latency 410system.cpu.dcache.demand_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency 411system.cpu.dcache.demand_avg_miss_latency::total 75782.805430 # average overall miss latency 412system.cpu.dcache.overall_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::total 75782.805430 # average overall miss latency | 406system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80343.750000 # average ReadReq miss latency 407system.cpu.dcache.ReadReq_avg_miss_latency::total 80343.750000 # average ReadReq miss latency 408system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74248 # average WriteReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::total 74248 # average WriteReq miss latency 410system.cpu.dcache.demand_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency 411system.cpu.dcache.demand_avg_miss_latency::total 76895.927602 # average overall miss latency 412system.cpu.dcache.overall_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::total 76895.927602 # average overall miss latency |
| 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 420system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits 421system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits --- 4 unchanged lines hidden (view full) --- 426system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses 427system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 428system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 429system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 430system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 431system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 432system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 433system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses | 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 420system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits 421system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits --- 4 unchanged lines hidden (view full) --- 426system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses 427system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 428system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 429system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 430system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 431system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 432system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 433system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses |
| 434system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7494000 # number of ReadReq MSHR miss cycles 435system.cpu.dcache.ReadReq_mshr_miss_latency::total 7494000 # number of ReadReq MSHR miss cycles 436system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5379500 # number of WriteReq MSHR miss cycles 437system.cpu.dcache.WriteReq_mshr_miss_latency::total 5379500 # number of WriteReq MSHR miss cycles 438system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12873500 # number of demand (read+write) MSHR miss cycles 439system.cpu.dcache.demand_mshr_miss_latency::total 12873500 # number of demand (read+write) MSHR miss cycles 440system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12873500 # number of overall MSHR miss cycles 441system.cpu.dcache.overall_mshr_miss_latency::total 12873500 # number of overall MSHR miss cycles | 434system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7617000 # number of ReadReq MSHR miss cycles 435system.cpu.dcache.ReadReq_mshr_miss_latency::total 7617000 # number of ReadReq MSHR miss cycles 436system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5452500 # number of WriteReq MSHR miss cycles 437system.cpu.dcache.WriteReq_mshr_miss_latency::total 5452500 # number of WriteReq MSHR miss cycles 438system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13069500 # number of demand (read+write) MSHR miss cycles 439system.cpu.dcache.demand_mshr_miss_latency::total 13069500 # number of demand (read+write) MSHR miss cycles 440system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13069500 # number of overall MSHR miss cycles 441system.cpu.dcache.overall_mshr_miss_latency::total 13069500 # number of overall MSHR miss cycles |
| 442system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses 443system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses 444system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 445system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 446system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for demand accesses 447system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses 448system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses 449system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses | 442system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses 443system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses 444system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 445system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 446system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for demand accesses 447system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses 448system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses 449system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses |
| 450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78062.500000 # average ReadReq mshr miss latency 451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78062.500000 # average ReadReq mshr miss latency 452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73691.780822 # average WriteReq mshr miss latency 453system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73691.780822 # average WriteReq mshr miss latency 454system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency 455system.cpu.dcache.demand_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency 456system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency 457system.cpu.dcache.overall_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency 458system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average ReadReq mshr miss latency 451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79343.750000 # average ReadReq mshr miss latency 452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74691.780822 # average WriteReq mshr miss latency 453system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74691.780822 # average WriteReq mshr miss latency 454system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency 455system.cpu.dcache.demand_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency 456system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency 457system.cpu.dcache.overall_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency 458system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 459system.cpu.icache.tags.replacements 0 # number of replacements | 459system.cpu.icache.tags.replacements 0 # number of replacements |
| 460system.cpu.icache.tags.tagsinuse 174.485780 # Cycle average of tags in use | 460system.cpu.icache.tags.tagsinuse 174.445567 # Cycle average of tags in use |
| 461system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. 462system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. 463system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. 464system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 461system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. 462system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. 463system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. 464system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 465system.cpu.icache.tags.occ_blocks::cpu.inst 174.485780 # Average occupied blocks per requestor 466system.cpu.icache.tags.occ_percent::cpu.inst 0.085198 # Average percentage of cache occupancy 467system.cpu.icache.tags.occ_percent::total 0.085198 # Average percentage of cache occupancy | 465system.cpu.icache.tags.occ_blocks::cpu.inst 174.445567 # Average occupied blocks per requestor 466system.cpu.icache.tags.occ_percent::cpu.inst 0.085178 # Average percentage of cache occupancy 467system.cpu.icache.tags.occ_percent::total 0.085178 # Average percentage of cache occupancy |
| 468system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id | 468system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id |
| 469system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 470system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id | 469system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 470system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id |
| 471system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id 472system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses 473system.cpu.icache.tags.data_accesses 5736 # Number of data accesses | 471system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id 472system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses 473system.cpu.icache.tags.data_accesses 5736 # Number of data accesses |
| 474system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 474system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 475system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits 476system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits 477system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits 478system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits 479system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits 480system.cpu.icache.overall_hits::total 2322 # number of overall hits 481system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 482system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 483system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 484system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 485system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 486system.cpu.icache.overall_misses::total 364 # number of overall misses | 475system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits 476system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits 477system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits 478system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits 479system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits 480system.cpu.icache.overall_hits::total 2322 # number of overall hits 481system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 482system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 483system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 484system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 485system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 486system.cpu.icache.overall_misses::total 364 # number of overall misses |
| 487system.cpu.icache.ReadReq_miss_latency::cpu.inst 28087500 # number of ReadReq miss cycles 488system.cpu.icache.ReadReq_miss_latency::total 28087500 # number of ReadReq miss cycles 489system.cpu.icache.demand_miss_latency::cpu.inst 28087500 # number of demand (read+write) miss cycles 490system.cpu.icache.demand_miss_latency::total 28087500 # number of demand (read+write) miss cycles 491system.cpu.icache.overall_miss_latency::cpu.inst 28087500 # number of overall miss cycles 492system.cpu.icache.overall_miss_latency::total 28087500 # number of overall miss cycles | 487system.cpu.icache.ReadReq_miss_latency::cpu.inst 28460500 # number of ReadReq miss cycles 488system.cpu.icache.ReadReq_miss_latency::total 28460500 # number of ReadReq miss cycles 489system.cpu.icache.demand_miss_latency::cpu.inst 28460500 # number of demand (read+write) miss cycles 490system.cpu.icache.demand_miss_latency::total 28460500 # number of demand (read+write) miss cycles 491system.cpu.icache.overall_miss_latency::cpu.inst 28460500 # number of overall miss cycles 492system.cpu.icache.overall_miss_latency::total 28460500 # number of overall miss cycles |
| 493system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) 494system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) 495system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses 496system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses 497system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses 498system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses 499system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses 500system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses 501system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses 502system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses 503system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses 504system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses | 493system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) 494system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) 495system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses 496system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses 497system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses 498system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses 499system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses 500system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses 501system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses 502system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses 503system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses 504system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses |
| 505system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77163.461538 # average ReadReq miss latency 506system.cpu.icache.ReadReq_avg_miss_latency::total 77163.461538 # average ReadReq miss latency 507system.cpu.icache.demand_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency 508system.cpu.icache.demand_avg_miss_latency::total 77163.461538 # average overall miss latency 509system.cpu.icache.overall_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency 510system.cpu.icache.overall_avg_miss_latency::total 77163.461538 # average overall miss latency | 505system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78188.186813 # average ReadReq miss latency 506system.cpu.icache.ReadReq_avg_miss_latency::total 78188.186813 # average ReadReq miss latency 507system.cpu.icache.demand_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency 508system.cpu.icache.demand_avg_miss_latency::total 78188.186813 # average overall miss latency 509system.cpu.icache.overall_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency 510system.cpu.icache.overall_avg_miss_latency::total 78188.186813 # average overall miss latency |
| 511system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 512system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 513system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 514system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 515system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 516system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 517system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses 518system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses 519system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses 520system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 521system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses 522system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses | 511system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 512system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 513system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 514system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 515system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 516system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 517system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses 518system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses 519system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses 520system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 521system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses 522system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses |
| 523system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27723500 # number of ReadReq MSHR miss cycles 524system.cpu.icache.ReadReq_mshr_miss_latency::total 27723500 # number of ReadReq MSHR miss cycles 525system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27723500 # number of demand (read+write) MSHR miss cycles 526system.cpu.icache.demand_mshr_miss_latency::total 27723500 # number of demand (read+write) MSHR miss cycles 527system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27723500 # number of overall MSHR miss cycles 528system.cpu.icache.overall_mshr_miss_latency::total 27723500 # number of overall MSHR miss cycles | 523system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28096500 # number of ReadReq MSHR miss cycles 524system.cpu.icache.ReadReq_mshr_miss_latency::total 28096500 # number of ReadReq MSHR miss cycles 525system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28096500 # number of demand (read+write) MSHR miss cycles 526system.cpu.icache.demand_mshr_miss_latency::total 28096500 # number of demand (read+write) MSHR miss cycles 527system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28096500 # number of overall MSHR miss cycles 528system.cpu.icache.overall_mshr_miss_latency::total 28096500 # number of overall MSHR miss cycles |
| 529system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses 530system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses 531system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses 532system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses 533system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses 534system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses | 529system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses 530system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses 531system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses 532system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses 533system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses 534system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses |
| 535system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76163.461538 # average ReadReq mshr miss latency 536system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76163.461538 # average ReadReq mshr miss latency 537system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency 539system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency 541system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 535system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77188.186813 # average ReadReq mshr miss latency 536system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77188.186813 # average ReadReq mshr miss latency 537system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency 539system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency 541system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 542system.cpu.l2cache.tags.replacements 0 # number of replacements | 542system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 543system.cpu.l2cache.tags.tagsinuse 232.271171 # Cycle average of tags in use | 543system.cpu.l2cache.tags.tagsinuse 278.242026 # Cycle average of tags in use |
| 544system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. | 544system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. |
| 545system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks. 546system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks. | 545system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. 546system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. |
| 547system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 547system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 548system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.500375 # Average occupied blocks per requestor 549system.cpu.l2cache.tags.occ_blocks::cpu.data 57.770796 # Average occupied blocks per requestor 550system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005325 # Average percentage of cache occupancy 551system.cpu.l2cache.tags.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy 552system.cpu.l2cache.tags.occ_percent::total 0.007088 # Average percentage of cache occupancy 553system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id 554system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 555system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 556system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id | 548system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.459359 # Average occupied blocks per requestor 549system.cpu.l2cache.tags.occ_blocks::cpu.data 103.782667 # Average occupied blocks per requestor 550system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005324 # Average percentage of cache occupancy 551system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy 552system.cpu.l2cache.tags.occ_percent::total 0.008491 # Average percentage of cache occupancy 553system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id 554system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 555system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id 556system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id |
| 557system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses 558system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses | 557system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses 558system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses |
| 559system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 559system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 560system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 561system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 562system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 563system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 564system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 565system.cpu.l2cache.overall_hits::total 1 # number of overall hits 566system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 567system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 568system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses 569system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses 570system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses 571system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses 572system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 573system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses 574system.cpu.l2cache.demand_misses::total 532 # number of demand (read+write) misses 575system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses 576system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses 577system.cpu.l2cache.overall_misses::total 532 # number of overall misses | 560system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 561system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 562system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 563system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 564system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 565system.cpu.l2cache.overall_hits::total 1 # number of overall hits 566system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 567system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 568system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses 569system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses 570system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses 571system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses 572system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 573system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses 574system.cpu.l2cache.demand_misses::total 532 # number of demand (read+write) misses 575system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses 576system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses 577system.cpu.l2cache.overall_misses::total 532 # number of overall misses |
| 578system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5270000 # number of ReadExReq miss cycles 579system.cpu.l2cache.ReadExReq_miss_latency::total 5270000 # number of ReadExReq miss cycles 580system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27166000 # number of ReadCleanReq miss cycles 581system.cpu.l2cache.ReadCleanReq_miss_latency::total 27166000 # number of ReadCleanReq miss cycles 582system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7348500 # number of ReadSharedReq miss cycles 583system.cpu.l2cache.ReadSharedReq_miss_latency::total 7348500 # number of ReadSharedReq miss cycles 584system.cpu.l2cache.demand_miss_latency::cpu.inst 27166000 # number of demand (read+write) miss cycles 585system.cpu.l2cache.demand_miss_latency::cpu.data 12618500 # number of demand (read+write) miss cycles 586system.cpu.l2cache.demand_miss_latency::total 39784500 # number of demand (read+write) miss cycles 587system.cpu.l2cache.overall_miss_latency::cpu.inst 27166000 # number of overall miss cycles 588system.cpu.l2cache.overall_miss_latency::cpu.data 12618500 # number of overall miss cycles 589system.cpu.l2cache.overall_miss_latency::total 39784500 # number of overall miss cycles | 578system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5343000 # number of ReadExReq miss cycles 579system.cpu.l2cache.ReadExReq_miss_latency::total 5343000 # number of ReadExReq miss cycles 580system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27539000 # number of ReadCleanReq miss cycles 581system.cpu.l2cache.ReadCleanReq_miss_latency::total 27539000 # number of ReadCleanReq miss cycles 582system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471500 # number of ReadSharedReq miss cycles 583system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471500 # number of ReadSharedReq miss cycles 584system.cpu.l2cache.demand_miss_latency::cpu.inst 27539000 # number of demand (read+write) miss cycles 585system.cpu.l2cache.demand_miss_latency::cpu.data 12814500 # number of demand (read+write) miss cycles 586system.cpu.l2cache.demand_miss_latency::total 40353500 # number of demand (read+write) miss cycles 587system.cpu.l2cache.overall_miss_latency::cpu.inst 27539000 # number of overall miss cycles 588system.cpu.l2cache.overall_miss_latency::cpu.data 12814500 # number of overall miss cycles 589system.cpu.l2cache.overall_miss_latency::total 40353500 # number of overall miss cycles |
| 590system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 591system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 592system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) 593system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses) 594system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses) 595system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses) 596system.cpu.l2cache.demand_accesses::cpu.inst 364 # number of demand (read+write) accesses 597system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 606system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 607system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 608system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997253 # miss rate for demand accesses 609system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 610system.cpu.l2cache.demand_miss_rate::total 0.998124 # miss rate for demand accesses 611system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses 612system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 613system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses | 590system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 591system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 592system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) 593system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses) 594system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses) 595system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses) 596system.cpu.l2cache.demand_accesses::cpu.inst 364 # number of demand (read+write) accesses 597system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 606system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 607system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 608system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997253 # miss rate for demand accesses 609system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 610system.cpu.l2cache.demand_miss_rate::total 0.998124 # miss rate for demand accesses 611system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses 612system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 613system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses |
| 614system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72191.780822 # average ReadExReq miss latency 615system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72191.780822 # average ReadExReq miss latency 616system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74837.465565 # average ReadCleanReq miss latency 617system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74837.465565 # average ReadCleanReq miss latency 618system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76546.875000 # average ReadSharedReq miss latency 619system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76546.875000 # average ReadSharedReq miss latency 620system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency 621system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency 622system.cpu.l2cache.demand_avg_miss_latency::total 74782.894737 # average overall miss latency 623system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency 624system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency 625system.cpu.l2cache.overall_avg_miss_latency::total 74782.894737 # average overall miss latency | 614system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73191.780822 # average ReadExReq miss latency 615system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73191.780822 # average ReadExReq miss latency 616system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75865.013774 # average ReadCleanReq miss latency 617system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75865.013774 # average ReadCleanReq miss latency 618system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77828.125000 # average ReadSharedReq miss latency 619system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77828.125000 # average ReadSharedReq miss latency 620system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency 621system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency 622system.cpu.l2cache.demand_avg_miss_latency::total 75852.443609 # average overall miss latency 623system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency 624system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency 625system.cpu.l2cache.overall_avg_miss_latency::total 75852.443609 # average overall miss latency |
| 626system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 628system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 629system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 630system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 631system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 633system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 634system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 635system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 636system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 637system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses 638system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 639system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 640system.cpu.l2cache.demand_mshr_misses::total 532 # number of demand (read+write) MSHR misses 641system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses 642system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 643system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses | 626system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 628system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 629system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 630system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 631system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 633system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 634system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 635system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 636system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 637system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses 638system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 639system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 640system.cpu.l2cache.demand_mshr_misses::total 532 # number of demand (read+write) MSHR misses 641system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses 642system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 643system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses |
| 644system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4540000 # number of ReadExReq MSHR miss cycles 645system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4540000 # number of ReadExReq MSHR miss cycles 646system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23536000 # number of ReadCleanReq MSHR miss cycles 647system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23536000 # number of ReadCleanReq MSHR miss cycles 648system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6388500 # number of ReadSharedReq MSHR miss cycles 649system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6388500 # number of ReadSharedReq MSHR miss cycles 650system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23536000 # number of demand (read+write) MSHR miss cycles 651system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10928500 # number of demand (read+write) MSHR miss cycles 652system.cpu.l2cache.demand_mshr_miss_latency::total 34464500 # number of demand (read+write) MSHR miss cycles 653system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23536000 # number of overall MSHR miss cycles 654system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10928500 # number of overall MSHR miss cycles 655system.cpu.l2cache.overall_mshr_miss_latency::total 34464500 # number of overall MSHR miss cycles | 644system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4613000 # number of ReadExReq MSHR miss cycles 645system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613000 # number of ReadExReq MSHR miss cycles 646system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23909000 # number of ReadCleanReq MSHR miss cycles 647system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23909000 # number of ReadCleanReq MSHR miss cycles 648system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511500 # number of ReadSharedReq MSHR miss cycles 649system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511500 # number of ReadSharedReq MSHR miss cycles 650system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23909000 # number of demand (read+write) MSHR miss cycles 651system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11124500 # number of demand (read+write) MSHR miss cycles 652system.cpu.l2cache.demand_mshr_miss_latency::total 35033500 # number of demand (read+write) MSHR miss cycles 653system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23909000 # number of overall MSHR miss cycles 654system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11124500 # number of overall MSHR miss cycles 655system.cpu.l2cache.overall_mshr_miss_latency::total 35033500 # number of overall MSHR miss cycles |
| 656system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 657system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 658system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses 659system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses 660system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 661system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 662system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses 663system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 664system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses 665system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses 666system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 667system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses | 656system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 657system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 658system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses 659system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses 660system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 661system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 662system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses 663system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 664system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses 665system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses 666system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 667system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses |
| 668system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62191.780822 # average ReadExReq mshr miss latency 669system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62191.780822 # average ReadExReq mshr miss latency 670system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64837.465565 # average ReadCleanReq mshr miss latency 671system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64837.465565 # average ReadCleanReq mshr miss latency 672system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66546.875000 # average ReadSharedReq mshr miss latency 673system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66546.875000 # average ReadSharedReq mshr miss latency 674system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency 675system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency 677system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency 678system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency | 668system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63191.780822 # average ReadExReq mshr miss latency 669system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63191.780822 # average ReadExReq mshr miss latency 670system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65865.013774 # average ReadCleanReq mshr miss latency 671system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65865.013774 # average ReadCleanReq mshr miss latency 672system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67828.125000 # average ReadSharedReq mshr miss latency 673system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67828.125000 # average ReadSharedReq mshr miss latency 674system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency 675system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency 677system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency 678system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency |
| 680system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. 681system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 682system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 683system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 684system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 685system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 680system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. 681system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 682system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 683system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 684system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 685system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 686system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 686system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 687system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution 688system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 689system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 690system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution 691system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution 692system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes) 693system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 694system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 709system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 710system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram 711system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks) 712system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 713system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks) 714system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 715system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) 716system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 687system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution 688system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 689system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 690system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution 691system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution 692system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes) 693system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 694system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 709system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 710system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram 711system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks) 712system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 713system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks) 714system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 715system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) 716system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 717system.membus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states | 717system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter. 718system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 719system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 720system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 721system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 722system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 723system.membus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states |
| 718system.membus.trans_dist::ReadResp 459 # Transaction distribution 719system.membus.trans_dist::ReadExReq 73 # Transaction distribution 720system.membus.trans_dist::ReadExResp 73 # Transaction distribution 721system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution 722system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes) 723system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes) 724system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes) 725system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes) --- 7 unchanged lines hidden (view full) --- 733system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 734system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 735system.membus.snoop_fanout::min_value 0 # Request fanout histogram 736system.membus.snoop_fanout::max_value 0 # Request fanout histogram 737system.membus.snoop_fanout::total 532 # Request fanout histogram 738system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) 739system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) 740system.membus.respLayer1.occupancy 2826500 # Layer occupancy (ticks) | 724system.membus.trans_dist::ReadResp 459 # Transaction distribution 725system.membus.trans_dist::ReadExReq 73 # Transaction distribution 726system.membus.trans_dist::ReadExResp 73 # Transaction distribution 727system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution 728system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes) 729system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes) 730system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes) 731system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes) --- 7 unchanged lines hidden (view full) --- 739system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 740system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 741system.membus.snoop_fanout::min_value 0 # Request fanout histogram 742system.membus.snoop_fanout::max_value 0 # Request fanout histogram 743system.membus.snoop_fanout::total 532 # Request fanout histogram 744system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) 745system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) 746system.membus.respLayer1.occupancy 2826500 # Layer occupancy (ticks) |
| 741system.membus.respLayer1.utilization 7.5 # Layer utilization (%) | 747system.membus.respLayer1.utilization 7.4 # Layer utilization (%) |
| 742 743---------- End Simulation Statistics ---------- | 748 749---------- End Simulation Statistics ---------- |