| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000037 # Number of seconds simulated 4sim_ticks 37494000 # Number of ticks simulated 5final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000037 # Number of seconds simulated 4sim_ticks 37494000 # Number of ticks simulated 5final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 176621 # Simulator instruction rate (inst/s) 8host_op_rate 176529 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1031613588 # Simulator tick rate (ticks/s) 10host_mem_usage 248004 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host | 7host_inst_rate 200557 # Simulator instruction rate (inst/s) 8host_op_rate 200498 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1171902214 # Simulator tick rate (ticks/s) 10host_mem_usage 294520 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host |
| 12sim_insts 6413 # Number of instructions simulated 13sim_ops 6413 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 6413 # Number of instructions simulated 13sim_ops 6413 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 18system.physmem.bytes_read::total 34048 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 532 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 920250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 25465305 # Total energy per rank (pJ) 247system.physmem_1.averagePower 810.835582 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 1481500 # Time in different power states 249system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 28986000 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 19system.physmem.bytes_read::total 34048 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 532 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 246system.physmem_1.preBackEnergy 920250 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 25465305 # Total energy per rank (pJ) 248system.physmem_1.averagePower 810.835582 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 1481500 # Time in different power states 250system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 28986000 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
|
| 253system.cpu.branchPred.lookups 2009 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1241 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1611 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 378 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 23.463687 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target. --- 31 unchanged lines hidden (view full) --- 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_acv 0 # DTB write access violations 294system.cpu.itb.write_accesses 0 # DTB write accesses 295system.cpu.itb.data_hits 0 # DTB hits 296system.cpu.itb.data_misses 0 # DTB misses 297system.cpu.itb.data_acv 0 # DTB access violations 298system.cpu.itb.data_accesses 0 # DTB accesses 299system.cpu.workload.num_syscalls 17 # Number of system calls | 255system.cpu.branchPred.lookups 2009 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1241 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 1611 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 378 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 23.463687 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target. --- 31 unchanged lines hidden (view full) --- 294system.cpu.itb.write_misses 0 # DTB write misses 295system.cpu.itb.write_acv 0 # DTB write access violations 296system.cpu.itb.write_accesses 0 # DTB write accesses 297system.cpu.itb.data_hits 0 # DTB hits 298system.cpu.itb.data_misses 0 # DTB misses 299system.cpu.itb.data_acv 0 # DTB access violations 300system.cpu.itb.data_accesses 0 # DTB accesses 301system.cpu.workload.num_syscalls 17 # Number of system calls |
| 302system.cpu.pwrStateResidencyTicks::ON 37494000 # Cumulative time (in ticks) in various power states |
|
| 300system.cpu.numCycles 74988 # number of cpu cycles simulated 301system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 302system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 303system.cpu.committedInsts 6413 # Number of instructions committed 304system.cpu.committedOps 6413 # Number of ops (including micro ops) committed 305system.cpu.discardedOps 1148 # Number of ops (including micro ops) which were discarded before commit 306system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 307system.cpu.cpi 11.693123 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 338system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction 339system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction 340system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction 341system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 342system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 343system.cpu.op_class_0::total 6413 # Class of committed instruction 344system.cpu.tickCycles 12653 # Number of cycles that the object actually ticked 345system.cpu.idleCycles 62335 # Total number of cycles that the object has spent stopped | 303system.cpu.numCycles 74988 # number of cpu cycles simulated 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 306system.cpu.committedInsts 6413 # Number of instructions committed 307system.cpu.committedOps 6413 # Number of ops (including micro ops) committed 308system.cpu.discardedOps 1148 # Number of ops (including micro ops) which were discarded before commit 309system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 310system.cpu.cpi 11.693123 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 341system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction 342system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction 343system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 6413 # Class of committed instruction 347system.cpu.tickCycles 12653 # Number of cycles that the object actually ticked 348system.cpu.idleCycles 62335 # Total number of cycles that the object has spent stopped |
| 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
|
| 346system.cpu.dcache.tags.replacements 0 # number of replacements 347system.cpu.dcache.tags.tagsinuse 104.135823 # Cycle average of tags in use 348system.cpu.dcache.tags.total_refs 1980 # Total number of references to valid blocks. 349system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 350system.cpu.dcache.tags.avg_refs 11.715976 # Average number of references to valid blocks. 351system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 352system.cpu.dcache.tags.occ_blocks::cpu.data 104.135823 # Average occupied blocks per requestor 353system.cpu.dcache.tags.occ_percent::cpu.data 0.025424 # Average percentage of cache occupancy 354system.cpu.dcache.tags.occ_percent::total 0.025424 # Average percentage of cache occupancy 355system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 356system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 357system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id 358system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 359system.cpu.dcache.tags.tag_accesses 4583 # Number of tag accesses 360system.cpu.dcache.tags.data_accesses 4583 # Number of data accesses | 350system.cpu.dcache.tags.replacements 0 # number of replacements 351system.cpu.dcache.tags.tagsinuse 104.135823 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 1980 # Total number of references to valid blocks. 353system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 354system.cpu.dcache.tags.avg_refs 11.715976 # Average number of references to valid blocks. 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu.dcache.tags.occ_blocks::cpu.data 104.135823 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.025424 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.025424 # Average percentage of cache occupancy 359system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id 362system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 363system.cpu.dcache.tags.tag_accesses 4583 # Number of tag accesses 364system.cpu.dcache.tags.data_accesses 4583 # Number of data accesses |
| 365system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
|
| 361system.cpu.dcache.ReadReq_hits::cpu.data 1240 # number of ReadReq hits 362system.cpu.dcache.ReadReq_hits::total 1240 # number of ReadReq hits 363system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits 364system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 365system.cpu.dcache.demand_hits::cpu.data 1980 # number of demand (read+write) hits 366system.cpu.dcache.demand_hits::total 1980 # number of demand (read+write) hits 367system.cpu.dcache.overall_hits::cpu.data 1980 # number of overall hits 368system.cpu.dcache.overall_hits::total 1980 # number of overall hits --- 78 unchanged lines hidden (view full) --- 447system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80447.916667 # average ReadReq mshr miss latency 448system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80447.916667 # average ReadReq mshr miss latency 449system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency 450system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency 451system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 452system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency 453system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 454system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency | 366system.cpu.dcache.ReadReq_hits::cpu.data 1240 # number of ReadReq hits 367system.cpu.dcache.ReadReq_hits::total 1240 # number of ReadReq hits 368system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits 369system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 370system.cpu.dcache.demand_hits::cpu.data 1980 # number of demand (read+write) hits 371system.cpu.dcache.demand_hits::total 1980 # number of demand (read+write) hits 372system.cpu.dcache.overall_hits::cpu.data 1980 # number of overall hits 373system.cpu.dcache.overall_hits::total 1980 # number of overall hits --- 78 unchanged lines hidden (view full) --- 452system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80447.916667 # average ReadReq mshr miss latency 453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80447.916667 # average ReadReq mshr miss latency 454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency 455system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency 456system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 457system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency 458system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 459system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency |
| 460system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
|
| 455system.cpu.icache.tags.replacements 0 # number of replacements 456system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use 457system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks. 458system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. 459system.cpu.icache.tags.avg_refs 6.381868 # Average number of references to valid blocks. 460system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 461system.cpu.icache.tags.occ_blocks::cpu.inst 175.312988 # Average occupied blocks per requestor 462system.cpu.icache.tags.occ_percent::cpu.inst 0.085602 # Average percentage of cache occupancy 463system.cpu.icache.tags.occ_percent::total 0.085602 # Average percentage of cache occupancy 464system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 465system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 466system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 467system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id 468system.cpu.icache.tags.tag_accesses 5738 # Number of tag accesses 469system.cpu.icache.tags.data_accesses 5738 # Number of data accesses | 461system.cpu.icache.tags.replacements 0 # number of replacements 462system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use 463system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks. 464system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. 465system.cpu.icache.tags.avg_refs 6.381868 # Average number of references to valid blocks. 466system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 467system.cpu.icache.tags.occ_blocks::cpu.inst 175.312988 # Average occupied blocks per requestor 468system.cpu.icache.tags.occ_percent::cpu.inst 0.085602 # Average percentage of cache occupancy 469system.cpu.icache.tags.occ_percent::total 0.085602 # Average percentage of cache occupancy 470system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 471system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 472system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 473system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id 474system.cpu.icache.tags.tag_accesses 5738 # Number of tag accesses 475system.cpu.icache.tags.data_accesses 5738 # Number of data accesses |
| 476system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
|
| 470system.cpu.icache.ReadReq_hits::cpu.inst 2323 # number of ReadReq hits 471system.cpu.icache.ReadReq_hits::total 2323 # number of ReadReq hits 472system.cpu.icache.demand_hits::cpu.inst 2323 # number of demand (read+write) hits 473system.cpu.icache.demand_hits::total 2323 # number of demand (read+write) hits 474system.cpu.icache.overall_hits::cpu.inst 2323 # number of overall hits 475system.cpu.icache.overall_hits::total 2323 # number of overall hits 476system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 477system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 528system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for overall accesses 529system.cpu.icache.overall_mshr_miss_rate::total 0.135467 # mshr miss rate for overall accesses 530system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75280.219780 # average ReadReq mshr miss latency 531system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75280.219780 # average ReadReq mshr miss latency 532system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 533system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency 534system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 535system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency | 477system.cpu.icache.ReadReq_hits::cpu.inst 2323 # number of ReadReq hits 478system.cpu.icache.ReadReq_hits::total 2323 # number of ReadReq hits 479system.cpu.icache.demand_hits::cpu.inst 2323 # number of demand (read+write) hits 480system.cpu.icache.demand_hits::total 2323 # number of demand (read+write) hits 481system.cpu.icache.overall_hits::cpu.inst 2323 # number of overall hits 482system.cpu.icache.overall_hits::total 2323 # number of overall hits 483system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 484system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 535system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for overall accesses 536system.cpu.icache.overall_mshr_miss_rate::total 0.135467 # mshr miss rate for overall accesses 537system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75280.219780 # average ReadReq mshr miss latency 538system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75280.219780 # average ReadReq mshr miss latency 539system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 540system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency 541system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 542system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency |
| 543system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
|
| 536system.cpu.l2cache.tags.replacements 0 # number of replacements 537system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use 538system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 539system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks. 540system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks. 541system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 542system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.327844 # Average occupied blocks per requestor 543system.cpu.l2cache.tags.occ_blocks::cpu.data 58.009069 # Average occupied blocks per requestor 544system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005351 # Average percentage of cache occupancy 545system.cpu.l2cache.tags.occ_percent::cpu.data 0.001770 # Average percentage of cache occupancy 546system.cpu.l2cache.tags.occ_percent::total 0.007121 # Average percentage of cache occupancy 547system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id 548system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 549system.cpu.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 550system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id 551system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses 552system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses | 544system.cpu.l2cache.tags.replacements 0 # number of replacements 545system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use 546system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 547system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks. 548system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks. 549system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 550system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.327844 # Average occupied blocks per requestor 551system.cpu.l2cache.tags.occ_blocks::cpu.data 58.009069 # Average occupied blocks per requestor 552system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005351 # Average percentage of cache occupancy 553system.cpu.l2cache.tags.occ_percent::cpu.data 0.001770 # Average percentage of cache occupancy 554system.cpu.l2cache.tags.occ_percent::total 0.007121 # Average percentage of cache occupancy 555system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id 556system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 557system.cpu.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 558system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id 559system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses 560system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses |
| 561system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
|
| 553system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 554system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 555system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 556system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 557system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 558system.cpu.l2cache.overall_hits::total 1 # number of overall hits 559system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 560system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 671system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency 672system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency 673system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. 674system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 675system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 676system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 677system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 678system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 562system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 563system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 564system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 565system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 566system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 567system.cpu.l2cache.overall_hits::total 1 # number of overall hits 568system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 569system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 680system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency 681system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency 682system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. 683system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 684system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 685system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 686system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 687system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 688system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
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| 679system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution 680system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 681system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 682system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution 683system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution 684system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes) 685system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 686system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 700system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 701system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram 702system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks) 703system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 704system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks) 705system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 706system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) 707system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 689system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution 690system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 691system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 692system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution 693system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution 694system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes) 695system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 696system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 710system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 711system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram 712system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks) 713system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 714system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks) 715system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 716system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) 717system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 718system.membus.pwrStateResidencyTicks::UNDEFINED 37494000 # Cumulative time (in ticks) in various power states |
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| 708system.membus.trans_dist::ReadResp 459 # Transaction distribution 709system.membus.trans_dist::ReadExReq 73 # Transaction distribution 710system.membus.trans_dist::ReadExResp 73 # Transaction distribution 711system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution 712system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes) 713system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes) 714system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes) 715system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 719system.membus.trans_dist::ReadResp 459 # Transaction distribution 720system.membus.trans_dist::ReadExReq 73 # Transaction distribution 721system.membus.trans_dist::ReadExResp 73 # Transaction distribution 722system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution 723system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes) 724system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes) 725system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes) 726system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |