| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000037 # Number of seconds simulated 4sim_ticks 37494000 # Number of ticks simulated 5final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000037 # Number of seconds simulated 4sim_ticks 37494000 # Number of ticks simulated 5final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 257461 # Simulator instruction rate (inst/s) 8host_op_rate 257361 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1504149892 # Simulator tick rate (ticks/s) | 7host_inst_rate 141195 # Simulator instruction rate (inst/s) 8host_op_rate 141164 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 825166364 # Simulator tick rate (ticks/s) |
| 10host_mem_usage 252900 # Number of bytes of host memory used | 10host_mem_usage 252900 # Number of bytes of host memory used |
| 11host_seconds 0.03 # Real time elapsed on the host | 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 6413 # Number of instructions simulated 13sim_ops 6413 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 18system.physmem.bytes_read::total 34048 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory --- 387 unchanged lines hidden (view full) --- 407system.cpu.dcache.overall_avg_miss_latency::cpu.data 76850.220264 # average overall miss latency 408system.cpu.dcache.overall_avg_miss_latency::total 76850.220264 # average overall miss latency 409system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 6413 # Number of instructions simulated 13sim_ops 6413 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 18system.physmem.bytes_read::total 34048 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory --- 387 unchanged lines hidden (view full) --- 407system.cpu.dcache.overall_avg_miss_latency::cpu.data 76850.220264 # average overall miss latency 408system.cpu.dcache.overall_avg_miss_latency::total 76850.220264 # average overall miss latency 409system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 415system.cpu.dcache.fast_writes 0 # number of fast writes performed 416system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 417system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 418system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 419system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits 420system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 421system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits 422system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits 423system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits 424system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 449system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80447.916667 # average ReadReq mshr miss latency 450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80447.916667 # average ReadReq mshr miss latency 451system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency 452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency 453system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 454system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency 455system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 456system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency | 415system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 416system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 417system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits 418system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 419system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits 420system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits 421system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits 422system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 447system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80447.916667 # average ReadReq mshr miss latency 448system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80447.916667 # average ReadReq mshr miss latency 449system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency 450system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency 451system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 452system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency 453system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 454system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency |
| 457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 458system.cpu.icache.tags.replacements 0 # number of replacements 459system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use 460system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks. 461system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. 462system.cpu.icache.tags.avg_refs 6.381868 # Average number of references to valid blocks. 463system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 464system.cpu.icache.tags.occ_blocks::cpu.inst 175.312988 # Average occupied blocks per requestor 465system.cpu.icache.tags.occ_percent::cpu.inst 0.085602 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 507system.cpu.icache.overall_avg_miss_latency::cpu.inst 76280.219780 # average overall miss latency 508system.cpu.icache.overall_avg_miss_latency::total 76280.219780 # average overall miss latency 509system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 510system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 511system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 512system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 513system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 514system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 455system.cpu.icache.tags.replacements 0 # number of replacements 456system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use 457system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks. 458system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. 459system.cpu.icache.tags.avg_refs 6.381868 # Average number of references to valid blocks. 460system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 461system.cpu.icache.tags.occ_blocks::cpu.inst 175.312988 # Average occupied blocks per requestor 462system.cpu.icache.tags.occ_percent::cpu.inst 0.085602 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 504system.cpu.icache.overall_avg_miss_latency::cpu.inst 76280.219780 # average overall miss latency 505system.cpu.icache.overall_avg_miss_latency::total 76280.219780 # average overall miss latency 506system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 507system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 508system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 509system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 510system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 511system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 515system.cpu.icache.fast_writes 0 # number of fast writes performed 516system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 517system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses 518system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses 519system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses 520system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 521system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses 522system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses 523system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27402000 # number of ReadReq MSHR miss cycles 524system.cpu.icache.ReadReq_mshr_miss_latency::total 27402000 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 533system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for overall accesses 534system.cpu.icache.overall_mshr_miss_rate::total 0.135467 # mshr miss rate for overall accesses 535system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75280.219780 # average ReadReq mshr miss latency 536system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75280.219780 # average ReadReq mshr miss latency 537system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency 539system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency | 512system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses 513system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses 514system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses 515system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 516system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses 517system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses 518system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27402000 # number of ReadReq MSHR miss cycles 519system.cpu.icache.ReadReq_mshr_miss_latency::total 27402000 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 528system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for overall accesses 529system.cpu.icache.overall_mshr_miss_rate::total 0.135467 # mshr miss rate for overall accesses 530system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75280.219780 # average ReadReq mshr miss latency 531system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75280.219780 # average ReadReq mshr miss latency 532system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 533system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency 534system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 535system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency |
| 541system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 542system.cpu.l2cache.tags.replacements 0 # number of replacements 543system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use 544system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 545system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks. 546system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks. 547system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 548system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.327844 # Average occupied blocks per requestor 549system.cpu.l2cache.tags.occ_blocks::cpu.data 58.009069 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 623system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76050.295858 # average overall miss latency 624system.cpu.l2cache.overall_avg_miss_latency::total 74617.481203 # average overall miss latency 625system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 626system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 628system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 629system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 630system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 536system.cpu.l2cache.tags.replacements 0 # number of replacements 537system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use 538system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 539system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks. 540system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks. 541system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 542system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.327844 # Average occupied blocks per requestor 543system.cpu.l2cache.tags.occ_blocks::cpu.data 58.009069 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 617system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76050.295858 # average overall miss latency 618system.cpu.l2cache.overall_avg_miss_latency::total 74617.481203 # average overall miss latency 619system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 620system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 621system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 622system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 623system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 624system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 631system.cpu.l2cache.fast_writes 0 # number of fast writes performed 632system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 633system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 634system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 635system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 636system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 637system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 638system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses 639system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 640system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 673system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68932.291667 # average ReadSharedReq mshr miss latency 674system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68932.291667 # average ReadSharedReq mshr miss latency 675system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency 678system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency 680system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency | 625system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 626system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 627system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 628system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 629system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 630system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses 631system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 632system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 665system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68932.291667 # average ReadSharedReq mshr miss latency 666system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68932.291667 # average ReadSharedReq mshr miss latency 667system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency 668system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency 669system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency 670system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency 671system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency 672system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency |
| 681system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 682system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. 683system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 684system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 685system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 686system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 687system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 688system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution 689system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution --- 52 unchanged lines hidden --- | 673system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. 674system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 675system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 676system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 677system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 678system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 679system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution 680system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution --- 52 unchanged lines hidden --- |