| stats.txt (10433:821cbe4a183b) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000035 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000035 # Number of seconds simulated |
| 4sim_ticks 35024500 # Number of ticks simulated 5final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 35022500 # Number of ticks simulated 5final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 72507 # Simulator instruction rate (inst/s) 8host_op_rate 72491 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 396631772 # Simulator tick rate (ticks/s) 10host_mem_usage 236200 # Number of bytes of host memory used | 7host_inst_rate 71946 # Simulator instruction rate (inst/s) 8host_op_rate 71929 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 393524726 # Simulator tick rate (ticks/s) 10host_mem_usage 237176 # Number of bytes of host memory used |
| 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 6400 # Number of instructions simulated 13sim_ops 6400 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory 17system.physmem.bytes_read::total 34112 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 533 # Number of read requests responded to by this memory | 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 6400 # Number of instructions simulated 13sim_ops 6400 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory 17system.physmem.bytes_read::total 34112 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 533 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s) |
| 28system.physmem.readReqs 533 # Number of read requests accepted 29system.physmem.writeReqs 0 # Number of write requests accepted 30system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 32system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 35system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 28system.physmem.readReqs 533 # Number of read requests accepted 29system.physmem.writeReqs 0 # Number of write requests accepted 30system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 32system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 35system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 74system.physmem.totGap 34926000 # Total gap between requests | 74system.physmem.totGap 34924000 # Total gap between requests |
| 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) 81system.physmem.readPktSize::6 533 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation | 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) 81system.physmem.readPktSize::6 533 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation |
| 199system.physmem.totQLat 3928000 # Total ticks spent queuing 200system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM | 199system.physmem.totQLat 3887500 # Total ticks spent queuing 200system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM |
| 201system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers | 201system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers |
| 202system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst | 202system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst |
| 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 204system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst 205system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s | 204system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst 205system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s |
| 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 207system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s | 207system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s |
| 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 7.61 # Data bus utilization in percentage 211system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 215system.physmem.readRowHits 435 # Number of row buffer hits during reads 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes 217system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 7.61 # Data bus utilization in percentage 211system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 215system.physmem.readRowHits 435 # Number of row buffer hits during reads 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes 217system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 219system.physmem.avgGap 65527.20 # Average gap between requests | 219system.physmem.avgGap 65523.45 # Average gap between requests |
| 220system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 15500 # Time in different power states 222system.physmem.memoryStateTime::REF 1040000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 220system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 15500 # Time in different power states 222system.physmem.memoryStateTime::REF 1040000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 224system.physmem.memoryStateTime::ACT 30394500 # Time in different power states | 224system.physmem.memoryStateTime::ACT 30393500 # Time in different power states |
| 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 226system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ) 227system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ) 228system.physmem.preEnergy::0 140250 # Energy for precharge commands per rank (pJ) 229system.physmem.preEnergy::1 210375 # Energy for precharge commands per rank (pJ) 230system.physmem.readEnergy::0 2082600 # Energy for read commands per rank (pJ) 231system.physmem.readEnergy::1 1677000 # Energy for read commands per rank (pJ) 232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 234system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) 235system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) 236system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ) | 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 226system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ) 227system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ) 228system.physmem.preEnergy::0 140250 # Energy for precharge commands per rank (pJ) 229system.physmem.preEnergy::1 210375 # Energy for precharge commands per rank (pJ) 230system.physmem.readEnergy::0 2082600 # Energy for read commands per rank (pJ) 231system.physmem.readEnergy::1 1677000 # Energy for read commands per rank (pJ) 232system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 233system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 234system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) 235system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) 236system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ) |
| 237system.physmem.actBackEnergy::1 20168595 # Energy for active background per rank (pJ) | 237system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ) |
| 238system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ) | 238system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ) |
| 239system.physmem.preBackEnergy::1 1170000 # Energy for precharge background per rank (pJ) | 239system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ) |
| 240system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ) | 240system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ) |
| 241system.physmem.totalEnergy::1 25645770 # Total energy per rank (pJ) | 241system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ) |
| 242system.physmem.averagePower::0 827.295718 # Core power per rank (mW) | 242system.physmem.averagePower::0 827.295718 # Core power per rank (mW) |
| 243system.physmem.averagePower::1 815.802457 # Core power per rank (mW) 244system.membus.trans_dist::ReadReq 460 # Transaction distribution 245system.membus.trans_dist::ReadResp 460 # Transaction distribution 246system.membus.trans_dist::ReadExReq 73 # Transaction distribution 247system.membus.trans_dist::ReadExResp 73 # Transaction distribution 248system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) 249system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) 250system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) 251system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 252system.membus.snoops 0 # Total snoops (count) 253system.membus.snoop_fanout::samples 533 # Request fanout histogram 254system.membus.snoop_fanout::mean 0 # Request fanout histogram 255system.membus.snoop_fanout::stdev 0 # Request fanout histogram 256system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 257system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram 258system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 259system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 260system.membus.snoop_fanout::min_value 0 # Request fanout histogram 261system.membus.snoop_fanout::max_value 0 # Request fanout histogram 262system.membus.snoop_fanout::total 533 # Request fanout histogram 263system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks) 264system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) 265system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks) 266system.membus.respLayer1.utilization 14.2 # Layer utilization (%) 267system.cpu_clk_domain.clock 500 # Clock period in ticks 268system.cpu.branchPred.lookups 1959 # Number of BP lookups 269system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted | 243system.physmem.averagePower::1 815.785757 # Core power per rank (mW) 244system.cpu.branchPred.lookups 1972 # Number of BP lookups 245system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted |
| 270system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect | 246system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect |
| 271system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups 272system.cpu.branchPred.BTBHits 381 # Number of BTB hits | 247system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups 248system.cpu.branchPred.BTBHits 385 # Number of BTB hits |
| 273system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 249system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 274system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage | 250system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage |
| 275system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. 276system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. | 251system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. 252system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. |
| 253system.cpu_clk_domain.clock 500 # Clock period in ticks |
|
| 277system.cpu.dtb.fetch_hits 0 # ITB hits 278system.cpu.dtb.fetch_misses 0 # ITB misses 279system.cpu.dtb.fetch_acv 0 # ITB acv 280system.cpu.dtb.fetch_accesses 0 # ITB accesses | 254system.cpu.dtb.fetch_hits 0 # ITB hits 255system.cpu.dtb.fetch_misses 0 # ITB misses 256system.cpu.dtb.fetch_acv 0 # ITB acv 257system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 281system.cpu.dtb.read_hits 1368 # DTB read hits | 258system.cpu.dtb.read_hits 1370 # DTB read hits |
| 282system.cpu.dtb.read_misses 11 # DTB read misses 283system.cpu.dtb.read_acv 0 # DTB read access violations | 259system.cpu.dtb.read_misses 11 # DTB read misses 260system.cpu.dtb.read_acv 0 # DTB read access violations |
| 284system.cpu.dtb.read_accesses 1379 # DTB read accesses | 261system.cpu.dtb.read_accesses 1381 # DTB read accesses |
| 285system.cpu.dtb.write_hits 884 # DTB write hits 286system.cpu.dtb.write_misses 3 # DTB write misses 287system.cpu.dtb.write_acv 0 # DTB write access violations 288system.cpu.dtb.write_accesses 887 # DTB write accesses | 262system.cpu.dtb.write_hits 884 # DTB write hits 263system.cpu.dtb.write_misses 3 # DTB write misses 264system.cpu.dtb.write_acv 0 # DTB write access violations 265system.cpu.dtb.write_accesses 887 # DTB write accesses |
| 289system.cpu.dtb.data_hits 2252 # DTB hits | 266system.cpu.dtb.data_hits 2254 # DTB hits |
| 290system.cpu.dtb.data_misses 14 # DTB misses 291system.cpu.dtb.data_acv 0 # DTB access violations | 267system.cpu.dtb.data_misses 14 # DTB misses 268system.cpu.dtb.data_acv 0 # DTB access violations |
| 292system.cpu.dtb.data_accesses 2266 # DTB accesses 293system.cpu.itb.fetch_hits 2630 # ITB hits | 269system.cpu.dtb.data_accesses 2268 # DTB accesses 270system.cpu.itb.fetch_hits 2642 # ITB hits |
| 294system.cpu.itb.fetch_misses 17 # ITB misses 295system.cpu.itb.fetch_acv 0 # ITB acv | 271system.cpu.itb.fetch_misses 17 # ITB misses 272system.cpu.itb.fetch_acv 0 # ITB acv |
| 296system.cpu.itb.fetch_accesses 2647 # ITB accesses | 273system.cpu.itb.fetch_accesses 2659 # ITB accesses |
| 297system.cpu.itb.read_hits 0 # DTB read hits 298system.cpu.itb.read_misses 0 # DTB read misses 299system.cpu.itb.read_acv 0 # DTB read access violations 300system.cpu.itb.read_accesses 0 # DTB read accesses 301system.cpu.itb.write_hits 0 # DTB write hits 302system.cpu.itb.write_misses 0 # DTB write misses 303system.cpu.itb.write_acv 0 # DTB write access violations 304system.cpu.itb.write_accesses 0 # DTB write accesses 305system.cpu.itb.data_hits 0 # DTB hits 306system.cpu.itb.data_misses 0 # DTB misses 307system.cpu.itb.data_acv 0 # DTB access violations 308system.cpu.itb.data_accesses 0 # DTB accesses 309system.cpu.workload.num_syscalls 17 # Number of system calls | 274system.cpu.itb.read_hits 0 # DTB read hits 275system.cpu.itb.read_misses 0 # DTB read misses 276system.cpu.itb.read_acv 0 # DTB read access violations 277system.cpu.itb.read_accesses 0 # DTB read accesses 278system.cpu.itb.write_hits 0 # DTB write hits 279system.cpu.itb.write_misses 0 # DTB write misses 280system.cpu.itb.write_acv 0 # DTB write access violations 281system.cpu.itb.write_accesses 0 # DTB write accesses 282system.cpu.itb.data_hits 0 # DTB hits 283system.cpu.itb.data_misses 0 # DTB misses 284system.cpu.itb.data_acv 0 # DTB access violations 285system.cpu.itb.data_accesses 0 # DTB accesses 286system.cpu.workload.num_syscalls 17 # Number of system calls |
| 310system.cpu.numCycles 70049 # number of cpu cycles simulated | 287system.cpu.numCycles 70045 # number of cpu cycles simulated |
| 311system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 312system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 313system.cpu.committedInsts 6400 # Number of instructions committed 314system.cpu.committedOps 6400 # Number of ops (including micro ops) committed | 288system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 289system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 290system.cpu.committedInsts 6400 # Number of instructions committed 291system.cpu.committedOps 6400 # Number of ops (including micro ops) committed |
| 315system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit | 292system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit |
| 316system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 293system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 317system.cpu.cpi 10.945156 # CPI: cycles per instruction 318system.cpu.ipc 0.091365 # IPC: instructions per cycle 319system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked 320system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped | 294system.cpu.cpi 10.944531 # CPI: cycles per instruction 295system.cpu.ipc 0.091370 # IPC: instructions per cycle 296system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked 297system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped 298system.cpu.dcache.tags.replacements 0 # number of replacements 299system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use 300system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. 301system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 302system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. 303system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 304system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor 305system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy 306system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy 307system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 308system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 309system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 310system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 311system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses 312system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses 313system.cpu.dcache.ReadReq_hits::cpu.inst 1233 # number of ReadReq hits 314system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits 315system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits 316system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 317system.cpu.dcache.demand_hits::cpu.inst 1973 # number of demand (read+write) hits 318system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits 319system.cpu.dcache.overall_hits::cpu.inst 1973 # number of overall hits 320system.cpu.dcache.overall_hits::total 1973 # number of overall hits 321system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses 322system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses 323system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses 324system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 325system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 326system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses 327system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses 328system.cpu.dcache.overall_misses::total 227 # number of overall misses 329system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles 330system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles 331system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles 332system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles 333system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles 334system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles 335system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles 336system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles 337system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses) 338system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) 339system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) 340system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 341system.cpu.dcache.demand_accesses::cpu.inst 2200 # number of demand (read+write) accesses 342system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses 343system.cpu.dcache.overall_accesses::cpu.inst 2200 # number of overall (read+write) accesses 344system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses 345system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076404 # miss rate for ReadReq accesses 346system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses 347system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses 348system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 349system.cpu.dcache.demand_miss_rate::cpu.inst 0.103182 # miss rate for demand accesses 350system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses 351system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 # miss rate for overall accesses 352system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses 353system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency 354system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency 355system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency 356system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency 357system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency 358system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency 359system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency 360system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency 361system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 362system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 363system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 364system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 365system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 366system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 367system.cpu.dcache.fast_writes 0 # number of fast writes performed 368system.cpu.dcache.cache_copies 0 # number of cache copies performed 369system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 370system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 371system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits 372system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 373system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits 374system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits 375system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits 376system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits 377system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses 378system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 379system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses 380system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 381system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses 382system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 383system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses 384system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses 385system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles 386system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles 387system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles 388system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles 389system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles 390system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles 391system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles 392system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles 393system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses 394system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses 395system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses 396system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 397system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for demand accesses 398system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses 399system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for overall accesses 400system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses 401system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency 402system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency 403system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency 404system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency 405system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency 406system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency 407system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency 408system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency 409system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 321system.cpu.icache.tags.replacements 0 # number of replacements | 410system.cpu.icache.tags.replacements 0 # number of replacements |
| 322system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use 323system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. | 411system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use 412system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. |
| 324system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. | 413system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. |
| 325system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. | 414system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. |
| 326system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 415system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 327system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor 328system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy 329system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy | 416system.cpu.icache.tags.occ_blocks::cpu.inst 176.126032 # Average occupied blocks per requestor 417system.cpu.icache.tags.occ_percent::cpu.inst 0.085999 # Average percentage of cache occupancy 418system.cpu.icache.tags.occ_percent::total 0.085999 # Average percentage of cache occupancy |
| 330system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 331system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 332system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 333system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id | 419system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 420system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 421system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 422system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id |
| 334system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses 335system.cpu.icache.tags.data_accesses 5625 # Number of data accesses 336system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits 337system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits 338system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits 339system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits 340system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits 341system.cpu.icache.overall_hits::total 2265 # number of overall hits | 423system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses 424system.cpu.icache.tags.data_accesses 5649 # Number of data accesses 425system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits 426system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits 427system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits 428system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits 429system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits 430system.cpu.icache.overall_hits::total 2277 # number of overall hits |
| 342system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 343system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 344system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 345system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 346system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 347system.cpu.icache.overall_misses::total 365 # number of overall misses | 431system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 432system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 433system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 434system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 435system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 436system.cpu.icache.overall_misses::total 365 # number of overall misses |
| 348system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles 349system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles 350system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles 351system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles 352system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles 353system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles 354system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) 355system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) 356system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses 357system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses 358system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses 359system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses 360system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses 361system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses 362system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses 363system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses 364system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses 365system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses 366system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency 367system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency 368system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency 369system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency 370system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency 371system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency | 437system.cpu.icache.ReadReq_miss_latency::cpu.inst 25915750 # number of ReadReq miss cycles 438system.cpu.icache.ReadReq_miss_latency::total 25915750 # number of ReadReq miss cycles 439system.cpu.icache.demand_miss_latency::cpu.inst 25915750 # number of demand (read+write) miss cycles 440system.cpu.icache.demand_miss_latency::total 25915750 # number of demand (read+write) miss cycles 441system.cpu.icache.overall_miss_latency::cpu.inst 25915750 # number of overall miss cycles 442system.cpu.icache.overall_miss_latency::total 25915750 # number of overall miss cycles 443system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) 444system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) 445system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses 446system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses 447system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses 448system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses 449system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses 450system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses 451system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses 452system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses 453system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses 454system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses 455system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795 # average ReadReq miss latency 456system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795 # average ReadReq miss latency 457system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency 458system.cpu.icache.demand_avg_miss_latency::total 71002.054795 # average overall miss latency 459system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency 460system.cpu.icache.overall_avg_miss_latency::total 71002.054795 # average overall miss latency |
| 372system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 373system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 374system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 376system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 377system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 378system.cpu.icache.fast_writes 0 # number of fast writes performed 379system.cpu.icache.cache_copies 0 # number of cache copies performed 380system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 381system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses 382system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 383system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 384system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 385system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses | 461system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 464system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 465system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 466system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 467system.cpu.icache.fast_writes 0 # number of fast writes performed 468system.cpu.icache.cache_copies 0 # number of cache copies performed 469system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 470system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses 471system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 472system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 473system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 474system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses |
| 386system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles 387system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles 388system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles 389system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles 390system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles 391system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles 392system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses 393system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses 394system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses 395system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses 396system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses 397system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses 398system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency 399system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency 400system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency 401system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency 402system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency 403system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency | 475system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25028250 # number of ReadReq MSHR miss cycles 476system.cpu.icache.ReadReq_mshr_miss_latency::total 25028250 # number of ReadReq MSHR miss cycles 477system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25028250 # number of demand (read+write) MSHR miss cycles 478system.cpu.icache.demand_mshr_miss_latency::total 25028250 # number of demand (read+write) MSHR miss cycles 479system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25028250 # number of overall MSHR miss cycles 480system.cpu.icache.overall_mshr_miss_latency::total 25028250 # number of overall MSHR miss cycles 481system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses 482system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses 483system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses 484system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses 485system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses 486system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses 487system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945 # average ReadReq mshr miss latency 488system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945 # average ReadReq mshr miss latency 489system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency 490system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency 491system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency 492system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency |
| 404system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 493system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 405system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution 406system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution 407system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 408system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 409system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 410system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 411system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) 412system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) 413system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 414system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) 415system.cpu.toL2Bus.snoops 0 # Total snoops (count) 416system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram 417system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 418system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 419system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 420system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 421system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram 422system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 423system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 424system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 425system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 426system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram 427system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) 428system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 429system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) 430system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 431system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) 432system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) | |
| 433system.cpu.l2cache.tags.replacements 0 # number of replacements | 494system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 434system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use | 495system.cpu.l2cache.tags.tagsinuse 233.857006 # Cycle average of tags in use |
| 435system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 436system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. 437system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. 438system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 496system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 497system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. 498system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. 499system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 439system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor 440system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy 441system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy | 500system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.857006 # Average occupied blocks per requestor 501system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy 502system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy |
| 442system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id 443system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 444system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 445system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id 446system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses 447system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses 448system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 449system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits --- 4 unchanged lines hidden (view full) --- 454system.cpu.l2cache.ReadReq_misses::cpu.inst 460 # number of ReadReq misses 455system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses 456system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses 457system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 458system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses 459system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses 460system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses 461system.cpu.l2cache.overall_misses::total 533 # number of overall misses | 503system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id 504system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 505system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 506system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id 507system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses 508system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses 509system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 510system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits --- 4 unchanged lines hidden (view full) --- 515system.cpu.l2cache.ReadReq_misses::cpu.inst 460 # number of ReadReq misses 516system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses 517system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses 518system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 519system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses 520system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses 521system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses 522system.cpu.l2cache.overall_misses::total 533 # number of overall misses |
| 462system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles 463system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles 464system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles 465system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles 466system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles 467system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles 468system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles 469system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles | 523system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31686750 # number of ReadReq miss cycles 524system.cpu.l2cache.ReadReq_miss_latency::total 31686750 # number of ReadReq miss cycles 525system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5053000 # number of ReadExReq miss cycles 526system.cpu.l2cache.ReadExReq_miss_latency::total 5053000 # number of ReadExReq miss cycles 527system.cpu.l2cache.demand_miss_latency::cpu.inst 36739750 # number of demand (read+write) miss cycles 528system.cpu.l2cache.demand_miss_latency::total 36739750 # number of demand (read+write) miss cycles 529system.cpu.l2cache.overall_miss_latency::cpu.inst 36739750 # number of overall miss cycles 530system.cpu.l2cache.overall_miss_latency::total 36739750 # number of overall miss cycles |
| 470system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) 471system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) 472system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) 473system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 474system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses 475system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses 476system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses 477system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses 478system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses 479system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses 480system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 481system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 482system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses 483system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses 484system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses 485system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses | 531system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) 532system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) 533system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) 534system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 535system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses 536system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses 537system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses 538system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses 539system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses 540system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses 541system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 542system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 543system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses 544system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses 545system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses 546system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses |
| 486system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency 487system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency 488system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency 489system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency 490system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency 491system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency 492system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency 493system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency | 547system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130 # average ReadReq miss latency 548system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130 # average ReadReq miss latency 549system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082 # average ReadExReq miss latency 550system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082 # average ReadExReq miss latency 551system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency 552system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570 # average overall miss latency 553system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency 554system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570 # average overall miss latency |
| 494system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 495system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 496system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 497system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 498system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 499system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 500system.cpu.l2cache.fast_writes 0 # number of fast writes performed 501system.cpu.l2cache.cache_copies 0 # number of cache copies performed 502system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses 503system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses 504system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses 505system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 506system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses 507system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses 508system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses 509system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses | 555system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 556system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 559system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 561system.cpu.l2cache.fast_writes 0 # number of fast writes performed 562system.cpu.l2cache.cache_copies 0 # number of cache copies performed 563system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses 564system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses 565system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses 566system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 567system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses 568system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses 569system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses 570system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses |
| 510system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles 511system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles | 571system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25921750 # number of ReadReq MSHR miss cycles 572system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25921750 # number of ReadReq MSHR miss cycles |
| 512system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles 513system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles | 573system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles 574system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles |
| 514system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles 515system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles 516system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles 517system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles | 575system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30069250 # number of demand (read+write) MSHR miss cycles 576system.cpu.l2cache.demand_mshr_miss_latency::total 30069250 # number of demand (read+write) MSHR miss cycles 577system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30069250 # number of overall MSHR miss cycles 578system.cpu.l2cache.overall_mshr_miss_latency::total 30069250 # number of overall MSHR miss cycles |
| 518system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses 519system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses 520system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 521system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 522system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses 523system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses 524system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses 525system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses | 579system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses 580system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses 581system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 582system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses 584system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses 585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses 586system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses |
| 526system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency 527system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency | 587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435 # average ReadReq mshr miss latency 588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435 # average ReadReq mshr miss latency |
| 528system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency 529system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency | 589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency 590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency |
| 530system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency 531system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency 532system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency 533system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency | 591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency 592system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency 594system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency |
| 534system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 535system.cpu.dcache.tags.replacements 0 # number of replacements 536system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use 537system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. 538system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 539system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. 540system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 541system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor 542system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy 543system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy 544system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 545system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 546system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 547system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 548system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses 549system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses 550system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits 551system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits 552system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits 553system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 554system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits 555system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits 556system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits 557system.cpu.dcache.overall_hits::total 1968 # number of overall hits 558system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses 559system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses 560system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses 561system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 562system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 563system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses 564system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses 565system.cpu.dcache.overall_misses::total 227 # number of overall misses 566system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles 567system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles 568system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles 569system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles 570system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles 571system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles 572system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles 573system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles 574system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses) 575system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses) 576system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) 577system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 578system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses 579system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses 580system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses 581system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses 582system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses 583system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses 584system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses 585system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 586system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses 587system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses 588system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses 589system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses 590system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency 591system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency 592system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency 593system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency 594system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency 595system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency 596system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency 597system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency 598system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 599system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 600system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 601system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 602system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 603system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 604system.cpu.dcache.fast_writes 0 # number of fast writes performed 605system.cpu.dcache.cache_copies 0 # number of cache copies performed 606system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 607system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 608system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits 609system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 610system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits 611system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits 612system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits 613system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits 614system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses 615system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 616system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses 617system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 618system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses 619system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 620system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses 621system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses 622system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles 623system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles 624system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles 625system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles 626system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles 627system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles 628system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles 629system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles 630system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses 631system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses 632system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses 633system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 634system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses 635system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses 636system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses 637system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses 638system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency 639system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency 640system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency 641system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency 642system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency 643system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency 644system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency 645system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency 646system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 596system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution 597system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution 598system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 600system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 601system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 602system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) 603system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) 604system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 605system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) 606system.cpu.toL2Bus.snoops 0 # Total snoops (count) 607system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram 608system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 609system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 610system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 611system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 612system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram 613system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 614system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 615system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 616system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 617system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram 618system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) 619system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 620system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) 621system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 622system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) 623system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 624system.membus.trans_dist::ReadReq 460 # Transaction distribution 625system.membus.trans_dist::ReadResp 460 # Transaction distribution 626system.membus.trans_dist::ReadExReq 73 # Transaction distribution 627system.membus.trans_dist::ReadExResp 73 # Transaction distribution 628system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) 629system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) 630system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) 631system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 632system.membus.snoops 0 # Total snoops (count) 633system.membus.snoop_fanout::samples 533 # Request fanout histogram 634system.membus.snoop_fanout::mean 0 # Request fanout histogram 635system.membus.snoop_fanout::stdev 0 # Request fanout histogram 636system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 637system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram 638system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 639system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 640system.membus.snoop_fanout::min_value 0 # Request fanout histogram 641system.membus.snoop_fanout::max_value 0 # Request fanout histogram 642system.membus.snoop_fanout::total 533 # Request fanout histogram 643system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) 644system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) 645system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks) 646system.membus.respLayer1.utilization 14.2 # Layer utilization (%) |
| 647 648---------- End Simulation Statistics ---------- | 647 648---------- End Simulation Statistics ---------- |