| stats.txt (10261:dc198e224a85) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000035 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000035 # Number of seconds simulated |
| 4sim_ticks 35015500 # Number of ticks simulated 5final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 35024500 # Number of ticks simulated 5final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 57020 # Simulator instruction rate (inst/s) 8host_op_rate 57008 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 311836228 # Simulator tick rate (ticks/s) 10host_mem_usage 240292 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host | 7host_inst_rate 173753 # Simulator instruction rate (inst/s) 8host_op_rate 173686 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 950177695 # Simulator tick rate (ticks/s) 10host_mem_usage 289108 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host |
| 12sim_insts 6400 # Number of instructions simulated 13sim_ops 6400 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory 17system.physmem.bytes_read::total 34112 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 533 # Number of read requests responded to by this memory | 12sim_insts 6400 # Number of instructions simulated 13sim_ops 6400 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory 17system.physmem.bytes_read::total 34112 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 533 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s) |
| 28system.physmem.readReqs 533 # Number of read requests accepted 29system.physmem.writeReqs 0 # Number of write requests accepted 30system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 32system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 35system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 28system.physmem.readReqs 533 # Number of read requests accepted 29system.physmem.writeReqs 0 # Number of write requests accepted 30system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 32system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 35system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 74system.physmem.totGap 34917000 # Total gap between requests | 74system.physmem.totGap 34926000 # Total gap between requests |
| 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) 81system.physmem.readPktSize::6 533 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation | 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) 81system.physmem.readPktSize::6 533 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 191system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation |
| 199system.physmem.totQLat 3823500 # Total ticks spent queuing 200system.physmem.totMemAccLat 13817250 # Total ticks spent from burst creation until serviced by the DRAM | 199system.physmem.totQLat 3928000 # Total ticks spent queuing 200system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM |
| 201system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers | 201system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers |
| 202system.physmem.avgQLat 7173.55 # Average queueing delay per DRAM burst | 202system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst |
| 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 204system.physmem.avgMemAccLat 25923.55 # Average memory access latency per DRAM burst 205system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s | 204system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst 205system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s |
| 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 207system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s | 207system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s |
| 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 7.61 # Data bus utilization in percentage 211system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 215system.physmem.readRowHits 435 # Number of row buffer hits during reads 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes 217system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 7.61 # Data bus utilization in percentage 211system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 215system.physmem.readRowHits 435 # Number of row buffer hits during reads 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes 217system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 219system.physmem.avgGap 65510.32 # Average gap between requests | 219system.physmem.avgGap 65527.20 # Average gap between requests |
| 220system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 15500 # Time in different power states 222system.physmem.memoryStateTime::REF 1040000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 220system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 15500 # Time in different power states 222system.physmem.memoryStateTime::REF 1040000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 224system.physmem.memoryStateTime::ACT 30385500 # Time in different power states | 224system.physmem.memoryStateTime::ACT 30394500 # Time in different power states |
| 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 226system.membus.throughput 974197141 # Throughput (bytes/s) | |
| 227system.membus.trans_dist::ReadReq 460 # Transaction distribution 228system.membus.trans_dist::ReadResp 460 # Transaction distribution 229system.membus.trans_dist::ReadExReq 73 # Transaction distribution 230system.membus.trans_dist::ReadExResp 73 # Transaction distribution 231system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) 232system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) | 226system.membus.trans_dist::ReadReq 460 # Transaction distribution 227system.membus.trans_dist::ReadResp 460 # Transaction distribution 228system.membus.trans_dist::ReadExReq 73 # Transaction distribution 229system.membus.trans_dist::ReadExResp 73 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) |
| 233system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) 234system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 235system.membus.data_through_bus 34112 # Total data (bytes) 236system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 232system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) 233system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 234system.membus.snoops 0 # Total snoops (count) 235system.membus.snoop_fanout::samples 533 # Request fanout histogram 236system.membus.snoop_fanout::mean 0 # Request fanout histogram 237system.membus.snoop_fanout::stdev 0 # Request fanout histogram 238system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 239system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram 240system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 241system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 242system.membus.snoop_fanout::min_value 0 # Request fanout histogram 243system.membus.snoop_fanout::max_value 0 # Request fanout histogram 244system.membus.snoop_fanout::total 533 # Request fanout histogram |
| 237system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks) 238system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) 239system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks) 240system.membus.respLayer1.utilization 14.2 # Layer utilization (%) 241system.cpu_clk_domain.clock 500 # Clock period in ticks 242system.cpu.branchPred.lookups 1959 # Number of BP lookups 243system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted 244system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect --- 31 unchanged lines hidden (view full) --- 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_acv 0 # DTB write access violations 278system.cpu.itb.write_accesses 0 # DTB write accesses 279system.cpu.itb.data_hits 0 # DTB hits 280system.cpu.itb.data_misses 0 # DTB misses 281system.cpu.itb.data_acv 0 # DTB access violations 282system.cpu.itb.data_accesses 0 # DTB accesses 283system.cpu.workload.num_syscalls 17 # Number of system calls | 245system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks) 246system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) 247system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks) 248system.membus.respLayer1.utilization 14.2 # Layer utilization (%) 249system.cpu_clk_domain.clock 500 # Clock period in ticks 250system.cpu.branchPred.lookups 1959 # Number of BP lookups 251system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted 252system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect --- 31 unchanged lines hidden (view full) --- 284system.cpu.itb.write_misses 0 # DTB write misses 285system.cpu.itb.write_acv 0 # DTB write access violations 286system.cpu.itb.write_accesses 0 # DTB write accesses 287system.cpu.itb.data_hits 0 # DTB hits 288system.cpu.itb.data_misses 0 # DTB misses 289system.cpu.itb.data_acv 0 # DTB access violations 290system.cpu.itb.data_accesses 0 # DTB accesses 291system.cpu.workload.num_syscalls 17 # Number of system calls |
| 284system.cpu.numCycles 70031 # number of cpu cycles simulated | 292system.cpu.numCycles 70049 # number of cpu cycles simulated |
| 285system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 286system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 287system.cpu.committedInsts 6400 # Number of instructions committed 288system.cpu.committedOps 6400 # Number of ops (including micro ops) committed 289system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit 290system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 293system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 294system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 295system.cpu.committedInsts 6400 # Number of instructions committed 296system.cpu.committedOps 6400 # Number of ops (including micro ops) committed 297system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit 298system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 291system.cpu.cpi 10.942344 # CPI: cycles per instruction 292system.cpu.ipc 0.091388 # IPC: instructions per cycle 293system.cpu.tickCycles 12510 # Number of cycles that the object actually ticked 294system.cpu.idleCycles 57521 # Total number of cycles that the object has spent stopped | 299system.cpu.cpi 10.945156 # CPI: cycles per instruction 300system.cpu.ipc 0.091365 # IPC: instructions per cycle 301system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked 302system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped |
| 295system.cpu.icache.tags.replacements 0 # number of replacements | 303system.cpu.icache.tags.replacements 0 # number of replacements |
| 296system.cpu.icache.tags.tagsinuse 176.143820 # Cycle average of tags in use | 304system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use |
| 297system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. 298system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 299system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. 300system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 305system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. 306system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 307system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. 308system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 301system.cpu.icache.tags.occ_blocks::cpu.inst 176.143820 # Average occupied blocks per requestor 302system.cpu.icache.tags.occ_percent::cpu.inst 0.086008 # Average percentage of cache occupancy 303system.cpu.icache.tags.occ_percent::total 0.086008 # Average percentage of cache occupancy | 309system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor 310system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy 311system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy |
| 304system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 305system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 306system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 307system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id 308system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses 309system.cpu.icache.tags.data_accesses 5625 # Number of data accesses 310system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits 311system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits 312system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits 313system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits 314system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits 315system.cpu.icache.overall_hits::total 2265 # number of overall hits 316system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 317system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 318system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 319system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 320system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 321system.cpu.icache.overall_misses::total 365 # number of overall misses | 312system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 313system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 314system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 315system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id 316system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses 317system.cpu.icache.tags.data_accesses 5625 # Number of data accesses 318system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits 319system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits 320system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits 321system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits 322system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits 323system.cpu.icache.overall_hits::total 2265 # number of overall hits 324system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 325system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 326system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 327system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 328system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 329system.cpu.icache.overall_misses::total 365 # number of overall misses |
| 322system.cpu.icache.ReadReq_miss_latency::cpu.inst 25932750 # number of ReadReq miss cycles 323system.cpu.icache.ReadReq_miss_latency::total 25932750 # number of ReadReq miss cycles 324system.cpu.icache.demand_miss_latency::cpu.inst 25932750 # number of demand (read+write) miss cycles 325system.cpu.icache.demand_miss_latency::total 25932750 # number of demand (read+write) miss cycles 326system.cpu.icache.overall_miss_latency::cpu.inst 25932750 # number of overall miss cycles 327system.cpu.icache.overall_miss_latency::total 25932750 # number of overall miss cycles | 330system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles 331system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles 332system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles 333system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles 334system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles 335system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles |
| 328system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) 329system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) 330system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses 331system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses 332system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses 333system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses 334system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses 335system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses 336system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses 337system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses 338system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses 339system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses | 336system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) 337system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) 338system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses 339system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses 340system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses 341system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses 342system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses 343system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses 344system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses 345system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses 346system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses 347system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses |
| 340system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71048.630137 # average ReadReq miss latency 341system.cpu.icache.ReadReq_avg_miss_latency::total 71048.630137 # average ReadReq miss latency 342system.cpu.icache.demand_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency 343system.cpu.icache.demand_avg_miss_latency::total 71048.630137 # average overall miss latency 344system.cpu.icache.overall_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency 345system.cpu.icache.overall_avg_miss_latency::total 71048.630137 # average overall miss latency | 348system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency 349system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency 350system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency 351system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency 352system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency 353system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency |
| 346system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 347system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 348system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 351system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 352system.cpu.icache.fast_writes 0 # number of fast writes performed 353system.cpu.icache.cache_copies 0 # number of cache copies performed 354system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 355system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses 356system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 357system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 358system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 359system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses | 354system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 355system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 356system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 357system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 358system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 359system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 360system.cpu.icache.fast_writes 0 # number of fast writes performed 361system.cpu.icache.cache_copies 0 # number of cache copies performed 362system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 363system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses 364system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 365system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 366system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 367system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses |
| 360system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25045250 # number of ReadReq MSHR miss cycles 361system.cpu.icache.ReadReq_mshr_miss_latency::total 25045250 # number of ReadReq MSHR miss cycles 362system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25045250 # number of demand (read+write) MSHR miss cycles 363system.cpu.icache.demand_mshr_miss_latency::total 25045250 # number of demand (read+write) MSHR miss cycles 364system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25045250 # number of overall MSHR miss cycles 365system.cpu.icache.overall_mshr_miss_latency::total 25045250 # number of overall MSHR miss cycles | 368system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles 369system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles 370system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles 371system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles 372system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles 373system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles |
| 366system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses 367system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses 368system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses 369system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses 370system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses 371system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses | 374system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses 375system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses 376system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses 377system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses 378system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses 379system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses |
| 372system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68617.123288 # average ReadReq mshr miss latency 373system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68617.123288 # average ReadReq mshr miss latency 374system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency 375system.cpu.icache.demand_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency 376system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency 377system.cpu.icache.overall_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency | 380system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency 381system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency 382system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency 383system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency 384system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency 385system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency |
| 378system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 386system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 379system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s) | |
| 380system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution 381system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution 382system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 383system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 384system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 385system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 386system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) | 387system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution 388system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution 389system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 390system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 391system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 392system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 393system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) |
| 387system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) 388system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 389system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) 390system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes) 391system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 394system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) 395system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 396system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) 397system.cpu.toL2Bus.snoops 0 # Total snoops (count) 398system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram 399system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 400system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 401system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 402system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 403system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram 404system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 405system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 406system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 407system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 408system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram |
| 392system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) 393system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 394system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) 395system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 396system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) 397system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 398system.cpu.l2cache.tags.replacements 0 # number of replacements | 409system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) 410system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 411system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) 412system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 413system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) 414system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 415system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 399system.cpu.l2cache.tags.tagsinuse 233.878182 # Cycle average of tags in use | 416system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use |
| 400system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 401system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. 402system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. 403system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 417system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 418system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. 419system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. 420system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 404system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.878182 # Average occupied blocks per requestor 405system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy 406system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy | 421system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor 422system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy 423system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy |
| 407system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id 408system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 409system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 410system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id 411system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses 412system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses 413system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 414system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits --- 6 unchanged lines hidden (view full) --- 421system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses 422system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 423system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses 424system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses 425system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses 426system.cpu.l2cache.overall_misses::total 533 # number of overall misses 427system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles 428system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles | 424system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id 425system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 426system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 427system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id 428system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses 429system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses 430system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 431system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits --- 6 unchanged lines hidden (view full) --- 438system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses 439system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 440system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses 441system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses 442system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses 443system.cpu.l2cache.overall_misses::total 533 # number of overall misses 444system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles 445system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles |
| 429system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5056000 # number of ReadExReq miss cycles 430system.cpu.l2cache.ReadExReq_miss_latency::total 5056000 # number of ReadExReq miss cycles 431system.cpu.l2cache.demand_miss_latency::cpu.inst 36782750 # number of demand (read+write) miss cycles 432system.cpu.l2cache.demand_miss_latency::total 36782750 # number of demand (read+write) miss cycles 433system.cpu.l2cache.overall_miss_latency::cpu.inst 36782750 # number of overall miss cycles 434system.cpu.l2cache.overall_miss_latency::total 36782750 # number of overall miss cycles | 446system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles 447system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles 448system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles 449system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles 450system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles 451system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles |
| 435system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) 436system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) 437system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) 438system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 439system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses 440system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses 441system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses 442system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses 443system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses 444system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses 445system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 446system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 447system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses 448system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses 449system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses 450system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses 451system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency 452system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency | 452system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) 453system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) 454system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) 455system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 456system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses 457system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses 458system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses 459system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses 460system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses 461system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses 462system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 463system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 464system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses 465system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses 466system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses 467system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses 468system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency 469system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency |
| 453system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69260.273973 # average ReadExReq miss latency 454system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69260.273973 # average ReadExReq miss latency 455system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency 456system.cpu.l2cache.demand_avg_miss_latency::total 69010.787992 # average overall miss latency 457system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency 458system.cpu.l2cache.overall_avg_miss_latency::total 69010.787992 # average overall miss latency | 470system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency 471system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency 472system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency 473system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency 474system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency 475system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency |
| 459system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 460system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 461system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 462system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 463system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 464system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 465system.cpu.l2cache.fast_writes 0 # number of fast writes performed 466system.cpu.l2cache.cache_copies 0 # number of cache copies performed 467system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses 468system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses 469system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses 470system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 471system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses 472system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses 473system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses 474system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses | 476system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 477system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 478system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 479system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 480system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 481system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 482system.cpu.l2cache.fast_writes 0 # number of fast writes performed 483system.cpu.l2cache.cache_copies 0 # number of cache copies performed 484system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses 485system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses 486system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses 487system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 488system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses 489system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses 490system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses 491system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses |
| 475system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25965250 # number of ReadReq MSHR miss cycles 476system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25965250 # number of ReadReq MSHR miss cycles 477system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles 478system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles 479system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30103250 # number of demand (read+write) MSHR miss cycles 480system.cpu.l2cache.demand_mshr_miss_latency::total 30103250 # number of demand (read+write) MSHR miss cycles 481system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30103250 # number of overall MSHR miss cycles 482system.cpu.l2cache.overall_mshr_miss_latency::total 30103250 # number of overall MSHR miss cycles | 492system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles 493system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles 494system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles 495system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles 496system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles 497system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles 498system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles 499system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles |
| 483system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses 484system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses 485system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 486system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 487system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses 488system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses 489system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses 490system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses | 500system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses 501system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses 502system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 503system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 504system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses 505system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses 506system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses 507system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses |
| 491system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652 # average ReadReq mshr miss latency 492system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652 # average ReadReq mshr miss latency 493system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency 494system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency 495system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency 496system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency 497system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency 498system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency | 508system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency 509system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency 510system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency 511system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency 512system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency 513system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency 514system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency 515system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency |
| 499system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 500system.cpu.dcache.tags.replacements 0 # number of replacements | 516system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 517system.cpu.dcache.tags.replacements 0 # number of replacements |
| 501system.cpu.dcache.tags.tagsinuse 104.053835 # Cycle average of tags in use | 518system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use |
| 502system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. 503system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 504system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. 505system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 519system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. 520system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 521system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. 522system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 506system.cpu.dcache.tags.occ_blocks::cpu.inst 104.053835 # Average occupied blocks per requestor 507system.cpu.dcache.tags.occ_percent::cpu.inst 0.025404 # Average percentage of cache occupancy 508system.cpu.dcache.tags.occ_percent::total 0.025404 # Average percentage of cache occupancy | 523system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor 524system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy 525system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy |
| 509system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 510system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 511system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 512system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 513system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses 514system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses 515system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits 516system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits --- 6 unchanged lines hidden (view full) --- 523system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses 524system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses 525system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses 526system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 527system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 528system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses 529system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses 530system.cpu.dcache.overall_misses::total 227 # number of overall misses | 526system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 527system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 528system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 529system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 530system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses 531system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses 532system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits 533system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits --- 6 unchanged lines hidden (view full) --- 540system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses 541system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses 542system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses 543system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 544system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 545system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses 546system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses 547system.cpu.dcache.overall_misses::total 227 # number of overall misses |
| 531system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7727250 # number of ReadReq miss cycles 532system.cpu.dcache.ReadReq_miss_latency::total 7727250 # number of ReadReq miss cycles 533system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8696750 # number of WriteReq miss cycles 534system.cpu.dcache.WriteReq_miss_latency::total 8696750 # number of WriteReq miss cycles | 548system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles 549system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles 550system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles 551system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles |
| 535system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles 536system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles 537system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles 538system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles 539system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses) 540system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses) 541system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) 542system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 547system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses 548system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses 549system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses 550system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 551system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses 552system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses 553system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses 554system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses | 552system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles 553system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles 554system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles 555system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles 556system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses) 557system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses) 558system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) 559system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 564system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses 565system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses 566system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses 567system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 568system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses 569system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses 570system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses 571system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses |
| 555system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941 # average ReadReq miss latency 556system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941 # average ReadReq miss latency 557system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69574 # average WriteReq miss latency 558system.cpu.dcache.WriteReq_avg_miss_latency::total 69574 # average WriteReq miss latency | 572system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency 573system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency 574system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency 575system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency |
| 559system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency 560system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency 561system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency 562system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency 563system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 564system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 565system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 566system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked --- 12 unchanged lines hidden (view full) --- 579system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses 580system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 581system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses 582system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 583system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses 584system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 585system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses 586system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses | 576system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency 577system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency 578system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency 579system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency 580system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 581system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 582system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 583system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked --- 12 unchanged lines hidden (view full) --- 596system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses 597system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 598system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses 599system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 600system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses 601system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 602system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses 603system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses |
| 587system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7154500 # number of ReadReq MSHR miss cycles 588system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154500 # number of ReadReq MSHR miss cycles 589system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5130500 # number of WriteReq MSHR miss cycles 590system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130500 # number of WriteReq MSHR miss cycles | 604system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles 605system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles 606system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles 607system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles |
| 591system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles 592system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles 593system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles 594system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles 595system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses 596system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses 597system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses 598system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 599system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses 600system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses 601system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses 602system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses | 608system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles 609system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles 610system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles 611system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles 612system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses 613system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses 614system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses 615system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 616system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses 617system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses 618system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses 619system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses |
| 603system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667 # average ReadReq mshr miss latency 604system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667 # average ReadReq mshr miss latency 605system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918 # average WriteReq mshr miss latency 606system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918 # average WriteReq mshr miss latency | 620system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency 621system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency 622system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency 623system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency |
| 607system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency 608system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency 609system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency 610system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency 611system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 612 613---------- End Simulation Statistics ---------- | 624system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency 625system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency 626system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency 627system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency 628system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 629 630---------- End Simulation Statistics ---------- |