| stats.txt (10260:384d554cea8c) | stats.txt (10261:dc198e224a85) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000035 # Number of seconds simulated 4sim_ticks 35015500 # Number of ticks simulated |
|
| 3final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 5final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 4host_inst_rate 59280 # Simulator instruction rate (inst/s) 5host_mem_usage 248380 # Number of bytes of host memory used 6host_op_rate 59280 # Simulator op (including micro ops) rate (op/s) 7host_seconds 0.11 # Real time elapsed on the host 8host_tick_rate 324332505 # Simulator tick rate (ticks/s) | |
| 9sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 57020 # Simulator instruction rate (inst/s) 8host_op_rate 57008 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 311836228 # Simulator tick rate (ticks/s) 10host_mem_usage 240292 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host |
|
| 10sim_insts 6400 # Number of instructions simulated 11sim_ops 6400 # Number of ops (including micro ops) simulated | 12sim_insts 6400 # Number of instructions simulated 13sim_ops 6400 # Number of ops (including micro ops) simulated |
| 12sim_seconds 0.000035 # Number of seconds simulated 13sim_ticks 35015500 # Number of ticks simulated | 14system.voltage_domain.voltage 1 # Voltage in Volts |
| 14system.clk_domain.clock 1000 # Clock period in ticks | 15system.clk_domain.clock 1000 # Clock period in ticks |
| 15system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 16system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage 17system.cpu.branchPred.BTBHits 381 # Number of BTB hits 18system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups 19system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. 20system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect 21system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted 22system.cpu.branchPred.lookups 1959 # Number of BP lookups 23system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. 24system.cpu.committedInsts 6400 # Number of instructions committed 25system.cpu.committedOps 6400 # Number of ops (including micro ops) committed 26system.cpu.cpi 10.942344 # CPI: cycles per instruction 27system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses) 28system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses) 29system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 78029.411765 # average ReadReq miss latency 30system.cpu.dcache.ReadReq_avg_miss_latency::total 78029.411765 # average ReadReq miss latency 31system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 76945.312500 # average ReadReq mshr miss latency 32system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76945.312500 # average ReadReq mshr miss latency 33system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits 34system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits 35system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7959000 # number of ReadReq miss cycles 36system.cpu.dcache.ReadReq_miss_latency::total 7959000 # number of ReadReq miss cycles 37system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses 38system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses 39system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses 40system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses 41system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 42system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 43system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7386750 # number of ReadReq MSHR miss cycles 44system.cpu.dcache.ReadReq_mshr_miss_latency::total 7386750 # number of ReadReq MSHR miss cycles 45system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses 46system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses 47system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses 48system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 49system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) 50system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 51system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69500 # average WriteReq miss latency 52system.cpu.dcache.WriteReq_avg_miss_latency::total 69500 # average WriteReq miss latency 53system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70147.260274 # average WriteReq mshr miss latency 54system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70147.260274 # average WriteReq mshr miss latency 55system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits 56system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 57system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8687500 # number of WriteReq miss cycles 58system.cpu.dcache.WriteReq_miss_latency::total 8687500 # number of WriteReq miss cycles 59system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses 60system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 61system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses 62system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 63system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits 64system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 65system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5120750 # number of WriteReq MSHR miss cycles 66system.cpu.dcache.WriteReq_mshr_miss_latency::total 5120750 # number of WriteReq MSHR miss cycles 67system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses 68system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses 70system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 71system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 72system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 73system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 74system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 75system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 76system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 77system.cpu.dcache.cache_copies 0 # number of cache copies performed 78system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses 79system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses 80system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73332.599119 # average overall miss latency 81system.cpu.dcache.demand_avg_miss_latency::total 73332.599119 # average overall miss latency 82system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 74008.875740 # average overall mshr miss latency 83system.cpu.dcache.demand_avg_mshr_miss_latency::total 74008.875740 # average overall mshr miss latency 84system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits 85system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits 86system.cpu.dcache.demand_miss_latency::cpu.inst 16646500 # number of demand (read+write) miss cycles 87system.cpu.dcache.demand_miss_latency::total 16646500 # number of demand (read+write) miss cycles 88system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses 89system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses 90system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 91system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses 92system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits 93system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits 94system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12507500 # number of demand (read+write) MSHR miss cycles 95system.cpu.dcache.demand_mshr_miss_latency::total 12507500 # number of demand (read+write) MSHR miss cycles 96system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses 97system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses 98system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses 99system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 100system.cpu.dcache.fast_writes 0 # number of fast writes performed 101system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 102system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses 103system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses 104system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73332.599119 # average overall miss latency 105system.cpu.dcache.overall_avg_miss_latency::total 73332.599119 # average overall miss latency 106system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 74008.875740 # average overall mshr miss latency 107system.cpu.dcache.overall_avg_mshr_miss_latency::total 74008.875740 # average overall mshr miss latency 108system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits 109system.cpu.dcache.overall_hits::total 1968 # number of overall hits 110system.cpu.dcache.overall_miss_latency::cpu.inst 16646500 # number of overall miss cycles 111system.cpu.dcache.overall_miss_latency::total 16646500 # number of overall miss cycles 112system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses 113system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses 114system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses 115system.cpu.dcache.overall_misses::total 227 # number of overall misses 116system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits 117system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits 118system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12507500 # number of overall MSHR miss cycles 119system.cpu.dcache.overall_mshr_miss_latency::total 12507500 # number of overall MSHR miss cycles 120system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses 121system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses 122system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses 123system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses 124system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 125system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 126system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. 127system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses 128system.cpu.dcache.tags.occ_blocks::cpu.inst 103.870916 # Average occupied blocks per requestor 129system.cpu.dcache.tags.occ_percent::cpu.inst 0.025359 # Average percentage of cache occupancy 130system.cpu.dcache.tags.occ_percent::total 0.025359 # Average percentage of cache occupancy 131system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 132system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 133system.cpu.dcache.tags.replacements 0 # number of replacements 134system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 135system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses 136system.cpu.dcache.tags.tagsinuse 103.870916 # Cycle average of tags in use 137system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. 138system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 139system.cpu.discardedOps 1111 # Number of ops (including micro ops) which were discarded before commit 140system.cpu.dtb.data_accesses 2266 # DTB accesses 141system.cpu.dtb.data_acv 0 # DTB access violations 142system.cpu.dtb.data_hits 2252 # DTB hits 143system.cpu.dtb.data_misses 14 # DTB misses 144system.cpu.dtb.fetch_accesses 0 # ITB accesses 145system.cpu.dtb.fetch_acv 0 # ITB acv 146system.cpu.dtb.fetch_hits 0 # ITB hits 147system.cpu.dtb.fetch_misses 0 # ITB misses 148system.cpu.dtb.read_accesses 1379 # DTB read accesses 149system.cpu.dtb.read_acv 0 # DTB read access violations 150system.cpu.dtb.read_hits 1368 # DTB read hits 151system.cpu.dtb.read_misses 11 # DTB read misses 152system.cpu.dtb.write_accesses 887 # DTB write accesses 153system.cpu.dtb.write_acv 0 # DTB write access violations 154system.cpu.dtb.write_hits 884 # DTB write hits 155system.cpu.dtb.write_misses 3 # DTB write misses 156system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) 157system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) 158system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70238.356164 # average ReadReq miss latency 159system.cpu.icache.ReadReq_avg_miss_latency::total 70238.356164 # average ReadReq miss latency 160system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67805.479452 # average ReadReq mshr miss latency 161system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67805.479452 # average ReadReq mshr miss latency 162system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits 163system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits 164system.cpu.icache.ReadReq_miss_latency::cpu.inst 25637000 # number of ReadReq miss cycles 165system.cpu.icache.ReadReq_miss_latency::total 25637000 # number of ReadReq miss cycles 166system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses 167system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses 168system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 169system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 170system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24749000 # number of ReadReq MSHR miss cycles 171system.cpu.icache.ReadReq_mshr_miss_latency::total 24749000 # number of ReadReq MSHR miss cycles 172system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses 173system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses 174system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 175system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses 176system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 177system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 178system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 179system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 180system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 181system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182system.cpu.icache.cache_copies 0 # number of cache copies performed 183system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses 184system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses 185system.cpu.icache.demand_avg_miss_latency::cpu.inst 70238.356164 # average overall miss latency 186system.cpu.icache.demand_avg_miss_latency::total 70238.356164 # average overall miss latency 187system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67805.479452 # average overall mshr miss latency 188system.cpu.icache.demand_avg_mshr_miss_latency::total 67805.479452 # average overall mshr miss latency 189system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits 190system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits 191system.cpu.icache.demand_miss_latency::cpu.inst 25637000 # number of demand (read+write) miss cycles 192system.cpu.icache.demand_miss_latency::total 25637000 # number of demand (read+write) miss cycles 193system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses 194system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses 195system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 196system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 197system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24749000 # number of demand (read+write) MSHR miss cycles 198system.cpu.icache.demand_mshr_miss_latency::total 24749000 # number of demand (read+write) MSHR miss cycles 199system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses 200system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses 201system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 202system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 203system.cpu.icache.fast_writes 0 # number of fast writes performed 204system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 205system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses 206system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses 207system.cpu.icache.overall_avg_miss_latency::cpu.inst 70238.356164 # average overall miss latency 208system.cpu.icache.overall_avg_miss_latency::total 70238.356164 # average overall miss latency 209system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67805.479452 # average overall mshr miss latency 210system.cpu.icache.overall_avg_mshr_miss_latency::total 67805.479452 # average overall mshr miss latency 211system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits 212system.cpu.icache.overall_hits::total 2265 # number of overall hits 213system.cpu.icache.overall_miss_latency::cpu.inst 25637000 # number of overall miss cycles 214system.cpu.icache.overall_miss_latency::total 25637000 # number of overall miss cycles 215system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses 216system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses 217system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 218system.cpu.icache.overall_misses::total 365 # number of overall misses 219system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24749000 # number of overall MSHR miss cycles 220system.cpu.icache.overall_mshr_miss_latency::total 24749000 # number of overall MSHR miss cycles 221system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses 222system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses 223system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 224system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses 225system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 226system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 227system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. 228system.cpu.icache.tags.data_accesses 5625 # Number of data accesses 229system.cpu.icache.tags.occ_blocks::cpu.inst 175.902434 # Average occupied blocks per requestor 230system.cpu.icache.tags.occ_percent::cpu.inst 0.085890 # Average percentage of cache occupancy 231system.cpu.icache.tags.occ_percent::total 0.085890 # Average percentage of cache occupancy 232system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 233system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id 234system.cpu.icache.tags.replacements 0 # number of replacements 235system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 236system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses 237system.cpu.icache.tags.tagsinuse 175.902434 # Cycle average of tags in use 238system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. 239system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 240system.cpu.idleCycles 57521 # Total number of cycles that the CPU has spent unscheduled due to idling 241system.cpu.ipc 0.091388 # IPC: instructions per cycle 242system.cpu.itb.data_accesses 0 # DTB accesses 243system.cpu.itb.data_acv 0 # DTB access violations 244system.cpu.itb.data_hits 0 # DTB hits 245system.cpu.itb.data_misses 0 # DTB misses 246system.cpu.itb.fetch_accesses 2647 # ITB accesses 247system.cpu.itb.fetch_acv 0 # ITB acv 248system.cpu.itb.fetch_hits 2630 # ITB hits 249system.cpu.itb.fetch_misses 17 # ITB misses 250system.cpu.itb.read_accesses 0 # DTB read accesses 251system.cpu.itb.read_acv 0 # DTB read access violations 252system.cpu.itb.read_hits 0 # DTB read hits 253system.cpu.itb.read_misses 0 # DTB read misses 254system.cpu.itb.write_accesses 0 # DTB write accesses 255system.cpu.itb.write_acv 0 # DTB write access violations 256system.cpu.itb.write_hits 0 # DTB write hits 257system.cpu.itb.write_misses 0 # DTB write misses 258system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) 259system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 260system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69126.712329 # average ReadExReq miss latency 261system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69126.712329 # average ReadExReq miss latency 262system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56544.520548 # average ReadExReq mshr miss latency 263system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56544.520548 # average ReadExReq mshr miss latency 264system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5046250 # number of ReadExReq miss cycles 265system.cpu.l2cache.ReadExReq_miss_latency::total 5046250 # number of ReadExReq miss cycles 266system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 267system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 268system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses 269system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 270system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4127750 # number of ReadExReq MSHR miss cycles 271system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4127750 # number of ReadExReq MSHR miss cycles 272system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 273system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 274system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses 275system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 276system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) 277system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) 278system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68832.065217 # average ReadReq miss latency 279system.cpu.l2cache.ReadReq_avg_miss_latency::total 68832.065217 # average ReadReq miss latency 280system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56304.891304 # average ReadReq mshr miss latency 281system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56304.891304 # average ReadReq mshr miss latency 282system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 283system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 284system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31662750 # number of ReadReq miss cycles 285system.cpu.l2cache.ReadReq_miss_latency::total 31662750 # number of ReadReq miss cycles 286system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses 287system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses 288system.cpu.l2cache.ReadReq_misses::cpu.inst 460 # number of ReadReq misses 289system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses 290system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25900250 # number of ReadReq MSHR miss cycles 291system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25900250 # number of ReadReq MSHR miss cycles 292system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses 293system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses 294system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses 295system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses 296system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 298system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 299system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 300system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 301system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 302system.cpu.l2cache.cache_copies 0 # number of cache copies performed 303system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses 304system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses 305system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68872.420263 # average overall miss latency 306system.cpu.l2cache.demand_avg_miss_latency::total 68872.420263 # average overall miss latency 307system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56337.711069 # average overall mshr miss latency 308system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56337.711069 # average overall mshr miss latency 309system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 310system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 311system.cpu.l2cache.demand_miss_latency::cpu.inst 36709000 # number of demand (read+write) miss cycles 312system.cpu.l2cache.demand_miss_latency::total 36709000 # number of demand (read+write) miss cycles 313system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses 314system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses 315system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses 316system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses 317system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30028000 # number of demand (read+write) MSHR miss cycles 318system.cpu.l2cache.demand_mshr_miss_latency::total 30028000 # number of demand (read+write) MSHR miss cycles 319system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses 320system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses 321system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses 322system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses 323system.cpu.l2cache.fast_writes 0 # number of fast writes performed 324system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 325system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses 326system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses 327system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68872.420263 # average overall miss latency 328system.cpu.l2cache.overall_avg_miss_latency::total 68872.420263 # average overall miss latency 329system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56337.711069 # average overall mshr miss latency 330system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56337.711069 # average overall mshr miss latency 331system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 332system.cpu.l2cache.overall_hits::total 1 # number of overall hits 333system.cpu.l2cache.overall_miss_latency::cpu.inst 36709000 # number of overall miss cycles 334system.cpu.l2cache.overall_miss_latency::total 36709000 # number of overall miss cycles 335system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses 336system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses 337system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses 338system.cpu.l2cache.overall_misses::total 533 # number of overall misses 339system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30028000 # number of overall MSHR miss cycles 340system.cpu.l2cache.overall_mshr_miss_latency::total 30028000 # number of overall MSHR miss cycles 341system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses 342system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses 343system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses 344system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses 345system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 346system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 347system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. 348system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses 349system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.550813 # Average occupied blocks per requestor 350system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007127 # Average percentage of cache occupancy 351system.cpu.l2cache.tags.occ_percent::total 0.007127 # Average percentage of cache occupancy 352system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id 353system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id 354system.cpu.l2cache.tags.replacements 0 # number of replacements 355system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. 356system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses 357system.cpu.l2cache.tags.tagsinuse 233.550813 # Cycle average of tags in use 358system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 359system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 360system.cpu.numCycles 70031 # number of cpu cycles simulated 361system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 362system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 364system.cpu.tickCycles 12510 # Number of cycles that the CPU actually ticked 365system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes) 366system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 367system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 368system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) 369system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) 370system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 371system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) 372system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 373system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) 374system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 375system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 376system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s) 377system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) 378system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 379system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) 380system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution 381system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution 382system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 383system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 384system.cpu.workload.num_syscalls 17 # Number of system calls 385system.cpu_clk_domain.clock 500 # Clock period in ticks 386system.membus.data_through_bus 34112 # Total data (bytes) 387system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) 388system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) 389system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) 390system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) 391system.membus.respLayer1.occupancy 4977500 # Layer occupancy (ticks) 392system.membus.respLayer1.utilization 14.2 # Layer utilization (%) 393system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 394system.membus.throughput 974197141 # Throughput (bytes/s) 395system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) 396system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 397system.membus.trans_dist::ReadReq 460 # Transaction distribution 398system.membus.trans_dist::ReadResp 460 # Transaction distribution 399system.membus.trans_dist::ReadExReq 73 # Transaction distribution 400system.membus.trans_dist::ReadExResp 73 # Transaction distribution 401system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 402system.physmem.avgGap 65510.32 # Average gap between requests 403system.physmem.avgMemAccLat 25799.25 # Average memory access latency per DRAM burst 404system.physmem.avgQLat 7049.25 # Average queueing delay per DRAM burst 405system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s 406system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s 407system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 408system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 409system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 410system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 411system.physmem.busUtil 7.61 # Data bus utilization in percentage 412system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads 413system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 414system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s) 415system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s) | 16system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory 17system.physmem.bytes_read::total 34112 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 533 # Number of read requests responded to by this memory |
| 416system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s) 417system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s) |
| 24system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s) |
|
| 418system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s) 419system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s) | 26system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s) |
| 420system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation 421system.physmem.bytesPerActivate::mean 369.617978 # Bytes accessed per row activation 422system.physmem.bytesPerActivate::gmean 234.259007 # Bytes accessed per row activation 423system.physmem.bytesPerActivate::stdev 335.584548 # Bytes accessed per row activation 424system.physmem.bytesPerActivate::0-127 22 24.72% 24.72% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::128-255 23 25.84% 50.56% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::256-383 10 11.24% 61.80% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::384-511 8 8.99% 70.79% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::512-639 4 4.49% 75.28% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::640-767 6 6.74% 82.02% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::768-895 2 2.25% 84.27% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::896-1023 4 4.49% 88.76% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation | 28system.physmem.readReqs 533 # Number of read requests accepted 29system.physmem.writeReqs 0 # Number of write requests accepted 30system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 434system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM | 32system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM |
| 435system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side | |
| 436system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 437system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 35system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side |
|
| 438system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side | 36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side |
| 439system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory 440system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory 441system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory 442system.physmem.bytes_read::total 34112 # Number of bytes read from this memory 443system.physmem.memoryStateTime::IDLE 15500 # Time in different power states 444system.physmem.memoryStateTime::REF 1040000 # Time in different power states 445system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 446system.physmem.memoryStateTime::ACT 30385500 # Time in different power states 447system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue |
| 448system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 449system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 450system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 451system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 452system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory 453system.physmem.num_reads::total 533 # Number of read requests responded to by this memory 454system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined 455system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | |
| 456system.physmem.perBankRdBursts::0 73 # Per bank write bursts 457system.physmem.perBankRdBursts::1 39 # Per bank write bursts 458system.physmem.perBankRdBursts::2 36 # Per bank write bursts 459system.physmem.perBankRdBursts::3 54 # Per bank write bursts 460system.physmem.perBankRdBursts::4 45 # Per bank write bursts 461system.physmem.perBankRdBursts::5 21 # Per bank write bursts 462system.physmem.perBankRdBursts::6 1 # Per bank write bursts 463system.physmem.perBankRdBursts::7 5 # Per bank write bursts --- 16 unchanged lines hidden (view full) --- 480system.physmem.perBankWrBursts::8 0 # Per bank write bursts 481system.physmem.perBankWrBursts::9 0 # Per bank write bursts 482system.physmem.perBankWrBursts::10 0 # Per bank write bursts 483system.physmem.perBankWrBursts::11 0 # Per bank write bursts 484system.physmem.perBankWrBursts::12 0 # Per bank write bursts 485system.physmem.perBankWrBursts::13 0 # Per bank write bursts 486system.physmem.perBankWrBursts::14 0 # Per bank write bursts 487system.physmem.perBankWrBursts::15 0 # Per bank write bursts | 40system.physmem.perBankRdBursts::0 73 # Per bank write bursts 41system.physmem.perBankRdBursts::1 39 # Per bank write bursts 42system.physmem.perBankRdBursts::2 36 # Per bank write bursts 43system.physmem.perBankRdBursts::3 54 # Per bank write bursts 44system.physmem.perBankRdBursts::4 45 # Per bank write bursts 45system.physmem.perBankRdBursts::5 21 # Per bank write bursts 46system.physmem.perBankRdBursts::6 1 # Per bank write bursts 47system.physmem.perBankRdBursts::7 5 # Per bank write bursts --- 16 unchanged lines hidden (view full) --- 64system.physmem.perBankWrBursts::8 0 # Per bank write bursts 65system.physmem.perBankWrBursts::9 0 # Per bank write bursts 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts |
| 488system.physmem.rdQLenPdf::0 440 # What read queue length does an incoming req see 489system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see | 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 74system.physmem.totGap 34917000 # Total gap between requests 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) 81system.physmem.readPktSize::6 533 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) 83system.physmem.writePktSize::1 0 # Write request sizes (log2) 84system.physmem.writePktSize::2 0 # Write request sizes (log2) 85system.physmem.writePktSize::3 0 # Write request sizes (log2) 86system.physmem.writePktSize::4 0 # Write request sizes (log2) 87system.physmem.writePktSize::5 0 # Write request sizes (log2) 88system.physmem.writePktSize::6 0 # Write request sizes (log2) 89system.physmem.rdQLenPdf::0 439 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 89 # What read queue length does an incoming req see |
| 490system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see 491system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 492system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 493system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 494system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 495system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 496system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 497system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 512system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 513system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 514system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 515system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 516system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 517system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 518system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 519system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 91system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 113system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 520system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue 521system.physmem.readPktSize::0 0 # Read request sizes (log2) 522system.physmem.readPktSize::1 0 # Read request sizes (log2) 523system.physmem.readPktSize::2 0 # Read request sizes (log2) 524system.physmem.readPktSize::3 0 # Read request sizes (log2) 525system.physmem.readPktSize::4 0 # Read request sizes (log2) 526system.physmem.readPktSize::5 0 # Read request sizes (log2) 527system.physmem.readPktSize::6 533 # Read request sizes (log2) 528system.physmem.readReqs 533 # Number of read requests accepted 529system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads 530system.physmem.readRowHits 436 # Number of row buffer hits during reads 531system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 532system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers 533system.physmem.totGap 34917000 # Total gap between requests 534system.physmem.totMemAccLat 13751000 # Total ticks spent from burst creation until serviced by the DRAM 535system.physmem.totQLat 3757250 # Total ticks spent queuing | |
| 536system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 537system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 538system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 539system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 540system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 541system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 542system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 543system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 48 unchanged lines hidden (view full) --- 592system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 593system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 594system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 595system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 596system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 597system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 598system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 599system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 121system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 48 unchanged lines hidden (view full) --- 177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 600system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 601system.physmem.writePktSize::0 0 # Write request sizes (log2) 602system.physmem.writePktSize::1 0 # Write request sizes (log2) 603system.physmem.writePktSize::2 0 # Write request sizes (log2) 604system.physmem.writePktSize::3 0 # Write request sizes (log2) 605system.physmem.writePktSize::4 0 # Write request sizes (log2) 606system.physmem.writePktSize::5 0 # Write request sizes (log2) 607system.physmem.writePktSize::6 0 # Write request sizes (log2) 608system.physmem.writeReqs 0 # Number of write requests accepted 609system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 185system.physmem.bytesPerActivate::samples 90 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::mean 365.511111 # Bytes accessed per row activation 187system.physmem.bytesPerActivate::gmean 232.220198 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::stdev 333.209697 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::0-127 22 24.44% 24.44% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::128-255 24 26.67% 51.11% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation 199system.physmem.totQLat 3823500 # Total ticks spent queuing 200system.physmem.totMemAccLat 13817250 # Total ticks spent from burst creation until serviced by the DRAM 201system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers 202system.physmem.avgQLat 7173.55 # Average queueing delay per DRAM burst 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 204system.physmem.avgMemAccLat 25923.55 # Average memory access latency per DRAM burst 205system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 7.61 # Data bus utilization in percentage 211system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 215system.physmem.readRowHits 435 # Number of row buffer hits during reads |
| 610system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 611system.voltage_domain.voltage 1 # Voltage in Volts | 217system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 65510.32 # Average gap between requests 220system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 15500 # Time in different power states 222system.physmem.memoryStateTime::REF 1040000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 224system.physmem.memoryStateTime::ACT 30385500 # Time in different power states 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 226system.membus.throughput 974197141 # Throughput (bytes/s) 227system.membus.trans_dist::ReadReq 460 # Transaction distribution 228system.membus.trans_dist::ReadResp 460 # Transaction distribution 229system.membus.trans_dist::ReadExReq 73 # Transaction distribution 230system.membus.trans_dist::ReadExResp 73 # Transaction distribution 231system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) 232system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) 233system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) 234system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 235system.membus.data_through_bus 34112 # Total data (bytes) 236system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 237system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks) 238system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) 239system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks) 240system.membus.respLayer1.utilization 14.2 # Layer utilization (%) 241system.cpu_clk_domain.clock 500 # Clock period in ticks 242system.cpu.branchPred.lookups 1959 # Number of BP lookups 243system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted 244system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect 245system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups 246system.cpu.branchPred.BTBHits 381 # Number of BTB hits 247system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 248system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage 249system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. 250system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. 251system.cpu.dtb.fetch_hits 0 # ITB hits 252system.cpu.dtb.fetch_misses 0 # ITB misses 253system.cpu.dtb.fetch_acv 0 # ITB acv 254system.cpu.dtb.fetch_accesses 0 # ITB accesses 255system.cpu.dtb.read_hits 1368 # DTB read hits 256system.cpu.dtb.read_misses 11 # DTB read misses 257system.cpu.dtb.read_acv 0 # DTB read access violations 258system.cpu.dtb.read_accesses 1379 # DTB read accesses 259system.cpu.dtb.write_hits 884 # DTB write hits 260system.cpu.dtb.write_misses 3 # DTB write misses 261system.cpu.dtb.write_acv 0 # DTB write access violations 262system.cpu.dtb.write_accesses 887 # DTB write accesses 263system.cpu.dtb.data_hits 2252 # DTB hits 264system.cpu.dtb.data_misses 14 # DTB misses 265system.cpu.dtb.data_acv 0 # DTB access violations 266system.cpu.dtb.data_accesses 2266 # DTB accesses 267system.cpu.itb.fetch_hits 2630 # ITB hits 268system.cpu.itb.fetch_misses 17 # ITB misses 269system.cpu.itb.fetch_acv 0 # ITB acv 270system.cpu.itb.fetch_accesses 2647 # ITB accesses 271system.cpu.itb.read_hits 0 # DTB read hits 272system.cpu.itb.read_misses 0 # DTB read misses 273system.cpu.itb.read_acv 0 # DTB read access violations 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_acv 0 # DTB write access violations 278system.cpu.itb.write_accesses 0 # DTB write accesses 279system.cpu.itb.data_hits 0 # DTB hits 280system.cpu.itb.data_misses 0 # DTB misses 281system.cpu.itb.data_acv 0 # DTB access violations 282system.cpu.itb.data_accesses 0 # DTB accesses 283system.cpu.workload.num_syscalls 17 # Number of system calls 284system.cpu.numCycles 70031 # number of cpu cycles simulated 285system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 286system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 287system.cpu.committedInsts 6400 # Number of instructions committed 288system.cpu.committedOps 6400 # Number of ops (including micro ops) committed 289system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit 290system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 291system.cpu.cpi 10.942344 # CPI: cycles per instruction 292system.cpu.ipc 0.091388 # IPC: instructions per cycle 293system.cpu.tickCycles 12510 # Number of cycles that the object actually ticked 294system.cpu.idleCycles 57521 # Total number of cycles that the object has spent stopped 295system.cpu.icache.tags.replacements 0 # number of replacements 296system.cpu.icache.tags.tagsinuse 176.143820 # Cycle average of tags in use 297system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. 298system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 299system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. 300system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 301system.cpu.icache.tags.occ_blocks::cpu.inst 176.143820 # Average occupied blocks per requestor 302system.cpu.icache.tags.occ_percent::cpu.inst 0.086008 # Average percentage of cache occupancy 303system.cpu.icache.tags.occ_percent::total 0.086008 # Average percentage of cache occupancy 304system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 305system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 306system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 307system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id 308system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses 309system.cpu.icache.tags.data_accesses 5625 # Number of data accesses 310system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits 311system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits 312system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits 313system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits 314system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits 315system.cpu.icache.overall_hits::total 2265 # number of overall hits 316system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 317system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 318system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 319system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 320system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 321system.cpu.icache.overall_misses::total 365 # number of overall misses 322system.cpu.icache.ReadReq_miss_latency::cpu.inst 25932750 # number of ReadReq miss cycles 323system.cpu.icache.ReadReq_miss_latency::total 25932750 # number of ReadReq miss cycles 324system.cpu.icache.demand_miss_latency::cpu.inst 25932750 # number of demand (read+write) miss cycles 325system.cpu.icache.demand_miss_latency::total 25932750 # number of demand (read+write) miss cycles 326system.cpu.icache.overall_miss_latency::cpu.inst 25932750 # number of overall miss cycles 327system.cpu.icache.overall_miss_latency::total 25932750 # number of overall miss cycles 328system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) 329system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) 330system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses 331system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses 332system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses 333system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses 334system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses 335system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses 336system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses 337system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses 338system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses 339system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses 340system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71048.630137 # average ReadReq miss latency 341system.cpu.icache.ReadReq_avg_miss_latency::total 71048.630137 # average ReadReq miss latency 342system.cpu.icache.demand_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency 343system.cpu.icache.demand_avg_miss_latency::total 71048.630137 # average overall miss latency 344system.cpu.icache.overall_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency 345system.cpu.icache.overall_avg_miss_latency::total 71048.630137 # average overall miss latency 346system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 347system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 348system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 351system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 352system.cpu.icache.fast_writes 0 # number of fast writes performed 353system.cpu.icache.cache_copies 0 # number of cache copies performed 354system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 355system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses 356system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 357system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 358system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 359system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses 360system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25045250 # number of ReadReq MSHR miss cycles 361system.cpu.icache.ReadReq_mshr_miss_latency::total 25045250 # number of ReadReq MSHR miss cycles 362system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25045250 # number of demand (read+write) MSHR miss cycles 363system.cpu.icache.demand_mshr_miss_latency::total 25045250 # number of demand (read+write) MSHR miss cycles 364system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25045250 # number of overall MSHR miss cycles 365system.cpu.icache.overall_mshr_miss_latency::total 25045250 # number of overall MSHR miss cycles 366system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses 367system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses 368system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses 369system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses 370system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses 371system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses 372system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68617.123288 # average ReadReq mshr miss latency 373system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68617.123288 # average ReadReq mshr miss latency 374system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency 375system.cpu.icache.demand_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency 376system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency 377system.cpu.icache.overall_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency 378system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 379system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s) 380system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution 381system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution 382system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 383system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 384system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 385system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 386system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) 387system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) 388system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 389system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) 390system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes) 391system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 392system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) 393system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 394system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) 395system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 396system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) 397system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 398system.cpu.l2cache.tags.replacements 0 # number of replacements 399system.cpu.l2cache.tags.tagsinuse 233.878182 # Cycle average of tags in use 400system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 401system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. 402system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. 403system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 404system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.878182 # Average occupied blocks per requestor 405system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy 406system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy 407system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id 408system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 409system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 410system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id 411system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses 412system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses 413system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 414system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 415system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 416system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 417system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 418system.cpu.l2cache.overall_hits::total 1 # number of overall hits 419system.cpu.l2cache.ReadReq_misses::cpu.inst 460 # number of ReadReq misses 420system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses 421system.cpu.l2cache.ReadExReq_misses::cpu.inst 73 # number of ReadExReq misses 422system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 423system.cpu.l2cache.demand_misses::cpu.inst 533 # number of demand (read+write) misses 424system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses 425system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses 426system.cpu.l2cache.overall_misses::total 533 # number of overall misses 427system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles 428system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles 429system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5056000 # number of ReadExReq miss cycles 430system.cpu.l2cache.ReadExReq_miss_latency::total 5056000 # number of ReadExReq miss cycles 431system.cpu.l2cache.demand_miss_latency::cpu.inst 36782750 # number of demand (read+write) miss cycles 432system.cpu.l2cache.demand_miss_latency::total 36782750 # number of demand (read+write) miss cycles 433system.cpu.l2cache.overall_miss_latency::cpu.inst 36782750 # number of overall miss cycles 434system.cpu.l2cache.overall_miss_latency::total 36782750 # number of overall miss cycles 435system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) 436system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) 437system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) 438system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 439system.cpu.l2cache.demand_accesses::cpu.inst 534 # number of demand (read+write) accesses 440system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses 441system.cpu.l2cache.overall_accesses::cpu.inst 534 # number of overall (read+write) accesses 442system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses 443system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997831 # miss rate for ReadReq accesses 444system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses 445system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 446system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 447system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 # miss rate for demand accesses 448system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses 449system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses 450system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses 451system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency 452system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency 453system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69260.273973 # average ReadExReq miss latency 454system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69260.273973 # average ReadExReq miss latency 455system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency 456system.cpu.l2cache.demand_avg_miss_latency::total 69010.787992 # average overall miss latency 457system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency 458system.cpu.l2cache.overall_avg_miss_latency::total 69010.787992 # average overall miss latency 459system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 460system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 461system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 462system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 463system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 464system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 465system.cpu.l2cache.fast_writes 0 # number of fast writes performed 466system.cpu.l2cache.cache_copies 0 # number of cache copies performed 467system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 460 # number of ReadReq MSHR misses 468system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses 469system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 73 # number of ReadExReq MSHR misses 470system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 471system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 # number of demand (read+write) MSHR misses 472system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses 473system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses 474system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses 475system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25965250 # number of ReadReq MSHR miss cycles 476system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25965250 # number of ReadReq MSHR miss cycles 477system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles 478system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles 479system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30103250 # number of demand (read+write) MSHR miss cycles 480system.cpu.l2cache.demand_mshr_miss_latency::total 30103250 # number of demand (read+write) MSHR miss cycles 481system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30103250 # number of overall MSHR miss cycles 482system.cpu.l2cache.overall_mshr_miss_latency::total 30103250 # number of overall MSHR miss cycles 483system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses 484system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses 485system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 486system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 487system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for demand accesses 488system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses 489system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses 490system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses 491system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652 # average ReadReq mshr miss latency 492system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652 # average ReadReq mshr miss latency 493system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency 494system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency 495system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency 496system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency 497system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency 498system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency 499system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 500system.cpu.dcache.tags.replacements 0 # number of replacements 501system.cpu.dcache.tags.tagsinuse 104.053835 # Cycle average of tags in use 502system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. 503system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 504system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. 505system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 506system.cpu.dcache.tags.occ_blocks::cpu.inst 104.053835 # Average occupied blocks per requestor 507system.cpu.dcache.tags.occ_percent::cpu.inst 0.025404 # Average percentage of cache occupancy 508system.cpu.dcache.tags.occ_percent::total 0.025404 # Average percentage of cache occupancy 509system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 510system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 511system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 512system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 513system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses 514system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses 515system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits 516system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits 517system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits 518system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 519system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits 520system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits 521system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits 522system.cpu.dcache.overall_hits::total 1968 # number of overall hits 523system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses 524system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses 525system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses 526system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 527system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses 528system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses 529system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses 530system.cpu.dcache.overall_misses::total 227 # number of overall misses 531system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7727250 # number of ReadReq miss cycles 532system.cpu.dcache.ReadReq_miss_latency::total 7727250 # number of ReadReq miss cycles 533system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8696750 # number of WriteReq miss cycles 534system.cpu.dcache.WriteReq_miss_latency::total 8696750 # number of WriteReq miss cycles 535system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles 536system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles 537system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles 538system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles 539system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses) 540system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses) 541system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) 542system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 543system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses 544system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses 545system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses 546system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses 547system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses 548system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses 549system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses 550system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 551system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses 552system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses 553system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses 554system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses 555system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941 # average ReadReq miss latency 556system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941 # average ReadReq miss latency 557system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69574 # average WriteReq miss latency 558system.cpu.dcache.WriteReq_avg_miss_latency::total 69574 # average WriteReq miss latency 559system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency 560system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency 561system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency 562system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency 563system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 564system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 565system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 566system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 567system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 568system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 569system.cpu.dcache.fast_writes 0 # number of fast writes performed 570system.cpu.dcache.cache_copies 0 # number of cache copies performed 571system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 572system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 573system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits 574system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 575system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits 576system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits 577system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits 578system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits 579system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses 580system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 581system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses 582system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 583system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses 584system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 585system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses 586system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses 587system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7154500 # number of ReadReq MSHR miss cycles 588system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154500 # number of ReadReq MSHR miss cycles 589system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5130500 # number of WriteReq MSHR miss cycles 590system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130500 # number of WriteReq MSHR miss cycles 591system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles 592system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles 593system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles 594system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles 595system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses 596system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses 597system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses 598system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 599system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses 600system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses 601system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses 602system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses 603system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667 # average ReadReq mshr miss latency 604system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667 # average ReadReq mshr miss latency 605system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918 # average WriteReq mshr miss latency 606system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918 # average WriteReq mshr miss latency 607system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency 608system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency 609system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency 610system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency 611system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 612 613---------- End Simulation Statistics ---------- | 612 613---------- End Simulation Statistics ---------- |