7,10c7,10
< host_inst_rate 217103 # Simulator instruction rate (inst/s)
< host_op_rate 217013 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1389706699 # Simulator tick rate (ticks/s)
< host_mem_usage 253264 # Number of bytes of host memory used
---
> host_inst_rate 202272 # Simulator instruction rate (inst/s)
> host_op_rate 202193 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1294825774 # Simulator tick rate (ticks/s)
> host_mem_usage 252636 # Number of bytes of host memory used
204,205c204,205
< system.physmem.totQLat 6580250 # Total ticks spent queuing
< system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6584250 # Total ticks spent queuing
> system.physmem.totMemAccLat 16559250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 12376.41 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 31126.41 # Average memory access latency per DRAM burst
250c250
< system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 4023060 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 14292180 # Energy for active power-down per rank (pJ)
265,268c265,268
< system.cpu.branchPred.lookups 2003 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups
---
> system.cpu.branchPred.lookups 2002 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1237 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 378 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 1602 # Number of BTB lookups
271,272c271,272
< system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 23.533084 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target.
274,277c274,277
< system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 322 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectLookups 333 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 14 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 319 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 114 # Number of mispredicted indirect branches.
295c295
< system.cpu.itb.fetch_hits 2686 # ITB hits
---
> system.cpu.itb.fetch_hits 2685 # ITB hits
298c298
< system.cpu.itb.fetch_accesses 2703 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2702 # ITB accesses
318c318
< system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1093 # Number of ops (including micro ops) which were discarded before commit
361,362c361,362
< system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 12637 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 69529 # Total number of cycles that the object has spent stopped
365c365
< system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 103.987673 # Cycle average of tags in use
370,372c370,372
< system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 103.987673 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.025388 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025388 # Average percentage of cache occupancy
398,403c398,403
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10428500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10428500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 18974000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 18974000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 18974000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 18974000 # number of overall miss cycles
422,427c422,427
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83428 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 83428 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 85855.203620 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 85855.203620 # average overall miss latency
450,455c450,455
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14538500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14538500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14538500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14538500 # number of overall MSHR miss cycles
466,471c466,471
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency
474,475c474,475
< system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 175.158440 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 2321 # Total number of references to valid blocks.
477c477
< system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 6.376374 # Average number of references to valid blocks.
479,481c479,481
< system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 175.158440 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.085527 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.085527 # Average percentage of cache occupancy
486,487c486,487
< system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 5736 # Number of data accesses
---
> system.cpu.icache.tags.tag_accesses 5734 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 5734 # Number of data accesses
489,494c489,494
< system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits
< system.cpu.icache.overall_hits::total 2322 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 2321 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 2321 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 2321 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 2321 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 2321 # number of overall hits
> system.cpu.icache.overall_hits::total 2321 # number of overall hits
501,524c501,524
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30321500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30321500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30321500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30321500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30321500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30321500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2685 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2685 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2685 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2685 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2685 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2685 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135568 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.135568 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.135568 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.135568 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.135568 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.135568 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83300.824176 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 83300.824176 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 83300.824176 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 83300.824176 # average overall miss latency
537,554c537,554
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29957500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 29957500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29957500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 29957500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29957500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 29957500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135568 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.135568 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.135568 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency
557c557
< system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 279.188916 # Cycle average of tags in use
562,563c562,563
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.158050 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 104.030866 # Average occupied blocks per requestor
592,595c592,595
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5979500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5979500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29400000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 29400000 # number of ReadCleanReq miss cycles
598,603c598,603
< system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 29400000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 14283500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 43683500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 29400000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 14283500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 43683500 # number of overall miss cycles
628,631c628,631
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81910.958904 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81910.958904 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80991.735537 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80991.735537 # average ReadCleanReq miss latency
634,639c634,639
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 82111.842105 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 82111.842105 # average overall miss latency
658,661c658,661
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5249500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5249500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25770000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25770000 # number of ReadCleanReq MSHR miss cycles
664,669c664,669
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25770000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12593500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 38363500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25770000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12593500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 38363500 # number of overall MSHR miss cycles
682,685c682,685
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537 # average ReadCleanReq mshr miss latency
688,693c688,693
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency
758c758
< system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 607000 # Layer occupancy (ticks)
< host_inst_rate 217103 # Simulator instruction rate (inst/s)
< host_op_rate 217013 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1389706699 # Simulator tick rate (ticks/s)
< host_mem_usage 253264 # Number of bytes of host memory used
---
> host_inst_rate 202272 # Simulator instruction rate (inst/s)
> host_op_rate 202193 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1294825774 # Simulator tick rate (ticks/s)
> host_mem_usage 252636 # Number of bytes of host memory used
204,205c204,205
< system.physmem.totQLat 6580250 # Total ticks spent queuing
< system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6584250 # Total ticks spent queuing
> system.physmem.totMemAccLat 16559250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 12376.41 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 31126.41 # Average memory access latency per DRAM burst
250c250
< system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 4023060 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 14292180 # Energy for active power-down per rank (pJ)
265,268c265,268
< system.cpu.branchPred.lookups 2003 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups
---
> system.cpu.branchPred.lookups 2002 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1237 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 378 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 1602 # Number of BTB lookups
271,272c271,272
< system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 23.533084 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target.
274,277c274,277
< system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 322 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectLookups 333 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 14 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 319 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 114 # Number of mispredicted indirect branches.
295c295
< system.cpu.itb.fetch_hits 2686 # ITB hits
---
> system.cpu.itb.fetch_hits 2685 # ITB hits
298c298
< system.cpu.itb.fetch_accesses 2703 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2702 # ITB accesses
318c318
< system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1093 # Number of ops (including micro ops) which were discarded before commit
361,362c361,362
< system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 12637 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 69529 # Total number of cycles that the object has spent stopped
365c365
< system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 103.987673 # Cycle average of tags in use
370,372c370,372
< system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 103.987673 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.025388 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025388 # Average percentage of cache occupancy
398,403c398,403
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10428500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10428500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 18974000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 18974000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 18974000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 18974000 # number of overall miss cycles
422,427c422,427
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83428 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 83428 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 85855.203620 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 85855.203620 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 85855.203620 # average overall miss latency
450,455c450,455
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14538500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14538500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14538500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 14538500 # number of overall MSHR miss cycles
466,471c466,471
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83410.958904 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83410.958904 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86026.627219 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 86026.627219 # average overall mshr miss latency
474,475c474,475
< system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 175.158440 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 2321 # Total number of references to valid blocks.
477c477
< system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 6.376374 # Average number of references to valid blocks.
479,481c479,481
< system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 175.158440 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.085527 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.085527 # Average percentage of cache occupancy
486,487c486,487
< system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 5736 # Number of data accesses
---
> system.cpu.icache.tags.tag_accesses 5734 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 5734 # Number of data accesses
489,494c489,494
< system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits
< system.cpu.icache.overall_hits::total 2322 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 2321 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 2321 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 2321 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 2321 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 2321 # number of overall hits
> system.cpu.icache.overall_hits::total 2321 # number of overall hits
501,524c501,524
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30321500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30321500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30321500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30321500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30321500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30321500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2685 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2685 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2685 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2685 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2685 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2685 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135568 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.135568 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.135568 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.135568 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.135568 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.135568 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83300.824176 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 83300.824176 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 83300.824176 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 83300.824176 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 83300.824176 # average overall miss latency
537,554c537,554
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29957500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 29957500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29957500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 29957500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29957500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 29957500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135568 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.135568 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135568 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.135568 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82300.824176 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82300.824176 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82300.824176 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 82300.824176 # average overall mshr miss latency
557c557
< system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 279.188916 # Cycle average of tags in use
562,563c562,563
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.158050 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 104.030866 # Average occupied blocks per requestor
592,595c592,595
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5979500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5979500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29400000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 29400000 # number of ReadCleanReq miss cycles
598,603c598,603
< system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 29400000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 14283500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 43683500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 29400000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 14283500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 43683500 # number of overall miss cycles
628,631c628,631
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81910.958904 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81910.958904 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80991.735537 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80991.735537 # average ReadCleanReq miss latency
634,639c634,639
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 82111.842105 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80991.735537 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84517.751479 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 82111.842105 # average overall miss latency
658,661c658,661
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5249500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5249500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25770000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25770000 # number of ReadCleanReq MSHR miss cycles
664,669c664,669
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25770000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12593500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 38363500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25770000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12593500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 38363500 # number of overall MSHR miss cycles
682,685c682,685
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71910.958904 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71910.958904 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70991.735537 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70991.735537 # average ReadCleanReq mshr miss latency
688,693c688,693
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70991.735537 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74517.751479 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72111.842105 # average overall mshr miss latency
758c758
< system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 607000 # Layer occupancy (ticks)