4,5c4,5
< sim_ticks 37822000 # Number of ticks simulated
< final_tick 37822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 38282000 # Number of ticks simulated
> final_tick 38282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 100508 # Simulator instruction rate (inst/s)
< host_op_rate 100471 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 592356577 # Simulator tick rate (ticks/s)
< host_mem_usage 249008 # Number of bytes of host memory used
< host_seconds 0.06 # Real time elapsed on the host
---
> host_inst_rate 159466 # Simulator instruction rate (inst/s)
> host_op_rate 159415 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 951356890 # Simulator tick rate (ticks/s)
> host_mem_usage 253388 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 614245677 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 285971128 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 900216805 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 614245677 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 614245677 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 614245677 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 285971128 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 900216805 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 606864845 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 282534873 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 889399718 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 606864845 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 606864845 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 606864845 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 282534873 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 889399718 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 37718000 # Total gap between requests
---
> system.physmem.totGap 38177000 # Total gap between requests
190,205c190,205
< system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 385.560976 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 252.880176 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 333.081835 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 17 20.73% 20.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 21 25.61% 46.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9 10.98% 57.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 11 13.41% 70.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4 4.88% 75.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3 3.66% 79.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 3.66% 82.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5 6.10% 89.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9 10.98% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation
< system.physmem.totQLat 3215000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13190000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 377.831325 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 247.256857 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.629090 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 20 24.10% 45.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 11 13.25% 59.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 11 13.25% 72.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 3.61% 75.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 4 4.82% 80.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3 3.61% 84.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 4 4.82% 89.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9 10.84% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation
> system.physmem.totQLat 3252000 # Total ticks spent queuing
> system.physmem.totMemAccLat 13227000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 6043.23 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6112.78 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 24793.23 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 900.22 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24862.78 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 889.40 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 900.22 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 889.40 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 7.03 # Data bus utilization in percentage
< system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 6.95 # Data bus utilization in percentage
> system.physmem.busUtilRead 6.95 # Data bus utilization in percentage for reads
220c220
< system.physmem.readRowHits 438 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 437 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads
224,225c224,225
< system.physmem.avgGap 70898.50 # Average gap between requests
< system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 71761.28 # Average gap between requests
> system.physmem.pageHitRate 82.14 # Row buffer hit rate, read and write combined
228c228
< system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 2020200 # Energy for read commands per rank (pJ)
231,235c231,235
< system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
< system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 366250 # Time in different power states
---
> system.physmem_0.actBackEnergy 21270690 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 184500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 25871865 # Total energy per rank (pJ)
> system.physmem_0.averagePower 823.813565 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 196750 # Time in different power states
238c238
< system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 30182000 # Time in different power states
240,242c240,242
< system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1505400 # Energy for read commands per rank (pJ)
245,249c245,249
< system.physmem_1.actBackEnergy 20148930 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1168500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 25398495 # Total energy per rank (pJ)
< system.physmem_1.averagePower 808.740487 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1794750 # Time in different power states
---
> system.physmem_1.actBackEnergy 20078820 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1230000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 25385970 # Total energy per rank (pJ)
> system.physmem_1.averagePower 808.341665 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2146500 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 28584000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 28481000 # Time in different power states
254c254
< system.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
302,303c302,303
< system.cpu.pwrStateResidencyTicks::ON 37822000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 75644 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 38282000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 76564 # number of cpu cycles simulated
310,311c310,311
< system.cpu.cpi 11.795416 # CPI: cycles per instruction
< system.cpu.ipc 0.084779 # IPC: instructions per cycle
---
> system.cpu.cpi 11.938874 # CPI: cycles per instruction
> system.cpu.ipc 0.083760 # IPC: instructions per cycle
348,349c348,349
< system.cpu.idleCycles 62993 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.idleCycles 63913 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
351c351
< system.cpu.dcache.tags.tagsinuse 103.701168 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 103.736314 # Cycle average of tags in use
356,358c356,358
< system.cpu.dcache.tags.occ_blocks::cpu.data 103.701168 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.025318 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025318 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 103.736314 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.025326 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025326 # Average percentage of cache occupancy
365c365
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
382,389c382,389
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7590000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7590000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9158000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9158000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 16748000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16748000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16748000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16748000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7713000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7713000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9281000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9281000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 16994000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16994000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 16994000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16994000 # number of overall miss cycles
406,413c406,413
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79062.500000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 79062.500000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73264 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73264 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 75782.805430 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 75782.805430 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80343.750000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 80343.750000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74248 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74248 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 76895.927602 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 76895.927602 # average overall miss latency
434,441c434,441
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7494000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7494000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5379500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5379500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12873500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12873500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12873500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12873500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7617000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7617000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5452500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5452500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13069500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13069500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13069500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13069500 # number of overall MSHR miss cycles
450,458c450,458
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78062.500000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78062.500000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73691.780822 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73691.780822 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79343.750000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74691.780822 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74691.780822 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
460c460
< system.cpu.icache.tags.tagsinuse 174.485780 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 174.445567 # Cycle average of tags in use
465,467c465,467
< system.cpu.icache.tags.occ_blocks::cpu.inst 174.485780 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.085198 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.085198 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 174.445567 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.085178 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.085178 # Average percentage of cache occupancy
469,470c469,470
< system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id
474c474
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
487,492c487,492
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28087500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28087500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28087500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28087500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28087500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28087500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 28460500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 28460500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 28460500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 28460500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 28460500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 28460500 # number of overall miss cycles
505,510c505,510
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77163.461538 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77163.461538 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77163.461538 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77163.461538 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78188.186813 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 78188.186813 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 78188.186813 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 78188.186813 # average overall miss latency
523,528c523,528
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27723500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 27723500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27723500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 27723500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27723500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 27723500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28096500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 28096500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28096500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 28096500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28096500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 28096500 # number of overall MSHR miss cycles
535,541c535,541
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76163.461538 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76163.461538 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77188.186813 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77188.186813 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
543c543
< system.cpu.l2cache.tags.tagsinuse 232.271171 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 278.242026 # Cycle average of tags in use
545,546c545,546
< system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks.
548,556c548,556
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.500375 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 57.770796 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005325 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007088 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.459359 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 103.782667 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005324 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.008491 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id
559c559
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
578,589c578,589
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5270000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5270000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27166000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 27166000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7348500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7348500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 27166000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12618500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 39784500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 27166000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12618500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 39784500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5343000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5343000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27539000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 27539000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27539000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12814500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 40353500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27539000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12814500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 40353500 # number of overall miss cycles
614,625c614,625
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72191.780822 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72191.780822 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74837.465565 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74837.465565 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76546.875000 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76546.875000 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74782.894737 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74782.894737 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73191.780822 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73191.780822 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75865.013774 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75865.013774 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77828.125000 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77828.125000 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75852.443609 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75852.443609 # average overall miss latency
644,655c644,655
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4540000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4540000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23536000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23536000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6388500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6388500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23536000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10928500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 34464500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23536000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10928500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 34464500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4613000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23909000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23909000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23909000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11124500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 35033500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23909000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11124500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 35033500 # number of overall MSHR miss cycles
668,679c668,679
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62191.780822 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62191.780822 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64837.465565 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64837.465565 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66546.875000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66546.875000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63191.780822 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63191.780822 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65865.013774 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65865.013774 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67828.125000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67828.125000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency
686c686
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
717c717,723
< system.membus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
741c747
< system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
---
> system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
< sim_ticks 37822000 # Number of ticks simulated
< final_tick 37822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 38282000 # Number of ticks simulated
> final_tick 38282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 100508 # Simulator instruction rate (inst/s)
< host_op_rate 100471 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 592356577 # Simulator tick rate (ticks/s)
< host_mem_usage 249008 # Number of bytes of host memory used
< host_seconds 0.06 # Real time elapsed on the host
---
> host_inst_rate 159466 # Simulator instruction rate (inst/s)
> host_op_rate 159415 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 951356890 # Simulator tick rate (ticks/s)
> host_mem_usage 253388 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 614245677 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 285971128 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 900216805 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 614245677 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 614245677 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 614245677 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 285971128 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 900216805 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 606864845 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 282534873 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 889399718 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 606864845 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 606864845 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 606864845 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 282534873 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 889399718 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 37718000 # Total gap between requests
---
> system.physmem.totGap 38177000 # Total gap between requests
190,205c190,205
< system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 385.560976 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 252.880176 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 333.081835 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 17 20.73% 20.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 21 25.61% 46.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 9 10.98% 57.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 11 13.41% 70.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4 4.88% 75.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3 3.66% 79.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 3.66% 82.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5 6.10% 89.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9 10.98% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation
< system.physmem.totQLat 3215000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13190000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 377.831325 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 247.256857 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.629090 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 20 24.10% 45.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 11 13.25% 59.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 11 13.25% 72.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 3.61% 75.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 4 4.82% 80.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3 3.61% 84.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 4 4.82% 89.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9 10.84% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation
> system.physmem.totQLat 3252000 # Total ticks spent queuing
> system.physmem.totMemAccLat 13227000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 6043.23 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6112.78 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 24793.23 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 900.22 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24862.78 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 889.40 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 900.22 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 889.40 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 7.03 # Data bus utilization in percentage
< system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 6.95 # Data bus utilization in percentage
> system.physmem.busUtilRead 6.95 # Data bus utilization in percentage for reads
220c220
< system.physmem.readRowHits 438 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 437 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads
224,225c224,225
< system.physmem.avgGap 70898.50 # Average gap between requests
< system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 71761.28 # Average gap between requests
> system.physmem.pageHitRate 82.14 # Row buffer hit rate, read and write combined
228c228
< system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 2020200 # Energy for read commands per rank (pJ)
231,235c231,235
< system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
< system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 366250 # Time in different power states
---
> system.physmem_0.actBackEnergy 21270690 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 184500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 25871865 # Total energy per rank (pJ)
> system.physmem_0.averagePower 823.813565 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 196750 # Time in different power states
238c238
< system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 30182000 # Time in different power states
240,242c240,242
< system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1505400 # Energy for read commands per rank (pJ)
245,249c245,249
< system.physmem_1.actBackEnergy 20148930 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1168500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 25398495 # Total energy per rank (pJ)
< system.physmem_1.averagePower 808.740487 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1794750 # Time in different power states
---
> system.physmem_1.actBackEnergy 20078820 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1230000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 25385970 # Total energy per rank (pJ)
> system.physmem_1.averagePower 808.341665 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2146500 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 28584000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 28481000 # Time in different power states
254c254
< system.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
302,303c302,303
< system.cpu.pwrStateResidencyTicks::ON 37822000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 75644 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 38282000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 76564 # number of cpu cycles simulated
310,311c310,311
< system.cpu.cpi 11.795416 # CPI: cycles per instruction
< system.cpu.ipc 0.084779 # IPC: instructions per cycle
---
> system.cpu.cpi 11.938874 # CPI: cycles per instruction
> system.cpu.ipc 0.083760 # IPC: instructions per cycle
348,349c348,349
< system.cpu.idleCycles 62993 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.idleCycles 63913 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
351c351
< system.cpu.dcache.tags.tagsinuse 103.701168 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 103.736314 # Cycle average of tags in use
356,358c356,358
< system.cpu.dcache.tags.occ_blocks::cpu.data 103.701168 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.025318 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025318 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 103.736314 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.025326 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025326 # Average percentage of cache occupancy
365c365
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
382,389c382,389
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7590000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7590000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9158000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9158000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 16748000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16748000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 16748000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16748000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7713000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7713000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9281000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9281000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 16994000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16994000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 16994000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16994000 # number of overall miss cycles
406,413c406,413
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79062.500000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 79062.500000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73264 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73264 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 75782.805430 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 75782.805430 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80343.750000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 80343.750000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74248 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74248 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 76895.927602 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 76895.927602 # average overall miss latency
434,441c434,441
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7494000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7494000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5379500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5379500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12873500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12873500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12873500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12873500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7617000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7617000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5452500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5452500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13069500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13069500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13069500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13069500 # number of overall MSHR miss cycles
450,458c450,458
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78062.500000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78062.500000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73691.780822 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73691.780822 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79343.750000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74691.780822 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74691.780822 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
460c460
< system.cpu.icache.tags.tagsinuse 174.485780 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 174.445567 # Cycle average of tags in use
465,467c465,467
< system.cpu.icache.tags.occ_blocks::cpu.inst 174.485780 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.085198 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.085198 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 174.445567 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.085178 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.085178 # Average percentage of cache occupancy
469,470c469,470
< system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id
474c474
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
487,492c487,492
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28087500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28087500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28087500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28087500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28087500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28087500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 28460500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 28460500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 28460500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 28460500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 28460500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 28460500 # number of overall miss cycles
505,510c505,510
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77163.461538 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77163.461538 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77163.461538 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77163.461538 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78188.186813 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 78188.186813 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 78188.186813 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 78188.186813 # average overall miss latency
523,528c523,528
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27723500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 27723500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27723500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 27723500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27723500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 27723500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28096500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 28096500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28096500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 28096500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28096500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 28096500 # number of overall MSHR miss cycles
535,541c535,541
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76163.461538 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76163.461538 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77188.186813 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77188.186813 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
543c543
< system.cpu.l2cache.tags.tagsinuse 232.271171 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 278.242026 # Cycle average of tags in use
545,546c545,546
< system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks.
548,556c548,556
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.500375 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 57.770796 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005325 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007088 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.459359 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 103.782667 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005324 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.008491 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id
559c559
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
578,589c578,589
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5270000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5270000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27166000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 27166000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7348500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7348500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 27166000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12618500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 39784500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 27166000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12618500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 39784500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5343000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5343000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27539000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 27539000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27539000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12814500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 40353500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27539000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12814500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 40353500 # number of overall miss cycles
614,625c614,625
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72191.780822 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72191.780822 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74837.465565 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74837.465565 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76546.875000 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76546.875000 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74782.894737 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74782.894737 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73191.780822 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73191.780822 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75865.013774 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75865.013774 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77828.125000 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77828.125000 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75852.443609 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75852.443609 # average overall miss latency
644,655c644,655
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4540000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4540000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23536000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23536000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6388500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6388500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23536000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10928500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 34464500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23536000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10928500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 34464500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4613000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23909000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23909000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23909000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11124500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 35033500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23909000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11124500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 35033500 # number of overall MSHR miss cycles
668,679c668,679
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62191.780822 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62191.780822 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64837.465565 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64837.465565 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66546.875000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66546.875000 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63191.780822 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63191.780822 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65865.013774 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65865.013774 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67828.125000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67828.125000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency
686c686
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
717c717,723
< system.membus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
741c747
< system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
---
> system.membus.respLayer1.utilization 7.4 # Layer utilization (%)