4,5c4,5
< sim_ticks 37928000 # Number of ticks simulated
< final_tick 37928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 37930000 # Number of ticks simulated
> final_tick 37930000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 174102 # Simulator instruction rate (inst/s)
< host_op_rate 174036 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1031016392 # Simulator tick rate (ticks/s)
< host_mem_usage 293404 # Number of bytes of host memory used
---
> host_inst_rate 161486 # Simulator instruction rate (inst/s)
> host_op_rate 161429 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 956403338 # Simulator tick rate (ticks/s)
> host_mem_usage 294064 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 614216410 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 285171905 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 899388315 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 614216410 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 614216410 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 614216410 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 285171905 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 899388315 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 614184023 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 285156868 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 899340891 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 614184023 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 614184023 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 614184023 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 285156868 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 899340891 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 37822500 # Total gap between requests
---
> system.physmem.totGap 37824500 # Total gap between requests
209c209
< system.physmem.avgRdBW 899.39 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgRdBW 899.34 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 899.39 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 899.34 # Average system read bandwidth in MiByte/s
223c223
< system.physmem.avgGap 70961.54 # Average gap between requests
---
> system.physmem.avgGap 70965.29 # Average gap between requests
234c234
< system.physmem_0.memoryStateTime::IDLE 371750 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 372750 # Time in different power states
253,254c253,254
< system.cpu.branchPred.lookups 1968 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 1964 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1204 # Number of conditional branches predicted
256,257c256,257
< system.cpu.branchPred.BTBLookups 1559 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 385 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 1555 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 382 # Number of BTB hits
259c259
< system.cpu.branchPred.BTBHitPct 24.695318 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 24.565916 # BTB Hit Percentage
267c267
< system.cpu.dtb.read_hits 1370 # DTB read hits
---
> system.cpu.dtb.read_hits 1371 # DTB read hits
270c270
< system.cpu.dtb.read_accesses 1381 # DTB read accesses
---
> system.cpu.dtb.read_accesses 1382 # DTB read accesses
275c275
< system.cpu.dtb.data_hits 2254 # DTB hits
---
> system.cpu.dtb.data_hits 2255 # DTB hits
278,279c278,279
< system.cpu.dtb.data_accesses 2268 # DTB accesses
< system.cpu.itb.fetch_hits 2639 # ITB hits
---
> system.cpu.dtb.data_accesses 2269 # DTB accesses
> system.cpu.itb.fetch_hits 2638 # ITB hits
282c282
< system.cpu.itb.fetch_accesses 2656 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2655 # ITB accesses
296c296
< system.cpu.numCycles 75856 # number of cpu cycles simulated
---
> system.cpu.numCycles 75860 # number of cpu cycles simulated
301c301
< system.cpu.discardedOps 1110 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit
303,306c303,306
< system.cpu.cpi 11.852500 # CPI: cycles per instruction
< system.cpu.ipc 0.084370 # IPC: instructions per cycle
< system.cpu.tickCycles 12576 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 63280 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 11.853125 # CPI: cycles per instruction
> system.cpu.ipc 0.084366 # IPC: instructions per cycle
> system.cpu.tickCycles 12560 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 63300 # Total number of cycles that the object has spent stopped
308,309c308,309
< system.cpu.dcache.tags.tagsinuse 103.896503 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 103.899066 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1976 # Total number of references to valid blocks.
311c311
< system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 11.692308 # Average number of references to valid blocks.
313,315c313,315
< system.cpu.dcache.tags.occ_blocks::cpu.data 103.896503 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.025365 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025365 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 103.899066 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.025366 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025366 # Average percentage of cache occupancy
320,323c320,323
< system.cpu.dcache.tags.tag_accesses 4571 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4571 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits
326,329c326,329
< system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits
< system.cpu.dcache.overall_hits::total 1975 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1976 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1976 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1976 # number of overall hits
> system.cpu.dcache.overall_hits::total 1976 # number of overall hits
338,347c338,347
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8143750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8143750 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9234250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9234250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 17378000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17378000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17378000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17378000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1336 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1336 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8144750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8144750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9233750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9233750 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 17378500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17378500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 17378500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17378500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses)
350,355c350,355
< system.cpu.dcache.demand_accesses::cpu.data 2201 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2201 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2201 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2201 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076347 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.076347 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses
358,369c358,369
< system.cpu.dcache.demand_miss_rate::cpu.data 0.102681 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.102681 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.102681 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.102681 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79840.686275 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 79840.686275 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74469.758065 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74469.758065 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 76893.805310 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 76893.805310 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.102634 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.102634 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.102634 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.102634 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79850.490196 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 79850.490196 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74465.725806 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74465.725806 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 76896.017699 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 76896.017699 # average overall miss latency
394,395c394,395
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7563250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7563250 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7564250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7564250 # number of ReadReq MSHR miss cycles
398,403c398,403
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12927500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12927500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12927500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12927500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071856 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071856 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12928500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12928500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12928500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12928500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses
406,411c406,411
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.076783 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.076783 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78783.854167 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78783.854167 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78794.270833 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78794.270833 # average ReadReq mshr miss latency
414,417c414,417
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency
420,421c420,421
< system.cpu.icache.tags.tagsinuse 175.733533 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 175.739822 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 2273 # Total number of references to valid blocks.
423c423
< system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 6.227397 # Average number of references to valid blocks.
425,427c425,427
< system.cpu.icache.tags.occ_blocks::cpu.inst 175.733533 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.085807 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.085807 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 175.739822 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.085810 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.085810 # Average percentage of cache occupancy
432,439c432,439
< system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 5643 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits
< system.cpu.icache.overall_hits::total 2274 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 5641 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 5641 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 2273 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 2273 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 2273 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 2273 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 2273 # number of overall hits
> system.cpu.icache.overall_hits::total 2273 # number of overall hits
446,469c446,469
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333250 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28333250 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28333250 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28333250 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28333250 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28333250 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77625.342466 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77625.342466 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77625.342466 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77625.342466 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333750 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 28333750 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 28333750 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 28333750 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 28333750 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 28333750 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2638 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2638 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2638 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2638 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2638 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2638 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138362 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.138362 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.138362 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.138362 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.138362 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.138362 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77626.712329 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77626.712329 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77626.712329 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77626.712329 # average overall miss latency
484,501c484,501
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 27622250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 27622250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 27622250 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75677.397260 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75677.397260 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 27622750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 27622750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 27622750 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138362 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.138362 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.138362 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75678.767123 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75678.767123 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency
504c504
< system.cpu.l2cache.tags.tagsinuse 233.387081 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 233.394654 # Cycle average of tags in use
509,510c509,510
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.765541 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 57.621541 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.771828 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 57.622826 # Average occupied blocks per requestor
512,513c512,513
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001758 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007122 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007123 # Average percentage of cache occupancy
537,539c537,539
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 34712000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7466750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 34713500 # number of ReadReq miss cycles
542,547c542,547
< system.cpu.l2cache.demand_miss_latency::cpu.inst 27246250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12756000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 40002250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 27246250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12756000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 40002250 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27246750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12757000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 40003750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27246750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12757000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 40003750 # number of overall miss cycles
570,572c570,572
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74852.335165 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77768.229167 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 75460.869565 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74853.708791 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77778.645833 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75464.130435 # average ReadReq miss latency
575,580c575,580
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75051.125704 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75051.125704 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75053.939962 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75053.939962 # average overall miss latency
600,602c600,602
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6259250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28945500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6260250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28947000 # number of ReadReq MSHR miss cycles
605,610c605,610
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10637500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 33323750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10637500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 33323750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10638500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 33325250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10638500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 33325250 # number of overall MSHR miss cycles
622,624c622,624
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62324.862637 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65200.520833 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62925 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62326.236264 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65210.937500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62928.260870 # average ReadReq mshr miss latency
627,632c627,632
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency
681c681
< system.membus.reqLayer0.occupancy 604000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks)
< sim_ticks 37928000 # Number of ticks simulated
< final_tick 37928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 37930000 # Number of ticks simulated
> final_tick 37930000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 174102 # Simulator instruction rate (inst/s)
< host_op_rate 174036 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1031016392 # Simulator tick rate (ticks/s)
< host_mem_usage 293404 # Number of bytes of host memory used
---
> host_inst_rate 161486 # Simulator instruction rate (inst/s)
> host_op_rate 161429 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 956403338 # Simulator tick rate (ticks/s)
> host_mem_usage 294064 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 614216410 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 285171905 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 899388315 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 614216410 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 614216410 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 614216410 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 285171905 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 899388315 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 614184023 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 285156868 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 899340891 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 614184023 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 614184023 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 614184023 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 285156868 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 899340891 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 37822500 # Total gap between requests
---
> system.physmem.totGap 37824500 # Total gap between requests
209c209
< system.physmem.avgRdBW 899.39 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgRdBW 899.34 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 899.39 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 899.34 # Average system read bandwidth in MiByte/s
223c223
< system.physmem.avgGap 70961.54 # Average gap between requests
---
> system.physmem.avgGap 70965.29 # Average gap between requests
234c234
< system.physmem_0.memoryStateTime::IDLE 371750 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 372750 # Time in different power states
253,254c253,254
< system.cpu.branchPred.lookups 1968 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 1964 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1204 # Number of conditional branches predicted
256,257c256,257
< system.cpu.branchPred.BTBLookups 1559 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 385 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 1555 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 382 # Number of BTB hits
259c259
< system.cpu.branchPred.BTBHitPct 24.695318 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 24.565916 # BTB Hit Percentage
267c267
< system.cpu.dtb.read_hits 1370 # DTB read hits
---
> system.cpu.dtb.read_hits 1371 # DTB read hits
270c270
< system.cpu.dtb.read_accesses 1381 # DTB read accesses
---
> system.cpu.dtb.read_accesses 1382 # DTB read accesses
275c275
< system.cpu.dtb.data_hits 2254 # DTB hits
---
> system.cpu.dtb.data_hits 2255 # DTB hits
278,279c278,279
< system.cpu.dtb.data_accesses 2268 # DTB accesses
< system.cpu.itb.fetch_hits 2639 # ITB hits
---
> system.cpu.dtb.data_accesses 2269 # DTB accesses
> system.cpu.itb.fetch_hits 2638 # ITB hits
282c282
< system.cpu.itb.fetch_accesses 2656 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2655 # ITB accesses
296c296
< system.cpu.numCycles 75856 # number of cpu cycles simulated
---
> system.cpu.numCycles 75860 # number of cpu cycles simulated
301c301
< system.cpu.discardedOps 1110 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit
303,306c303,306
< system.cpu.cpi 11.852500 # CPI: cycles per instruction
< system.cpu.ipc 0.084370 # IPC: instructions per cycle
< system.cpu.tickCycles 12576 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 63280 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 11.853125 # CPI: cycles per instruction
> system.cpu.ipc 0.084366 # IPC: instructions per cycle
> system.cpu.tickCycles 12560 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 63300 # Total number of cycles that the object has spent stopped
308,309c308,309
< system.cpu.dcache.tags.tagsinuse 103.896503 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 103.899066 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1976 # Total number of references to valid blocks.
311c311
< system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 11.692308 # Average number of references to valid blocks.
313,315c313,315
< system.cpu.dcache.tags.occ_blocks::cpu.data 103.896503 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.025365 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025365 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 103.899066 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.025366 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025366 # Average percentage of cache occupancy
320,323c320,323
< system.cpu.dcache.tags.tag_accesses 4571 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4571 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits
326,329c326,329
< system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits
< system.cpu.dcache.overall_hits::total 1975 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1976 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1976 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1976 # number of overall hits
> system.cpu.dcache.overall_hits::total 1976 # number of overall hits
338,347c338,347
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8143750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8143750 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9234250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9234250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 17378000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17378000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17378000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17378000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1336 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1336 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8144750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8144750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9233750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9233750 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 17378500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 17378500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 17378500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 17378500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses)
350,355c350,355
< system.cpu.dcache.demand_accesses::cpu.data 2201 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2201 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2201 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2201 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076347 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.076347 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses
358,369c358,369
< system.cpu.dcache.demand_miss_rate::cpu.data 0.102681 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.102681 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.102681 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.102681 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79840.686275 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 79840.686275 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74469.758065 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74469.758065 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 76893.805310 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 76893.805310 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.102634 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.102634 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.102634 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.102634 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79850.490196 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 79850.490196 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74465.725806 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74465.725806 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 76896.017699 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 76896.017699 # average overall miss latency
394,395c394,395
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7563250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7563250 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7564250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7564250 # number of ReadReq MSHR miss cycles
398,403c398,403
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12927500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12927500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12927500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12927500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071856 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071856 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12928500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12928500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12928500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12928500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses
406,411c406,411
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.076783 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.076783 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78783.854167 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78783.854167 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78794.270833 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78794.270833 # average ReadReq mshr miss latency
414,417c414,417
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency
420,421c420,421
< system.cpu.icache.tags.tagsinuse 175.733533 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 175.739822 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 2273 # Total number of references to valid blocks.
423c423
< system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 6.227397 # Average number of references to valid blocks.
425,427c425,427
< system.cpu.icache.tags.occ_blocks::cpu.inst 175.733533 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.085807 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.085807 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 175.739822 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.085810 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.085810 # Average percentage of cache occupancy
432,439c432,439
< system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 5643 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits
< system.cpu.icache.overall_hits::total 2274 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 5641 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 5641 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 2273 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 2273 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 2273 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 2273 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 2273 # number of overall hits
> system.cpu.icache.overall_hits::total 2273 # number of overall hits
446,469c446,469
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333250 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28333250 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28333250 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28333250 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28333250 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28333250 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77625.342466 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77625.342466 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77625.342466 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77625.342466 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333750 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 28333750 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 28333750 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 28333750 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 28333750 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 28333750 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2638 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2638 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2638 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2638 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2638 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2638 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138362 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.138362 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.138362 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.138362 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.138362 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.138362 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77626.712329 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77626.712329 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77626.712329 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77626.712329 # average overall miss latency
484,501c484,501
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 27622250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 27622250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 27622250 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75677.397260 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75677.397260 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 27622750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 27622750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 27622750 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138362 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.138362 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.138362 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75678.767123 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75678.767123 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency
504c504
< system.cpu.l2cache.tags.tagsinuse 233.387081 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 233.394654 # Cycle average of tags in use
509,510c509,510
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.765541 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 57.621541 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.771828 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 57.622826 # Average occupied blocks per requestor
512,513c512,513
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001758 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007122 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007123 # Average percentage of cache occupancy
537,539c537,539
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 34712000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7466750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 34713500 # number of ReadReq miss cycles
542,547c542,547
< system.cpu.l2cache.demand_miss_latency::cpu.inst 27246250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12756000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 40002250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 27246250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12756000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 40002250 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27246750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12757000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 40003750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27246750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12757000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 40003750 # number of overall miss cycles
570,572c570,572
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74852.335165 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77768.229167 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 75460.869565 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74853.708791 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77778.645833 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75464.130435 # average ReadReq miss latency
575,580c575,580
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75051.125704 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75051.125704 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75053.939962 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75053.939962 # average overall miss latency
600,602c600,602
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6259250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28945500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6260250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28947000 # number of ReadReq MSHR miss cycles
605,610c605,610
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10637500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 33323750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10637500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 33323750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10638500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 33325250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10638500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 33325250 # number of overall MSHR miss cycles
622,624c622,624
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62324.862637 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65200.520833 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62925 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62326.236264 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65210.937500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62928.260870 # average ReadReq mshr miss latency
627,632c627,632
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency
681c681
< system.membus.reqLayer0.occupancy 604000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks)