4,5c4,5
< sim_ticks 35024500 # Number of ticks simulated
< final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 35022500 # Number of ticks simulated
> final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 72507 # Simulator instruction rate (inst/s)
< host_op_rate 72491 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 396631772 # Simulator tick rate (ticks/s)
< host_mem_usage 236200 # Number of bytes of host memory used
---
> host_inst_rate 71946 # Simulator instruction rate (inst/s)
> host_op_rate 71929 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 393524726 # Simulator tick rate (ticks/s)
> host_mem_usage 237176 # Number of bytes of host memory used
22,27c22,27
< system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s)
74c74
< system.physmem.totGap 34926000 # Total gap between requests
---
> system.physmem.totGap 34924000 # Total gap between requests
199,200c199,200
< system.physmem.totQLat 3928000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3887500 # Total ticks spent queuing
> system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst
204,205c204,205
< system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s
207c207
< system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s
219c219
< system.physmem.avgGap 65527.20 # Average gap between requests
---
> system.physmem.avgGap 65523.45 # Average gap between requests
224c224
< system.physmem.memoryStateTime::ACT 30394500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 30393500 # Time in different power states
237c237
< system.physmem.actBackEnergy::1 20168595 # Energy for active background per rank (pJ)
---
> system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ)
239c239
< system.physmem.preBackEnergy::1 1170000 # Energy for precharge background per rank (pJ)
---
> system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ)
241c241
< system.physmem.totalEnergy::1 25645770 # Total energy per rank (pJ)
---
> system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ)
243,269c243,245
< system.physmem.averagePower::1 815.802457 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 460 # Transaction distribution
< system.membus.trans_dist::ReadResp 460 # Transaction distribution
< system.membus.trans_dist::ReadExReq 73 # Transaction distribution
< system.membus.trans_dist::ReadExResp 73 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 533 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 533 # Request fanout histogram
< system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 14.2 # Layer utilization (%)
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.branchPred.lookups 1959 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted
---
> system.physmem.averagePower::1 815.785757 # Core power per rank (mW)
> system.cpu.branchPred.lookups 1972 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted
271,272c247,248
< system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 381 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 385 # Number of BTB hits
274c250
< system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage
276a253
> system.cpu_clk_domain.clock 500 # Clock period in ticks
281c258
< system.cpu.dtb.read_hits 1368 # DTB read hits
---
> system.cpu.dtb.read_hits 1370 # DTB read hits
284c261
< system.cpu.dtb.read_accesses 1379 # DTB read accesses
---
> system.cpu.dtb.read_accesses 1381 # DTB read accesses
289c266
< system.cpu.dtb.data_hits 2252 # DTB hits
---
> system.cpu.dtb.data_hits 2254 # DTB hits
292,293c269,270
< system.cpu.dtb.data_accesses 2266 # DTB accesses
< system.cpu.itb.fetch_hits 2630 # ITB hits
---
> system.cpu.dtb.data_accesses 2268 # DTB accesses
> system.cpu.itb.fetch_hits 2642 # ITB hits
296c273
< system.cpu.itb.fetch_accesses 2647 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2659 # ITB accesses
310c287
< system.cpu.numCycles 70049 # number of cpu cycles simulated
---
> system.cpu.numCycles 70045 # number of cpu cycles simulated
315c292
< system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit
317,320c294,409
< system.cpu.cpi 10.945156 # CPI: cycles per instruction
< system.cpu.ipc 0.091365 # IPC: instructions per cycle
< system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 10.944531 # CPI: cycles per instruction
> system.cpu.ipc 0.091370 # IPC: instructions per cycle
> system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 1233 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.inst 1973 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 1973 # number of overall hits
> system.cpu.dcache.overall_hits::total 1973 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
> system.cpu.dcache.overall_misses::total 227 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.inst 2200 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 2200 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076404 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.103182 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
322,323c411,412
< system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks.
325c414
< system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks.
327,329c416,418
< system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 176.126032 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.085999 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.085999 # Average percentage of cache occupancy
334,341c423,430
< system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 5625 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits
< system.cpu.icache.overall_hits::total 2265 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 5649 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits
> system.cpu.icache.overall_hits::total 2277 # number of overall hits
348,371c437,460
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25915750 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25915750 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25915750 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25915750 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25915750 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25915750 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 71002.054795 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 71002.054795 # average overall miss latency
386,403c475,492
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25028250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25028250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25028250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25028250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25028250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25028250 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency
405,432d493
< system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 0 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
434c495
< system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 233.857006 # Cycle average of tags in use
439,441c500,502
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.857006 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy
462,469c523,530
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31686750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 31686750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5053000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5053000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 36739750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 36739750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 36739750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 36739750 # number of overall miss cycles
486,493c547,554
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570 # average overall miss latency
510,511c571,572
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25921750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25921750 # number of ReadReq MSHR miss cycles
514,517c575,578
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30069250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 30069250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30069250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30069250 # number of overall MSHR miss cycles
526,527c587,588
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435 # average ReadReq mshr miss latency
530,533c591,594
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency
535,646c596,646
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits
< system.cpu.dcache.overall_hits::total 1968 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
< system.cpu.dcache.overall_misses::total 227 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
> system.membus.trans_dist::ReadReq 460 # Transaction distribution
> system.membus.trans_dist::ReadResp 460 # Transaction distribution
> system.membus.trans_dist::ReadExReq 73 # Transaction distribution
> system.membus.trans_dist::ReadExResp 73 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 533 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 533 # Request fanout histogram
> system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
> system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 14.2 # Layer utilization (%)
< sim_ticks 35024500 # Number of ticks simulated
< final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 35022500 # Number of ticks simulated
> final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 72507 # Simulator instruction rate (inst/s)
< host_op_rate 72491 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 396631772 # Simulator tick rate (ticks/s)
< host_mem_usage 236200 # Number of bytes of host memory used
---
> host_inst_rate 71946 # Simulator instruction rate (inst/s)
> host_op_rate 71929 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 393524726 # Simulator tick rate (ticks/s)
> host_mem_usage 237176 # Number of bytes of host memory used
22,27c22,27
< system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s)
74c74
< system.physmem.totGap 34926000 # Total gap between requests
---
> system.physmem.totGap 34924000 # Total gap between requests
199,200c199,200
< system.physmem.totQLat 3928000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3887500 # Total ticks spent queuing
> system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst
204,205c204,205
< system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s
207c207
< system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s
219c219
< system.physmem.avgGap 65527.20 # Average gap between requests
---
> system.physmem.avgGap 65523.45 # Average gap between requests
224c224
< system.physmem.memoryStateTime::ACT 30394500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 30393500 # Time in different power states
237c237
< system.physmem.actBackEnergy::1 20168595 # Energy for active background per rank (pJ)
---
> system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ)
239c239
< system.physmem.preBackEnergy::1 1170000 # Energy for precharge background per rank (pJ)
---
> system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ)
241c241
< system.physmem.totalEnergy::1 25645770 # Total energy per rank (pJ)
---
> system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ)
243,269c243,245
< system.physmem.averagePower::1 815.802457 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 460 # Transaction distribution
< system.membus.trans_dist::ReadResp 460 # Transaction distribution
< system.membus.trans_dist::ReadExReq 73 # Transaction distribution
< system.membus.trans_dist::ReadExResp 73 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 533 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 533 # Request fanout histogram
< system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 14.2 # Layer utilization (%)
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.branchPred.lookups 1959 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted
---
> system.physmem.averagePower::1 815.785757 # Core power per rank (mW)
> system.cpu.branchPred.lookups 1972 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted
271,272c247,248
< system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 381 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 385 # Number of BTB hits
274c250
< system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage
276a253
> system.cpu_clk_domain.clock 500 # Clock period in ticks
281c258
< system.cpu.dtb.read_hits 1368 # DTB read hits
---
> system.cpu.dtb.read_hits 1370 # DTB read hits
284c261
< system.cpu.dtb.read_accesses 1379 # DTB read accesses
---
> system.cpu.dtb.read_accesses 1381 # DTB read accesses
289c266
< system.cpu.dtb.data_hits 2252 # DTB hits
---
> system.cpu.dtb.data_hits 2254 # DTB hits
292,293c269,270
< system.cpu.dtb.data_accesses 2266 # DTB accesses
< system.cpu.itb.fetch_hits 2630 # ITB hits
---
> system.cpu.dtb.data_accesses 2268 # DTB accesses
> system.cpu.itb.fetch_hits 2642 # ITB hits
296c273
< system.cpu.itb.fetch_accesses 2647 # ITB accesses
---
> system.cpu.itb.fetch_accesses 2659 # ITB accesses
310c287
< system.cpu.numCycles 70049 # number of cpu cycles simulated
---
> system.cpu.numCycles 70045 # number of cpu cycles simulated
315c292
< system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit
317,320c294,409
< system.cpu.cpi 10.945156 # CPI: cycles per instruction
< system.cpu.ipc 0.091365 # IPC: instructions per cycle
< system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 10.944531 # CPI: cycles per instruction
> system.cpu.ipc 0.091370 # IPC: instructions per cycle
> system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 1233 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.inst 1973 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 1973 # number of overall hits
> system.cpu.dcache.overall_hits::total 1973 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
> system.cpu.dcache.overall_misses::total 227 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.inst 2200 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 2200 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076404 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.103182 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
322,323c411,412
< system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks.
325c414
< system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks.
327,329c416,418
< system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 176.126032 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.085999 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.085999 # Average percentage of cache occupancy
334,341c423,430
< system.cpu.icache.tags.tag_accesses 5625 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 5625 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 2265 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 2265 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 2265 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 2265 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 2265 # number of overall hits
< system.cpu.icache.overall_hits::total 2265 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 5649 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits
> system.cpu.icache.overall_hits::total 2277 # number of overall hits
348,371c437,460
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2630 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2630 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2630 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138783 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.138783 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25915750 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25915750 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25915750 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25915750 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25915750 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25915750 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 71002.054795 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 71002.054795 # average overall miss latency
386,403c475,492
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25028250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25028250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25028250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25028250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25028250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25028250 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency
405,432d493
< system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 0 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
434c495
< system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 233.857006 # Cycle average of tags in use
439,441c500,502
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.857006 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy
462,469c523,530
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31686750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 31686750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5053000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5053000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 36739750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 36739750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 36739750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 36739750 # number of overall miss cycles
486,493c547,554
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570 # average overall miss latency
510,511c571,572
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25921750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25921750 # number of ReadReq MSHR miss cycles
514,517c575,578
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30069250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 30069250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30069250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30069250 # number of overall MSHR miss cycles
526,527c587,588
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435 # average ReadReq mshr miss latency
530,533c591,594
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency
535,646c596,646
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits
< system.cpu.dcache.overall_hits::total 1968 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
< system.cpu.dcache.overall_misses::total 227 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
> system.membus.trans_dist::ReadReq 460 # Transaction distribution
> system.membus.trans_dist::ReadResp 460 # Transaction distribution
> system.membus.trans_dist::ReadExReq 73 # Transaction distribution
> system.membus.trans_dist::ReadExResp 73 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 533 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 533 # Request fanout histogram
> system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
> system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 14.2 # Layer utilization (%)