4,5c4,5
< sim_ticks 35015500 # Number of ticks simulated
< final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 35024500 # Number of ticks simulated
> final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 57020 # Simulator instruction rate (inst/s)
< host_op_rate 57008 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 311836228 # Simulator tick rate (ticks/s)
< host_mem_usage 240292 # Number of bytes of host memory used
< host_seconds 0.11 # Real time elapsed on the host
---
> host_inst_rate 173753 # Simulator instruction rate (inst/s)
> host_op_rate 173686 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 950177695 # Simulator tick rate (ticks/s)
> host_mem_usage 289108 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
22,27c22,27
< system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s)
74c74
< system.physmem.totGap 34917000 # Total gap between requests
---
> system.physmem.totGap 34926000 # Total gap between requests
199,200c199,200
< system.physmem.totQLat 3823500 # Total ticks spent queuing
< system.physmem.totMemAccLat 13817250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3928000 # Total ticks spent queuing
> system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 7173.55 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst
204,205c204,205
< system.physmem.avgMemAccLat 25923.55 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s
207c207
< system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s
219c219
< system.physmem.avgGap 65510.32 # Average gap between requests
---
> system.physmem.avgGap 65527.20 # Average gap between requests
224c224
< system.physmem.memoryStateTime::ACT 30385500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 30394500 # Time in different power states
226d225
< system.membus.throughput 974197141 # Throughput (bytes/s)
233,236c232,244
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 34112 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 533 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 533 # Request fanout histogram
284c292
< system.cpu.numCycles 70031 # number of cpu cycles simulated
---
> system.cpu.numCycles 70049 # number of cpu cycles simulated
291,294c299,302
< system.cpu.cpi 10.942344 # CPI: cycles per instruction
< system.cpu.ipc 0.091388 # IPC: instructions per cycle
< system.cpu.tickCycles 12510 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 57521 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 10.945156 # CPI: cycles per instruction
> system.cpu.ipc 0.091365 # IPC: instructions per cycle
> system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped
296c304
< system.cpu.icache.tags.tagsinuse 176.143820 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use
301,303c309,311
< system.cpu.icache.tags.occ_blocks::cpu.inst 176.143820 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.086008 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.086008 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy
322,327c330,335
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25932750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25932750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25932750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25932750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25932750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25932750 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles
340,345c348,353
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71048.630137 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 71048.630137 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 71048.630137 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 71048.630137 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency
360,365c368,373
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25045250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25045250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25045250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25045250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25045250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25045250 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles
372,377c380,385
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68617.123288 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68617.123288 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
379d386
< system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s)
387,391c394,408
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
399c416
< system.cpu.l2cache.tags.tagsinuse 233.878182 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use
404,406c421,423
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.878182 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy
429,434c446,451
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5056000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5056000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 36782750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 36782750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 36782750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 36782750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles
453,458c470,475
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69260.273973 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69260.273973 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69010.787992 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69010.787992 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency
475,482c492,499
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25965250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25965250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30103250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 30103250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30103250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 30103250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles
491,498c508,515
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
501c518
< system.cpu.dcache.tags.tagsinuse 104.053835 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use
506,508c523,525
< system.cpu.dcache.tags.occ_blocks::cpu.inst 104.053835 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.025404 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025404 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy
531,534c548,551
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7727250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7727250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8696750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8696750 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles
555,558c572,575
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69574 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 69574 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency
587,590c604,607
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7154500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5130500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles
603,606c620,623
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency
< sim_ticks 35015500 # Number of ticks simulated
< final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 35024500 # Number of ticks simulated
> final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 57020 # Simulator instruction rate (inst/s)
< host_op_rate 57008 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 311836228 # Simulator tick rate (ticks/s)
< host_mem_usage 240292 # Number of bytes of host memory used
< host_seconds 0.11 # Real time elapsed on the host
---
> host_inst_rate 173753 # Simulator instruction rate (inst/s)
> host_op_rate 173686 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 950177695 # Simulator tick rate (ticks/s)
> host_mem_usage 289108 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
22,27c22,27
< system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s)
74c74
< system.physmem.totGap 34917000 # Total gap between requests
---
> system.physmem.totGap 34926000 # Total gap between requests
199,200c199,200
< system.physmem.totQLat 3823500 # Total ticks spent queuing
< system.physmem.totMemAccLat 13817250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3928000 # Total ticks spent queuing
> system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM
202c202
< system.physmem.avgQLat 7173.55 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst
204,205c204,205
< system.physmem.avgMemAccLat 25923.55 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s
207c207
< system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s
219c219
< system.physmem.avgGap 65510.32 # Average gap between requests
---
> system.physmem.avgGap 65527.20 # Average gap between requests
224c224
< system.physmem.memoryStateTime::ACT 30385500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 30394500 # Time in different power states
226d225
< system.membus.throughput 974197141 # Throughput (bytes/s)
233,236c232,244
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 34112 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 533 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 533 # Request fanout histogram
284c292
< system.cpu.numCycles 70031 # number of cpu cycles simulated
---
> system.cpu.numCycles 70049 # number of cpu cycles simulated
291,294c299,302
< system.cpu.cpi 10.942344 # CPI: cycles per instruction
< system.cpu.ipc 0.091388 # IPC: instructions per cycle
< system.cpu.tickCycles 12510 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 57521 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 10.945156 # CPI: cycles per instruction
> system.cpu.ipc 0.091365 # IPC: instructions per cycle
> system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped
296c304
< system.cpu.icache.tags.tagsinuse 176.143820 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use
301,303c309,311
< system.cpu.icache.tags.occ_blocks::cpu.inst 176.143820 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.086008 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.086008 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy
322,327c330,335
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25932750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25932750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25932750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25932750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25932750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25932750 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles
340,345c348,353
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71048.630137 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 71048.630137 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 71048.630137 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 71048.630137 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency
360,365c368,373
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25045250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25045250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25045250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25045250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25045250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25045250 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles
372,377c380,385
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68617.123288 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68617.123288 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
379d386
< system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s)
387,391c394,408
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
399c416
< system.cpu.l2cache.tags.tagsinuse 233.878182 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use
404,406c421,423
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.878182 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy
429,434c446,451
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5056000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5056000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 36782750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 36782750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 36782750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 36782750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles
453,458c470,475
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69260.273973 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69260.273973 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69010.787992 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69010.787992 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency
475,482c492,499
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25965250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25965250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30103250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 30103250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30103250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 30103250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles
491,498c508,515
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
501c518
< system.cpu.dcache.tags.tagsinuse 104.053835 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use
506,508c523,525
< system.cpu.dcache.tags.occ_blocks::cpu.inst 104.053835 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.025404 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025404 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy
531,534c548,551
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7727250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7727250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8696750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8696750 # number of WriteReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles
555,558c572,575
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69574 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 69574 # average WriteReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency
587,590c604,607
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7154500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5130500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles
603,606c620,623
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency