Cross Reference: /gem5/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt

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1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000041 # Number of seconds simulated 4sim_ticks 41083000 # Number of ticks simulated 5final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000041 # Number of seconds simulated 4sim_ticks 41083000 # Number of ticks simulated 5final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 172605 # Simulator instruction rate (inst/s) 8host_op_rate 172547 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1105034404 # Simulator tick rate (ticks/s) 10host_mem_usage 251288 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host	7host_inst_rate 217103 # Simulator instruction rate (inst/s) 8host_op_rate 217013 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1389706699 # Simulator tick rate (ticks/s) 10host_mem_usage 253264 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host
12sim_insts 6413 # Number of instructions simulated 13sim_ops 6413 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 19system.physmem.bytes_read::total 34048 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 532 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 565489375 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 263271913 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 828761288 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 565489375 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 565489375 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 565489375 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 263271913 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 828761288 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 532 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 73 # Per bank write bursts 46system.physmem.perBankRdBursts::1 39 # Per bank write bursts 47system.physmem.perBankRdBursts::2 36 # Per bank write bursts 48system.physmem.perBankRdBursts::3 54 # Per bank write bursts 49system.physmem.perBankRdBursts::4 45 # Per bank write bursts 50system.physmem.perBankRdBursts::5 21 # Per bank write bursts 51system.physmem.perBankRdBursts::6 1 # Per bank write bursts 52system.physmem.perBankRdBursts::7 5 # Per bank write bursts 53system.physmem.perBankRdBursts::8 0 # Per bank write bursts 54system.physmem.perBankRdBursts::9 1 # Per bank write bursts 55system.physmem.perBankRdBursts::10 21 # Per bank write bursts 56system.physmem.perBankRdBursts::11 29 # Per bank write bursts 57system.physmem.perBankRdBursts::12 19 # Per bank write bursts 58system.physmem.perBankRdBursts::13 127 # Per bank write bursts 59system.physmem.perBankRdBursts::14 47 # Per bank write bursts 60system.physmem.perBankRdBursts::15 14 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 40972000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 532 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 91 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 363.604396 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 235.588514 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 321.826485 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 22 24.18% 24.18% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 22 24.18% 48.35% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 13 14.29% 62.64% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 8 8.79% 71.43% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 5 5.49% 76.92% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 4 4.40% 81.32% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation 204system.physmem.totQLat 6580250 # Total ticks spent queuing 205system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 6.47 # Data bus utilization in percentage 216system.physmem.busUtilRead 6.47 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 436 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 77015.04 # Average gap between requests 225system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 264180 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 1956360 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 3932430 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 68640 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 13617300 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 928800 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 23977530 # Total energy per rank (pJ) 237system.physmem_0.averagePower 583.625643 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 32009500 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 39500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 1300000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 2418500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 7463000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 29862000 # Time in different power states 245system.physmem_1.actEnergy 421260 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 208725 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ) 256system.physmem_1.averagePower 589.365503 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 31744250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 288500 # Time in different power states 259system.physmem_1.memoryStateTime::REF 1300000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2003 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 377 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 322 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.fetch_hits 0 # ITB hits 280system.cpu.dtb.fetch_misses 0 # ITB misses 281system.cpu.dtb.fetch_acv 0 # ITB acv 282system.cpu.dtb.fetch_accesses 0 # ITB accesses 283system.cpu.dtb.read_hits 1365 # DTB read hits 284system.cpu.dtb.read_misses 11 # DTB read misses 285system.cpu.dtb.read_acv 0 # DTB read access violations 286system.cpu.dtb.read_accesses 1376 # DTB read accesses 287system.cpu.dtb.write_hits 884 # DTB write hits 288system.cpu.dtb.write_misses 3 # DTB write misses 289system.cpu.dtb.write_acv 0 # DTB write access violations 290system.cpu.dtb.write_accesses 887 # DTB write accesses 291system.cpu.dtb.data_hits 2249 # DTB hits 292system.cpu.dtb.data_misses 14 # DTB misses 293system.cpu.dtb.data_acv 0 # DTB access violations 294system.cpu.dtb.data_accesses 2263 # DTB accesses 295system.cpu.itb.fetch_hits 2686 # ITB hits 296system.cpu.itb.fetch_misses 17 # ITB misses 297system.cpu.itb.fetch_acv 0 # ITB acv 298system.cpu.itb.fetch_accesses 2703 # ITB accesses 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.read_acv 0 # DTB read access violations 302system.cpu.itb.read_accesses 0 # DTB read accesses 303system.cpu.itb.write_hits 0 # DTB write hits 304system.cpu.itb.write_misses 0 # DTB write misses 305system.cpu.itb.write_acv 0 # DTB write access violations 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.data_hits 0 # DTB hits 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses 311system.cpu.workload.num_syscalls 17 # Number of system calls 312system.cpu.pwrStateResidencyTicks::ON 41083000 # Cumulative time (in ticks) in various power states 313system.cpu.numCycles 82166 # number of cpu cycles simulated 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 316system.cpu.committedInsts 6413 # Number of instructions committed 317system.cpu.committedOps 6413 # Number of ops (including micro ops) committed 318system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit 319system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 320system.cpu.cpi 12.812412 # CPI: cycles per instruction 321system.cpu.ipc 0.078049 # IPC: instructions per cycle 322system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 323system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction 324system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction 325system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction 326system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction 327system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction 328system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction 329system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction	12sim_insts 6413 # Number of instructions simulated 13sim_ops 6413 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 19system.physmem.bytes_read::total 34048 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 532 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 565489375 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 263271913 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 828761288 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 565489375 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 565489375 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 565489375 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 263271913 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 828761288 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 532 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 73 # Per bank write bursts 46system.physmem.perBankRdBursts::1 39 # Per bank write bursts 47system.physmem.perBankRdBursts::2 36 # Per bank write bursts 48system.physmem.perBankRdBursts::3 54 # Per bank write bursts 49system.physmem.perBankRdBursts::4 45 # Per bank write bursts 50system.physmem.perBankRdBursts::5 21 # Per bank write bursts 51system.physmem.perBankRdBursts::6 1 # Per bank write bursts 52system.physmem.perBankRdBursts::7 5 # Per bank write bursts 53system.physmem.perBankRdBursts::8 0 # Per bank write bursts 54system.physmem.perBankRdBursts::9 1 # Per bank write bursts 55system.physmem.perBankRdBursts::10 21 # Per bank write bursts 56system.physmem.perBankRdBursts::11 29 # Per bank write bursts 57system.physmem.perBankRdBursts::12 19 # Per bank write bursts 58system.physmem.perBankRdBursts::13 127 # Per bank write bursts 59system.physmem.perBankRdBursts::14 47 # Per bank write bursts 60system.physmem.perBankRdBursts::15 14 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 40972000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 532 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 91 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 363.604396 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 235.588514 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 321.826485 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 22 24.18% 24.18% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 22 24.18% 48.35% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 13 14.29% 62.64% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 8 8.79% 71.43% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 5 5.49% 76.92% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 4 4.40% 81.32% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation 204system.physmem.totQLat 6580250 # Total ticks spent queuing 205system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 6.47 # Data bus utilization in percentage 216system.physmem.busUtilRead 6.47 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 436 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 77015.04 # Average gap between requests 225system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 264180 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 1956360 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 3932430 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 68640 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 13617300 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 928800 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 23977530 # Total energy per rank (pJ) 237system.physmem_0.averagePower 583.625643 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 32009500 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 39500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 1300000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 2418500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 7463000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 29862000 # Time in different power states 245system.physmem_1.actEnergy 421260 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 208725 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ) 256system.physmem_1.averagePower 589.365503 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 31744250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 288500 # Time in different power states 259system.physmem_1.memoryStateTime::REF 1300000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2003 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 377 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 322 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.fetch_hits 0 # ITB hits 280system.cpu.dtb.fetch_misses 0 # ITB misses 281system.cpu.dtb.fetch_acv 0 # ITB acv 282system.cpu.dtb.fetch_accesses 0 # ITB accesses 283system.cpu.dtb.read_hits 1365 # DTB read hits 284system.cpu.dtb.read_misses 11 # DTB read misses 285system.cpu.dtb.read_acv 0 # DTB read access violations 286system.cpu.dtb.read_accesses 1376 # DTB read accesses 287system.cpu.dtb.write_hits 884 # DTB write hits 288system.cpu.dtb.write_misses 3 # DTB write misses 289system.cpu.dtb.write_acv 0 # DTB write access violations 290system.cpu.dtb.write_accesses 887 # DTB write accesses 291system.cpu.dtb.data_hits 2249 # DTB hits 292system.cpu.dtb.data_misses 14 # DTB misses 293system.cpu.dtb.data_acv 0 # DTB access violations 294system.cpu.dtb.data_accesses 2263 # DTB accesses 295system.cpu.itb.fetch_hits 2686 # ITB hits 296system.cpu.itb.fetch_misses 17 # ITB misses 297system.cpu.itb.fetch_acv 0 # ITB acv 298system.cpu.itb.fetch_accesses 2703 # ITB accesses 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.read_acv 0 # DTB read access violations 302system.cpu.itb.read_accesses 0 # DTB read accesses 303system.cpu.itb.write_hits 0 # DTB write hits 304system.cpu.itb.write_misses 0 # DTB write misses 305system.cpu.itb.write_acv 0 # DTB write access violations 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.data_hits 0 # DTB hits 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses 311system.cpu.workload.num_syscalls 17 # Number of system calls 312system.cpu.pwrStateResidencyTicks::ON 41083000 # Cumulative time (in ticks) in various power states 313system.cpu.numCycles 82166 # number of cpu cycles simulated 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 316system.cpu.committedInsts 6413 # Number of instructions committed 317system.cpu.committedOps 6413 # Number of ops (including micro ops) committed 318system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit 319system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 320system.cpu.cpi 12.812412 # CPI: cycles per instruction 321system.cpu.ipc 0.078049 # IPC: instructions per cycle 322system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 323system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction 324system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction 325system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction 326system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction 327system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction 328system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction 329system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction
	330system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.88% # Class of committed instruction
330system.cpu.op_class_0::FloatDiv 0 0.00% 67.88% # Class of committed instruction	331system.cpu.op_class_0::FloatDiv 0 0.00% 67.88% # Class of committed instruction
	332system.cpu.op_class_0::FloatMisc 0 0.00% 67.88% # Class of committed instruction
331system.cpu.op_class_0::FloatSqrt 0 0.00% 67.88% # Class of committed instruction 332system.cpu.op_class_0::SimdAdd 0 0.00% 67.88% # Class of committed instruction 333system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction 334system.cpu.op_class_0::SimdAlu 0 0.00% 67.88% # Class of committed instruction 335system.cpu.op_class_0::SimdCmp 0 0.00% 67.88% # Class of committed instruction 336system.cpu.op_class_0::SimdCvt 0 0.00% 67.88% # Class of committed instruction 337system.cpu.op_class_0::SimdMisc 0 0.00% 67.88% # Class of committed instruction 338system.cpu.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction 339system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction 340system.cpu.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction 341system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction 342system.cpu.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction 343system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction 344system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction 345system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction 346system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction 347system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction 348system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction 349system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction 350system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction 351system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction	333system.cpu.op_class_0::FloatSqrt 0 0.00% 67.88% # Class of committed instruction 334system.cpu.op_class_0::SimdAdd 0 0.00% 67.88% # Class of committed instruction 335system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction 336system.cpu.op_class_0::SimdAlu 0 0.00% 67.88% # Class of committed instruction 337system.cpu.op_class_0::SimdCmp 0 0.00% 67.88% # Class of committed instruction 338system.cpu.op_class_0::SimdCvt 0 0.00% 67.88% # Class of committed instruction 339system.cpu.op_class_0::SimdMisc 0 0.00% 67.88% # Class of committed instruction 340system.cpu.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction 341system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction 342system.cpu.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction 343system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction 344system.cpu.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction 345system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction 346system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction 347system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction 348system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction 349system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction 350system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction 351system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction 352system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction 353system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction
352system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction 353system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction	354system.cpu.op_class_0::MemRead 1191 18.57% 86.45% # Class of committed instruction 355system.cpu.op_class_0::MemWrite 861 13.43% 99.88% # Class of committed instruction 356system.cpu.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 357system.cpu.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
354system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 355system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 356system.cpu.op_class_0::total 6413 # Class of committed instruction 357system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked 358system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped 359system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 360system.cpu.dcache.tags.replacements 0 # number of replacements 361system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use 362system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. 363system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 364system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. 365system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 366system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor 367system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy 368system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy 369system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 370system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 371system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 372system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 373system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses 374system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses 375system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 376system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits 377system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits 378system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits 379system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 380system.cpu.dcache.demand_hits::cpu.data 1990 # number of demand (read+write) hits 381system.cpu.dcache.demand_hits::total 1990 # number of demand (read+write) hits 382system.cpu.dcache.overall_hits::cpu.data 1990 # number of overall hits 383system.cpu.dcache.overall_hits::total 1990 # number of overall hits 384system.cpu.dcache.ReadReq_misses::cpu.data 96 # number of ReadReq misses 385system.cpu.dcache.ReadReq_misses::total 96 # number of ReadReq misses 386system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses 387system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 388system.cpu.dcache.demand_misses::cpu.data 221 # number of demand (read+write) misses 389system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses 390system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses 391system.cpu.dcache.overall_misses::total 221 # number of overall misses 392system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles 393system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles 394system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles 395system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles 396system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles 397system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles 398system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles 399system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles 400system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) 401system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) 402system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 403system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 404system.cpu.dcache.demand_accesses::cpu.data 2211 # number of demand (read+write) accesses 405system.cpu.dcache.demand_accesses::total 2211 # number of demand (read+write) accesses 406system.cpu.dcache.overall_accesses::cpu.data 2211 # number of overall (read+write) accesses 407system.cpu.dcache.overall_accesses::total 2211 # number of overall (read+write) accesses 408system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071322 # miss rate for ReadReq accesses 409system.cpu.dcache.ReadReq_miss_rate::total 0.071322 # miss rate for ReadReq accesses 410system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses 411system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 412system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 # miss rate for demand accesses 413system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses 414system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses 415system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses 416system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency 417system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency 418system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency 419system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency 420system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency 421system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency 422system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency 423system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency 424system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 425system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 426system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 427system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 428system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 429system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 430system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits 431system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 432system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits 433system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits 434system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits 435system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits 436system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses 437system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 438system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 439system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 440system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 441system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 442system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 443system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses 444system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles 445system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles 446system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles 447system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles 448system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles 449system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles 450system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles 451system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles 452system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses 453system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses 454system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 455system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 456system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for demand accesses 457system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses 458system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses 459system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses 460system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency 461system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency 462system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency 463system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency 464system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency 465system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency 466system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency 467system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency 468system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 469system.cpu.icache.tags.replacements 0 # number of replacements 470system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use 471system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. 472system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. 473system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. 474system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 475system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor 476system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy 477system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy 478system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 479system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 480system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id 481system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id 482system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses 483system.cpu.icache.tags.data_accesses 5736 # Number of data accesses 484system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 485system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits 486system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits 487system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits 488system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits 489system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits 490system.cpu.icache.overall_hits::total 2322 # number of overall hits 491system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 492system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 493system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 494system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 495system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 496system.cpu.icache.overall_misses::total 364 # number of overall misses 497system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles 498system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles 499system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles 500system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles 501system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles 502system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles 503system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) 504system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) 505system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses 506system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses 507system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses 508system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses 509system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses 510system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses 511system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses 512system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses 513system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses 514system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses 515system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency 516system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency 517system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency 518system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency 519system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency 520system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency 521system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 522system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 523system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 524system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 525system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 526system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 527system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses 528system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses 529system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses 530system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 531system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses 532system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses 533system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles 534system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles 535system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles 536system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles 537system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles 538system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles 539system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses 540system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses 541system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses 542system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses 543system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses 544system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses 545system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency 546system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency 547system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency 548system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency 549system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency 550system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency 551system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 552system.cpu.l2cache.tags.replacements 0 # number of replacements 553system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use 554system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 555system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. 556system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. 557system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 558system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor 559system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor 560system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy 561system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy 562system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy 563system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id 564system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 565system.cpu.l2cache.tags.age_task_id_blocks_1024::1 422 # Occupied blocks per task id 566system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id 567system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses 568system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses 569system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 570system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 571system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 572system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 573system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 574system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 575system.cpu.l2cache.overall_hits::total 1 # number of overall hits 576system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 577system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 578system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses 579system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses 580system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses 581system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses 582system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 583system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses 584system.cpu.l2cache.demand_misses::total 532 # number of demand (read+write) misses 585system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses 586system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses 587system.cpu.l2cache.overall_misses::total 532 # number of overall misses 588system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles 589system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles 590system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles 591system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles 592system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles 593system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles 594system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles 595system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles 596system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles 597system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles 598system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles 599system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles 600system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 601system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 602system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) 603system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses) 604system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses) 605system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses) 606system.cpu.l2cache.demand_accesses::cpu.inst 364 # number of demand (read+write) accesses 607system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses 608system.cpu.l2cache.demand_accesses::total 533 # number of demand (read+write) accesses 609system.cpu.l2cache.overall_accesses::cpu.inst 364 # number of overall (read+write) accesses 610system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses 611system.cpu.l2cache.overall_accesses::total 533 # number of overall (read+write) accesses 612system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 613system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 614system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997253 # miss rate for ReadCleanReq accesses 615system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997253 # miss rate for ReadCleanReq accesses 616system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 617system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 618system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997253 # miss rate for demand accesses 619system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::total 0.998124 # miss rate for demand accesses 621system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses 622system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses 624system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency 625system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency 626system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency 627system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency 628system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency 629system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency 632system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency 635system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency 636system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 643system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 644system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 645system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 646system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 647system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses 648system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 649system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 650system.cpu.l2cache.demand_mshr_misses::total 532 # number of demand (read+write) MSHR misses 651system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses 652system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 653system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses 654system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles 655system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles 656system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles 657system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles 658system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles 659system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles 660system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles 661system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles 662system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles 663system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles 664system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles 665system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles 666system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 667system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 668system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses 669system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses 670system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 671system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 672system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses 673system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 674system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses 675system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses 676system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 677system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses 678system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency 679system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency 680system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency 681system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency 682system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency 683system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency 684system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency 685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency 686system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency 687system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency 688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency 689system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency 690system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. 691system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 692system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 693system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 694system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 695system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 696system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 697system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution 698system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 699system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 700system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution 701system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution 702system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes) 703system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 704system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) 705system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes) 706system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 707system.cpu.toL2Bus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 708system.cpu.toL2Bus.snoops 0 # Total snoops (count) 709system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 710system.cpu.toL2Bus.snoop_fanout::samples 533 # Request fanout histogram 711system.cpu.toL2Bus.snoop_fanout::mean 0.001876 # Request fanout histogram 712system.cpu.toL2Bus.snoop_fanout::stdev 0.043315 # Request fanout histogram 713system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 714system.cpu.toL2Bus.snoop_fanout::0 532 99.81% 99.81% # Request fanout histogram 715system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram 716system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 717system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 718system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 719system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 720system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram 721system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks) 722system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 723system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks) 724system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 725system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) 726system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 727system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter. 728system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 729system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 730system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 731system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 732system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 733system.membus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 734system.membus.trans_dist::ReadResp 459 # Transaction distribution 735system.membus.trans_dist::ReadExReq 73 # Transaction distribution 736system.membus.trans_dist::ReadExResp 73 # Transaction distribution 737system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution 738system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes) 739system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes) 740system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes) 741system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes) 742system.membus.snoops 0 # Total snoops (count) 743system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 744system.membus.snoop_fanout::samples 532 # Request fanout histogram 745system.membus.snoop_fanout::mean 0 # Request fanout histogram 746system.membus.snoop_fanout::stdev 0 # Request fanout histogram 747system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 748system.membus.snoop_fanout::0 532 100.00% 100.00% # Request fanout histogram 749system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 750system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 751system.membus.snoop_fanout::min_value 0 # Request fanout histogram 752system.membus.snoop_fanout::max_value 0 # Request fanout histogram 753system.membus.snoop_fanout::total 532 # Request fanout histogram 754system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) 755system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) 756system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks) 757system.membus.respLayer1.utilization 6.9 # Layer utilization (%) 758 759---------- End Simulation Statistics ----------	358system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 359system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 360system.cpu.op_class_0::total 6413 # Class of committed instruction 361system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked 362system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped 363system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 364system.cpu.dcache.tags.replacements 0 # number of replacements 365system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use 366system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. 367system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 368system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. 369system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 370system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor 371system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy 372system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy 373system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 374system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 375system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 376system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 377system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses 378system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses 379system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 380system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits 381system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits 382system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits 383system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 384system.cpu.dcache.demand_hits::cpu.data 1990 # number of demand (read+write) hits 385system.cpu.dcache.demand_hits::total 1990 # number of demand (read+write) hits 386system.cpu.dcache.overall_hits::cpu.data 1990 # number of overall hits 387system.cpu.dcache.overall_hits::total 1990 # number of overall hits 388system.cpu.dcache.ReadReq_misses::cpu.data 96 # number of ReadReq misses 389system.cpu.dcache.ReadReq_misses::total 96 # number of ReadReq misses 390system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses 391system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 392system.cpu.dcache.demand_misses::cpu.data 221 # number of demand (read+write) misses 393system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses 394system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses 395system.cpu.dcache.overall_misses::total 221 # number of overall misses 396system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles 397system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles 398system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles 399system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles 400system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles 401system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles 402system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles 403system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles 404system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) 405system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) 406system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 407system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 408system.cpu.dcache.demand_accesses::cpu.data 2211 # number of demand (read+write) accesses 409system.cpu.dcache.demand_accesses::total 2211 # number of demand (read+write) accesses 410system.cpu.dcache.overall_accesses::cpu.data 2211 # number of overall (read+write) accesses 411system.cpu.dcache.overall_accesses::total 2211 # number of overall (read+write) accesses 412system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071322 # miss rate for ReadReq accesses 413system.cpu.dcache.ReadReq_miss_rate::total 0.071322 # miss rate for ReadReq accesses 414system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses 415system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 416system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 # miss rate for demand accesses 417system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses 418system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses 419system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses 420system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency 421system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency 422system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency 423system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency 424system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency 425system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency 426system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency 427system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency 428system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 429system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 430system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 431system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 432system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 433system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 434system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits 435system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 436system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits 437system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits 438system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits 439system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits 440system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses 441system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 442system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 443system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 444system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 445system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 446system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 447system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses 448system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles 449system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles 450system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles 451system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles 452system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles 453system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles 454system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles 455system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles 456system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses 457system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses 458system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 459system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 460system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for demand accesses 461system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses 462system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses 463system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses 464system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency 465system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency 466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency 467system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency 468system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency 469system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency 470system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency 471system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency 472system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 473system.cpu.icache.tags.replacements 0 # number of replacements 474system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use 475system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. 476system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. 477system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. 478system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 479system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor 480system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy 481system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy 482system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 483system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 484system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id 485system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id 486system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses 487system.cpu.icache.tags.data_accesses 5736 # Number of data accesses 488system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 489system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits 490system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits 491system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits 492system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits 493system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits 494system.cpu.icache.overall_hits::total 2322 # number of overall hits 495system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 496system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 497system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 498system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 499system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 500system.cpu.icache.overall_misses::total 364 # number of overall misses 501system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles 502system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles 503system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles 504system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles 505system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles 506system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles 507system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) 508system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) 509system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses 510system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses 511system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses 512system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses 513system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses 514system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses 515system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses 516system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses 517system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses 518system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses 519system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency 520system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency 521system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency 522system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency 523system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency 524system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency 525system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 526system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 527system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 528system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 529system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 530system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 531system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses 532system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses 533system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses 534system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 535system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses 536system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses 537system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles 538system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles 539system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles 540system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles 541system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles 542system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles 543system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses 544system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses 545system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses 546system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses 547system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses 548system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses 549system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency 550system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency 551system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency 552system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency 553system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency 554system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency 555system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 556system.cpu.l2cache.tags.replacements 0 # number of replacements 557system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use 558system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 559system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. 560system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. 561system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 562system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor 563system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor 564system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy 565system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy 566system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy 567system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id 568system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 569system.cpu.l2cache.tags.age_task_id_blocks_1024::1 422 # Occupied blocks per task id 570system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id 571system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses 572system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses 573system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 574system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 575system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 576system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 577system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 578system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 579system.cpu.l2cache.overall_hits::total 1 # number of overall hits 580system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 581system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 582system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses 583system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses 584system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses 585system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses 586system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 587system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses 588system.cpu.l2cache.demand_misses::total 532 # number of demand (read+write) misses 589system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses 590system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses 591system.cpu.l2cache.overall_misses::total 532 # number of overall misses 592system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles 593system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles 594system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles 595system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles 596system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles 597system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles 598system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles 599system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles 600system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles 601system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles 602system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles 603system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles 604system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 605system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 606system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) 607system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses) 608system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses) 609system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses) 610system.cpu.l2cache.demand_accesses::cpu.inst 364 # number of demand (read+write) accesses 611system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses 612system.cpu.l2cache.demand_accesses::total 533 # number of demand (read+write) accesses 613system.cpu.l2cache.overall_accesses::cpu.inst 364 # number of overall (read+write) accesses 614system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses 615system.cpu.l2cache.overall_accesses::total 533 # number of overall (read+write) accesses 616system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 617system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 618system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997253 # miss rate for ReadCleanReq accesses 619system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997253 # miss rate for ReadCleanReq accesses 620system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 621system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 622system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997253 # miss rate for demand accesses 623system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 624system.cpu.l2cache.demand_miss_rate::total 0.998124 # miss rate for demand accesses 625system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses 626system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 627system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses 628system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency 629system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency 630system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency 631system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency 632system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency 633system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency 634system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency 635system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency 636system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency 637system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency 638system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency 640system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 641system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 642system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 643system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 644system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 645system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 646system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 647system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 648system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 649system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 650system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 651system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses 652system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 653system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.demand_mshr_misses::total 532 # number of demand (read+write) MSHR misses 655system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses 656system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 657system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses 658system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles 659system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles 660system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles 661system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles 662system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles 663system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles 664system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles 665system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles 666system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles 667system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles 668system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles 669system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles 670system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 671system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 672system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses 673system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses 674system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 675system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 676system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses 677system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 678system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses 679system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses 680system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 681system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses 682system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency 683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency 684system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency 685system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency 686system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency 687system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency 688system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency 689system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency 690system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency 691system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency 692system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency 693system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency 694system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. 695system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 696system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 697system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 698system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 699system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 700system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 701system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution 702system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 703system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 704system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution 705system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution 706system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes) 707system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 708system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) 709system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes) 710system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 711system.cpu.toL2Bus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 712system.cpu.toL2Bus.snoops 0 # Total snoops (count) 713system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 714system.cpu.toL2Bus.snoop_fanout::samples 533 # Request fanout histogram 715system.cpu.toL2Bus.snoop_fanout::mean 0.001876 # Request fanout histogram 716system.cpu.toL2Bus.snoop_fanout::stdev 0.043315 # Request fanout histogram 717system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 718system.cpu.toL2Bus.snoop_fanout::0 532 99.81% 99.81% # Request fanout histogram 719system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram 720system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 721system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 722system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 723system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 724system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram 725system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks) 726system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 727system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks) 728system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 729system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) 730system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 731system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter. 732system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 733system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 734system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 735system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 736system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 737system.membus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states 738system.membus.trans_dist::ReadResp 459 # Transaction distribution 739system.membus.trans_dist::ReadExReq 73 # Transaction distribution 740system.membus.trans_dist::ReadExResp 73 # Transaction distribution 741system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution 742system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes) 743system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes) 744system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes) 745system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes) 746system.membus.snoops 0 # Total snoops (count) 747system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 748system.membus.snoop_fanout::samples 532 # Request fanout histogram 749system.membus.snoop_fanout::mean 0 # Request fanout histogram 750system.membus.snoop_fanout::stdev 0 # Request fanout histogram 751system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 752system.membus.snoop_fanout::0 532 100.00% 100.00% # Request fanout histogram 753system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 754system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 755system.membus.snoop_fanout::min_value 0 # Request fanout histogram 756system.membus.snoop_fanout::max_value 0 # Request fanout histogram 757system.membus.snoop_fanout::total 532 # Request fanout histogram 758system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) 759system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) 760system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks) 761system.membus.respLayer1.utilization 6.9 # Layer utilization (%) 762 763---------- End Simulation Statistics ----------