1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 9 unchanged lines hidden (view full) ---

18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=timing
24mem_ranges=
25memories=system.physmem
26num_work_ids=16
27readfile=
28symbolfile=
29work_begin_ckpt_count=0
30work_begin_cpu_id_exit=-1
31work_begin_exit_count=0
32work_cpus_ckpt_count=0
33work_end_ckpt_count=0

--- 599 unchanged lines hidden (view full) ---

633hit_latency=20
634sequential_access=false
635size=2097152
636
637[system.cpu.toL2Bus]
638type=CoherentXBar
639clk_domain=system.cpu_clk_domain
640eventq_index=0
641header_cycles=1
642snoop_filter=Null
643system=system
644use_default_range=false
645width=32
646master=system.cpu.l2cache.cpu_side
647slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
648
649[system.cpu.tracer]
650type=ExeTracer

--- 37 unchanged lines hidden (view full) ---

688eventq_index=0
689sys_clk_domain=system.clk_domain
690transition_latency=100000000
691
692[system.membus]
693type=CoherentXBar
694clk_domain=system.clk_domain
695eventq_index=0
696header_cycles=1
697snoop_filter=Null
698system=system
699use_default_range=false
700width=8
701master=system.physmem.port
702slave=system.system_port system.cpu.l2cache.mem_side
703
704[system.physmem]
705type=DRAMCtrl
706IDD0=0.075000
707IDD02=0.000000
708IDD2N=0.050000

--- 14 unchanged lines hidden (view full) ---

723IDD4W2=0.000000
724IDD5=0.220000
725IDD52=0.000000
726IDD6=0.000000
727IDD62=0.000000
728VDD=1.500000
729VDD2=0.000000
730activation_limit=4
731addr_mapping=RoRaBaChCo
732bank_groups_per_rank=0
733banks_per_rank=8
734burst_length=8
735channels=1
736clk_domain=system.clk_domain
737conf_table_reported=true
738device_bus_width=8
739device_rowbuffer_size=1024

--- 46 unchanged lines hidden ---