1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 5.187336 # Number of seconds simulated
4sim_ticks 5187335906000 # Number of ticks simulated
5final_tick 5187335906000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 5.196145 # Number of seconds simulated
4sim_ticks 5196144770000 # Number of ticks simulated
5final_tick 5196144770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 633010 # Simulator instruction rate (inst/s)
8host_op_rate 1220249 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 25590316667 # Simulator tick rate (ticks/s)
10host_mem_usage 632708 # Number of bytes of host memory used
11host_seconds 202.71 # Real time elapsed on the host
12sim_insts 128315489 # Number of instructions simulated
13sim_ops 247353048 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2850304 # Number of bytes read from this memory
| 7host_inst_rate 471788 # Simulator instruction rate (inst/s)
8host_op_rate 909467 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 19106715414 # Simulator tick rate (ticks/s)
10host_mem_usage 586268 # Number of bytes of host memory used
11host_seconds 271.95 # Real time elapsed on the host
12sim_insts 128304418 # Number of instructions simulated
13sim_ops 247333117 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2891776 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
| 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
16system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9026304 # Number of bytes read from this memory
18system.physmem.bytes_read::total 12701440 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 8120576 # Number of bytes written to this memory
22system.physmem.bytes_written::total 8120576 # Number of bytes written to this memory
23system.physmem.num_reads::pc.south_bridge.ide 44536 # Number of read requests responded to by this memory
| 17system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 8961408 # Number of bytes read from this memory
19system.physmem.bytes_read::total 12677312 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 8105792 # Number of bytes written to this memory
23system.physmem.bytes_written::total 8105792 # Number of bytes written to this memory
24system.physmem.num_reads::pc.south_bridge.ide 45184 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
24system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
| 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
25system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 141036 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 198460 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 126884 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 126884 # Number of write requests responded to by this memory
30system.physmem.bw_read::pc.south_bridge.ide 549474 # Total read bandwidth from this memory (bytes/s)
| 27system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.data 140022 # Number of read requests responded to by this memory
29system.physmem.num_reads::total 198083 # Number of read requests responded to by this memory
30system.physmem.num_writes::writebacks 126653 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 126653 # Number of write requests responded to by this memory
32system.physmem.bw_read::pc.south_bridge.ide 556523 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
|
31system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
| 34system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
|
32system.physmem.bw_read::cpu.inst 158947 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.data 1740065 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 2448548 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 158947 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 158947 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 1565462 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 1565462 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 1565462 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::pc.south_bridge.ide 549474 # Total bandwidth to/from this memory (bytes/s)
| 35system.physmem.bw_read::cpu.inst 158530 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.data 1724626 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::total 2439753 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_inst_read::cpu.inst 158530 # Instruction read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::total 158530 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_write::writebacks 1559963 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_write::total 1559963 # Write bandwidth from this memory (bytes/s)
42system.physmem.bw_total::writebacks 1559963 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::pc.south_bridge.ide 556523 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
|
41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
| 45system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
|
42system.physmem.bw_total::cpu.inst 158947 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::cpu.data 1740065 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::total 4014010 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.readReqs 198460 # Total number of read requests seen
46system.physmem.writeReqs 126884 # Total number of write requests seen
47system.physmem.cpureqs 326965 # Reqs generatd by CPU via cache - shady
48system.physmem.bytesRead 12701440 # Total number of bytes read from memory
49system.physmem.bytesWritten 8120576 # Total number of bytes written to memory
50system.physmem.bytesConsumedRd 12701440 # bytesRead derated as per pkt->getSize()
51system.physmem.bytesConsumedWr 8120576 # bytesWritten derated as per pkt->getSize()
52system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q
53system.physmem.neitherReadNorWrite 1615 # Reqs where no action is needed
54system.physmem.perBankRdReqs::0 12387 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::1 12046 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::2 12118 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::3 12449 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::4 12193 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::5 12119 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::6 12473 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::7 12536 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::8 12592 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::9 12290 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::10 12456 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::11 12641 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::12 12408 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::13 12254 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::14 12740 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::15 12648 # Track reads on a per bank basis
70system.physmem.perBankWrReqs::0 7793 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::1 7533 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::2 7699 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::3 7988 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::4 7862 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::5 7739 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::6 7964 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::7 8103 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::8 8131 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::9 7898 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::10 7933 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::11 8107 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::12 7973 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::13 7879 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::14 8152 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::15 8130 # Track writes on a per bank basis
| 46system.physmem.bw_total::cpu.inst 158530 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.data 1724626 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::total 3999716 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.readReqs 198083 # Total number of read requests seen
50system.physmem.writeReqs 126653 # Total number of write requests seen
51system.physmem.cpureqs 326336 # Reqs generatd by CPU via cache - shady
52system.physmem.bytesRead 12677312 # Total number of bytes read from memory
53system.physmem.bytesWritten 8105792 # Total number of bytes written to memory
54system.physmem.bytesConsumedRd 12677312 # bytesRead derated as per pkt->getSize()
55system.physmem.bytesConsumedWr 8105792 # bytesWritten derated as per pkt->getSize()
56system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q
57system.physmem.neitherReadNorWrite 1597 # Reqs where no action is needed
58system.physmem.perBankRdReqs::0 12388 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::1 12465 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::2 13064 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::3 12742 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::4 12822 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::5 12061 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::6 12170 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::7 12418 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::8 11780 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::9 11808 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::10 12169 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::11 12505 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::12 12558 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::13 12789 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::14 12227 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::15 12047 # Track reads on a per bank basis
74system.physmem.perBankWrReqs::0 7920 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::1 8110 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::2 8533 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::3 8387 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::4 8388 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::5 7744 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::6 7664 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::7 7959 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::8 7196 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::9 7383 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::10 7714 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::11 7959 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::12 8157 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::13 8159 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::14 7876 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis
|
86system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
| 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
87system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry
88system.physmem.totGap 5187335842500 # Total gap between requests
| 91system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry
92system.physmem.totGap 5196144706500 # Total gap between requests
|
89system.physmem.readPktSize::0 0 # Categorize read packet sizes
90system.physmem.readPktSize::1 0 # Categorize read packet sizes
91system.physmem.readPktSize::2 0 # Categorize read packet sizes
92system.physmem.readPktSize::3 0 # Categorize read packet sizes
93system.physmem.readPktSize::4 0 # Categorize read packet sizes
94system.physmem.readPktSize::5 0 # Categorize read packet sizes
| 93system.physmem.readPktSize::0 0 # Categorize read packet sizes
94system.physmem.readPktSize::1 0 # Categorize read packet sizes
95system.physmem.readPktSize::2 0 # Categorize read packet sizes
96system.physmem.readPktSize::3 0 # Categorize read packet sizes
97system.physmem.readPktSize::4 0 # Categorize read packet sizes
98system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
95system.physmem.readPktSize::6 198460 # Categorize read packet sizes
| 99system.physmem.readPktSize::6 198083 # Categorize read packet sizes
|
96system.physmem.writePktSize::0 0 # Categorize write packet sizes
97system.physmem.writePktSize::1 0 # Categorize write packet sizes
98system.physmem.writePktSize::2 0 # Categorize write packet sizes
99system.physmem.writePktSize::3 0 # Categorize write packet sizes
100system.physmem.writePktSize::4 0 # Categorize write packet sizes
101system.physmem.writePktSize::5 0 # Categorize write packet sizes
| 100system.physmem.writePktSize::0 0 # Categorize write packet sizes
101system.physmem.writePktSize::1 0 # Categorize write packet sizes
102system.physmem.writePktSize::2 0 # Categorize write packet sizes
103system.physmem.writePktSize::3 0 # Categorize write packet sizes
104system.physmem.writePktSize::4 0 # Categorize write packet sizes
105system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
102system.physmem.writePktSize::6 126884 # Categorize write packet sizes
103system.physmem.rdQLenPdf::0 155340 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::1 8720 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::2 6686 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::4 3378 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::5 2810 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::6 2218 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::7 2141 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::8 2080 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::9 2004 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::10 1276 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::11 1172 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::12 1102 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::13 1032 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::14 958 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::15 968 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::17 1055 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::18 518 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::19 325 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
| 106system.physmem.writePktSize::6 126653 # Categorize write packet sizes
107system.physmem.rdQLenPdf::0 154572 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::1 13375 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::2 7517 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::3 3048 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::4 2915 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::5 2517 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::6 1489 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::8 1265 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::9 1181 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::10 1109 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::12 1032 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::13 1095 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::14 1162 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::15 1135 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::16 924 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::17 646 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::18 350 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::19 220 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::20 26 # What read queue length does an incoming req see
|
124system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
| 128system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
135system.physmem.wrQLenPdf::0 4200 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::1 4548 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::2 5338 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::3 5455 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::4 5485 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::5 5501 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::6 5506 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::7 5508 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::8 5508 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::9 5517 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::10 5517 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::11 5517 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::12 5517 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::13 5517 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::14 5517 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::15 5517 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::16 5516 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::17 5516 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::19 5516 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::20 5516 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::21 5516 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::22 5516 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::23 1317 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::24 969 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::26 62 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::27 32 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
167system.physmem.totQLat 4133329999 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 7970683749 # Sum of mem lat for all requests
169system.physmem.totBusLat 991750000 # Total cycles spent in databus access
170system.physmem.totBankLat 2845603750 # Total cycles spent in bank access
171system.physmem.avgQLat 20838.57 # Average queueing delay per request
172system.physmem.avgBankLat 14346.38 # Average bank access latency per request
| 139system.physmem.wrQLenPdf::0 4307 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::1 4658 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::2 5438 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::3 5493 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::4 5496 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::5 5499 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::6 5500 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::7 5502 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::8 5502 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::9 5507 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::10 5507 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::11 5507 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::12 5507 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::13 5507 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::14 5507 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::15 5506 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::16 5506 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::17 5506 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::18 5506 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::19 5506 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::20 5506 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::21 5506 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::22 5506 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::24 849 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::25 69 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
171system.physmem.bytesPerActivate::samples 45242 # Bytes accessed per row activation
172system.physmem.bytesPerActivate::mean 458.910923 # Bytes accessed per row activation
173system.physmem.bytesPerActivate::gmean 168.789921 # Bytes accessed per row activation
174system.physmem.bytesPerActivate::stdev 1568.289191 # Bytes accessed per row activation
175system.physmem.bytesPerActivate::64-67 18577 41.06% 41.06% # Bytes accessed per row activation
176system.physmem.bytesPerActivate::128-131 7110 15.72% 56.78% # Bytes accessed per row activation
177system.physmem.bytesPerActivate::192-195 4218 9.32% 66.10% # Bytes accessed per row activation
178system.physmem.bytesPerActivate::256-259 2889 6.39% 72.49% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::320-323 2001 4.42% 76.91% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::384-387 1601 3.54% 80.45% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::448-451 1275 2.82% 83.27% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::512-515 961 2.12% 85.39% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::576-579 799 1.77% 87.16% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::640-643 633 1.40% 88.55% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::704-707 499 1.10% 89.66% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::768-771 460 1.02% 90.67% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::832-835 337 0.74% 91.42% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::896-899 345 0.76% 92.18% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::960-963 215 0.48% 92.66% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::1024-1027 394 0.87% 93.53% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::1088-1091 170 0.38% 93.90% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::1152-1155 159 0.35% 94.26% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1216-1219 128 0.28% 94.54% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1280-1283 109 0.24% 94.78% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1344-1347 88 0.19% 94.97% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1408-1411 127 0.28% 95.25% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1472-1475 644 1.42% 96.68% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1536-1539 160 0.35% 97.03% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::1600-1603 109 0.24% 97.27% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::1664-1667 90 0.20% 97.47% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1728-1731 61 0.13% 97.61% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1792-1795 44 0.10% 97.70% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::1856-1859 17 0.04% 97.74% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1920-1923 21 0.05% 97.79% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1984-1987 12 0.03% 97.81% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::2048-2051 37 0.08% 97.90% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::2112-2115 16 0.04% 97.93% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::2176-2179 11 0.02% 97.96% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.99% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::2304-2307 9 0.02% 98.01% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.02% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::2432-2435 9 0.02% 98.04% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::2496-2499 6 0.01% 98.05% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.08% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.09% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.09% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.11% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.11% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::2880-2883 3 0.01% 98.12% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.13% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::3008-3011 2 0.00% 98.13% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::3072-3075 5 0.01% 98.15% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::3136-3139 3 0.01% 98.15% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.16% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3264-3267 2 0.00% 98.16% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3328-3331 3 0.01% 98.17% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3392-3395 3 0.01% 98.17% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.20% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::3520-3523 1 0.00% 98.20% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::3584-3587 1 0.00% 98.20% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.21% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.22% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.24% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::3904-3907 2 0.00% 98.25% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::4032-4035 3 0.01% 98.26% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::4096-4099 14 0.03% 98.29% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::4160-4163 6 0.01% 98.30% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4224-4227 2 0.00% 98.31% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.31% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.32% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.32% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4480-4483 3 0.01% 98.33% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.34% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.34% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.34% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.35% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::4928-4931 1 0.00% 98.35% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.35% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::5056-5059 4 0.01% 98.36% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::5120-5123 2 0.00% 98.37% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.37% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::5248-5251 1 0.00% 98.37% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.38% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.38% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::5440-5443 2 0.00% 98.38% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::5504-5507 2 0.00% 98.39% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5632-5635 1 0.00% 98.39% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.39% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::5760-5763 2 0.00% 98.40% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.40% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.40% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.40% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::6400-6403 1 0.00% 98.41% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.41% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.42% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::6720-6723 4 0.01% 98.42% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::6848-6851 12 0.03% 98.45% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::6912-6915 2 0.00% 98.45% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.46% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.46% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.46% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::7168-7171 7 0.02% 98.48% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::7232-7235 2 0.00% 98.48% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::7424-7427 2 0.00% 98.49% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.49% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.49% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.50% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.50% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.50% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.51% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::8192-8195 340 0.75% 99.26% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.26% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.26% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::8576-8579 2 0.00% 99.27% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.27% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.27% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.27% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.28% # Bytes accessed per row activation
291system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.28% # Bytes accessed per row activation
292system.physmem.bytesPerActivate::9216-9219 7 0.02% 99.29% # Bytes accessed per row activation
293system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.29% # Bytes accessed per row activation
294system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.30% # Bytes accessed per row activation
295system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.30% # Bytes accessed per row activation
296system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.30% # Bytes accessed per row activation
297system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.30% # Bytes accessed per row activation
298system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.31% # Bytes accessed per row activation
299system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.31% # Bytes accessed per row activation
300system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.31% # Bytes accessed per row activation
301system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.31% # Bytes accessed per row activation
302system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.31% # Bytes accessed per row activation
303system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.32% # Bytes accessed per row activation
304system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.32% # Bytes accessed per row activation
305system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.32% # Bytes accessed per row activation
306system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.33% # Bytes accessed per row activation
307system.physmem.bytesPerActivate::14912-14915 8 0.02% 99.34% # Bytes accessed per row activation
308system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.35% # Bytes accessed per row activation
309system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.35% # Bytes accessed per row activation
310system.physmem.bytesPerActivate::15360-15363 10 0.02% 99.37% # Bytes accessed per row activation
311system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.37% # Bytes accessed per row activation
312system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.37% # Bytes accessed per row activation
313system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.38% # Bytes accessed per row activation
314system.physmem.bytesPerActivate::16384-16387 237 0.52% 99.90% # Bytes accessed per row activation
315system.physmem.bytesPerActivate::16448-16451 13 0.03% 99.93% # Bytes accessed per row activation
316system.physmem.bytesPerActivate::16512-16515 17 0.04% 99.97% # Bytes accessed per row activation
317system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.97% # Bytes accessed per row activation
318system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.98% # Bytes accessed per row activation
319system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation
320system.physmem.bytesPerActivate::16960-16963 2 0.00% 99.99% # Bytes accessed per row activation
321system.physmem.bytesPerActivate::17280-17283 2 0.00% 100.00% # Bytes accessed per row activation
322system.physmem.bytesPerActivate::17600-17603 1 0.00% 100.00% # Bytes accessed per row activation
323system.physmem.bytesPerActivate::17856-17859 1 0.00% 100.00% # Bytes accessed per row activation
324system.physmem.bytesPerActivate::total 45242 # Bytes accessed per row activation
325system.physmem.totQLat 3435518998 # Total cycles spent in queuing delays
326system.physmem.totMemAccLat 7067756498 # Sum of mem lat for all requests
327system.physmem.totBusLat 990065000 # Total cycles spent in databus access
328system.physmem.totBankLat 2642172500 # Total cycles spent in bank access
329system.physmem.avgQLat 17349.97 # Average queueing delay per request
330system.physmem.avgBankLat 13343.43 # Average bank access latency per request
|
173system.physmem.avgBusLat 5000.00 # Average bus latency per request
| 331system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
174system.physmem.avgMemAccLat 40184.94 # Average memory access latency
175system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s
176system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s
177system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s
178system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s
| 332system.physmem.avgMemAccLat 35693.40 # Average memory access latency
333system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
334system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
335system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
336system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
|
179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
180system.physmem.busUtil 0.03 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.00 # Average read queue length over time
| 337system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
338system.physmem.busUtil 0.03 # Data bus utilization in percentage
339system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
182system.physmem.avgWrQLen 12.90 # Average write queue length over time
183system.physmem.readRowHits 174211 # Number of row buffer hits during reads
184system.physmem.writeRowHits 94671 # Number of row buffer hits during writes
185system.physmem.readRowHitRate 87.83 # Row buffer hit rate for reads
186system.physmem.writeRowHitRate 74.61 # Row buffer hit rate for writes
187system.physmem.avgGap 15944157.08 # Average gap between requests
188system.iocache.replacements 47504 # number of replacements
189system.iocache.tagsinuse 0.157150 # Cycle average of tags in use
| 340system.physmem.avgWrQLen 9.35 # Average write queue length over time
341system.physmem.readRowHits 181015 # Number of row buffer hits during reads
342system.physmem.writeRowHits 98394 # Number of row buffer hits during writes
343system.physmem.readRowHitRate 91.42 # Row buffer hit rate for reads
344system.physmem.writeRowHitRate 77.69 # Row buffer hit rate for writes
345system.physmem.avgGap 16001135.40 # Average gap between requests
346system.membus.throughput 4358895 # Throughput (bytes/s)
347system.membus.trans_dist::ReadReq 623371 # Transaction distribution
348system.membus.trans_dist::ReadResp 623371 # Transaction distribution
349system.membus.trans_dist::WriteReq 13727 # Transaction distribution
350system.membus.trans_dist::WriteResp 13727 # Transaction distribution
351system.membus.trans_dist::Writeback 126653 # Transaction distribution
352system.membus.trans_dist::UpgradeReq 2147 # Transaction distribution
353system.membus.trans_dist::UpgradeResp 1615 # Transaction distribution
354system.membus.trans_dist::ReadExReq 159120 # Transaction distribution
355system.membus.trans_dist::ReadExResp 159120 # Transaction distribution
356system.membus.trans_dist::MessageReq 1656 # Transaction distribution
357system.membus.trans_dist::MessageResp 1656 # Transaction distribution
358system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes)
359system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes)
360system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390174 # Packet count per connected master and slave (bytes)
361system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480118 # Packet count per connected master and slave (bytes)
362system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes)
363system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580408 # Packet count per connected master and slave (bytes)
364system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139407 # Packet count per connected master and slave (bytes)
365system.membus.pkt_count_system.iocache.mem_side::total 139407 # Packet count per connected master and slave (bytes)
366system.membus.pkt_count::system.physmem.port 529581 # Packet count per connected master and slave (bytes)
367system.membus.pkt_count::system.bridge.slave 480118 # Packet count per connected master and slave (bytes)
368system.membus.pkt_count::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes)
369system.membus.pkt_count::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes)
370system.membus.pkt_count::total 1723127 # Packet count per connected master and slave (bytes)
371system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes)
372system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes)
373system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14904512 # Cumulative packet size per connected master and slave (bytes)
374system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes)
375system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes)
376system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16571083 # Cumulative packet size per connected master and slave (bytes)
377system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5878592 # Cumulative packet size per connected master and slave (bytes)
378system.membus.tot_pkt_size_system.iocache.mem_side::total 5878592 # Cumulative packet size per connected master and slave (bytes)
379system.membus.tot_pkt_size::system.physmem.port 20783104 # Cumulative packet size per connected master and slave (bytes)
380system.membus.tot_pkt_size::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes)
381system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes)
382system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes)
383system.membus.tot_pkt_size::total 22456299 # Cumulative packet size per connected master and slave (bytes)
384system.membus.data_through_bus 22456299 # Total data (bytes)
385system.membus.snoop_data_through_bus 193152 # Total snoop data (bytes)
386system.membus.reqLayer0.occupancy 1348670998 # Layer occupancy (ticks)
387system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
388system.membus.reqLayer1.occupancy 256617500 # Layer occupancy (ticks)
389system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
390system.membus.reqLayer2.occupancy 359320000 # Layer occupancy (ticks)
391system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
392system.membus.reqLayer3.occupancy 3312000 # Layer occupancy (ticks)
393system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
394system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks)
395system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
396system.membus.respLayer2.occupancy 2607874799 # Layer occupancy (ticks)
397system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
398system.membus.respLayer4.occupancy 428809000 # Layer occupancy (ticks)
399system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
400system.iocache.replacements 47501 # number of replacements
401system.iocache.tagsinuse 0.169264 # Cycle average of tags in use
|
190system.iocache.total_refs 0 # Total number of references to valid blocks.
| 402system.iocache.total_refs 0 # Total number of references to valid blocks.
|
191system.iocache.sampled_refs 47520 # Sample count of references to valid blocks.
| 403system.iocache.sampled_refs 47517 # Sample count of references to valid blocks.
|
192system.iocache.avg_refs 0 # Average number of references to valid blocks.
| 404system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
193system.iocache.warmup_cycle 5044705088000 # Cycle when the warmup percentage was hit.
194system.iocache.occ_blocks::pc.south_bridge.ide 0.157150 # Average occupied blocks per requestor
195system.iocache.occ_percent::pc.south_bridge.ide 0.009822 # Average percentage of cache occupancy
196system.iocache.occ_percent::total 0.009822 # Average percentage of cache occupancy
197system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses
198system.iocache.ReadReq_misses::total 837 # number of ReadReq misses
| 405system.iocache.warmup_cycle 5049524013000 # Cycle when the warmup percentage was hit.
406system.iocache.occ_blocks::pc.south_bridge.ide 0.169264 # Average occupied blocks per requestor
407system.iocache.occ_percent::pc.south_bridge.ide 0.010579 # Average percentage of cache occupancy
408system.iocache.occ_percent::total 0.010579 # Average percentage of cache occupancy
409system.iocache.ReadReq_misses::pc.south_bridge.ide 834 # number of ReadReq misses
410system.iocache.ReadReq_misses::total 834 # number of ReadReq misses
|
199system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
200system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
| 411system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
412system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
201system.iocache.demand_misses::pc.south_bridge.ide 47557 # number of demand (read+write) misses
202system.iocache.demand_misses::total 47557 # number of demand (read+write) misses
203system.iocache.overall_misses::pc.south_bridge.ide 47557 # number of overall misses
204system.iocache.overall_misses::total 47557 # number of overall misses
205system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139731143 # number of ReadReq miss cycles
206system.iocache.ReadReq_miss_latency::total 139731143 # number of ReadReq miss cycles
207system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10765565415 # number of WriteReq miss cycles
208system.iocache.WriteReq_miss_latency::total 10765565415 # number of WriteReq miss cycles
209system.iocache.demand_miss_latency::pc.south_bridge.ide 10905296558 # number of demand (read+write) miss cycles
210system.iocache.demand_miss_latency::total 10905296558 # number of demand (read+write) miss cycles
211system.iocache.overall_miss_latency::pc.south_bridge.ide 10905296558 # number of overall miss cycles
212system.iocache.overall_miss_latency::total 10905296558 # number of overall miss cycles
213system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses)
214system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses)
| 413system.iocache.demand_misses::pc.south_bridge.ide 47554 # number of demand (read+write) misses
414system.iocache.demand_misses::total 47554 # number of demand (read+write) misses
415system.iocache.overall_misses::pc.south_bridge.ide 47554 # number of overall misses
416system.iocache.overall_misses::total 47554 # number of overall misses
417system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142703185 # number of ReadReq miss cycles
418system.iocache.ReadReq_miss_latency::total 142703185 # number of ReadReq miss cycles
419system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10862337325 # number of WriteReq miss cycles
420system.iocache.WriteReq_miss_latency::total 10862337325 # number of WriteReq miss cycles
421system.iocache.demand_miss_latency::pc.south_bridge.ide 11005040510 # number of demand (read+write) miss cycles
422system.iocache.demand_miss_latency::total 11005040510 # number of demand (read+write) miss cycles
423system.iocache.overall_miss_latency::pc.south_bridge.ide 11005040510 # number of overall miss cycles
424system.iocache.overall_miss_latency::total 11005040510 # number of overall miss cycles
425system.iocache.ReadReq_accesses::pc.south_bridge.ide 834 # number of ReadReq accesses(hits+misses)
426system.iocache.ReadReq_accesses::total 834 # number of ReadReq accesses(hits+misses)
|
215system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
216system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
| 427system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
428system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
217system.iocache.demand_accesses::pc.south_bridge.ide 47557 # number of demand (read+write) accesses
218system.iocache.demand_accesses::total 47557 # number of demand (read+write) accesses
219system.iocache.overall_accesses::pc.south_bridge.ide 47557 # number of overall (read+write) accesses
220system.iocache.overall_accesses::total 47557 # number of overall (read+write) accesses
| 429system.iocache.demand_accesses::pc.south_bridge.ide 47554 # number of demand (read+write) accesses
430system.iocache.demand_accesses::total 47554 # number of demand (read+write) accesses
431system.iocache.overall_accesses::pc.south_bridge.ide 47554 # number of overall (read+write) accesses
432system.iocache.overall_accesses::total 47554 # number of overall (read+write) accesses
|
221system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
222system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
223system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
224system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
225system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
226system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
227system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
228system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
| 433system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
434system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
435system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
436system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
437system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
438system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
439system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
440system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
229system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166942.823178 # average ReadReq miss latency
230system.iocache.ReadReq_avg_miss_latency::total 166942.823178 # average ReadReq miss latency
231system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 230427.341931 # average WriteReq miss latency
232system.iocache.WriteReq_avg_miss_latency::total 230427.341931 # average WriteReq miss latency
233system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency
234system.iocache.demand_avg_miss_latency::total 229310.018672 # average overall miss latency
235system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency
236system.iocache.overall_avg_miss_latency::total 229310.018672 # average overall miss latency
237system.iocache.blocked_cycles::no_mshrs 177808 # number of cycles access was blocked
| 441system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171106.936451 # average ReadReq miss latency
442system.iocache.ReadReq_avg_miss_latency::total 171106.936451 # average ReadReq miss latency
443system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 232498.658497 # average WriteReq miss latency
444system.iocache.WriteReq_avg_miss_latency::total 232498.658497 # average WriteReq miss latency
445system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency
446system.iocache.demand_avg_miss_latency::total 231421.973125 # average overall miss latency
447system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency
448system.iocache.overall_avg_miss_latency::total 231421.973125 # average overall miss latency
449system.iocache.blocked_cycles::no_mshrs 174194 # number of cycles access was blocked
|
238system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
| 450system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
239system.iocache.blocked::no_mshrs 16153 # number of cycles access was blocked
| 451system.iocache.blocked::no_mshrs 16040 # number of cycles access was blocked
|
240system.iocache.blocked::no_targets 0 # number of cycles access was blocked
| 452system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
241system.iocache.avg_blocked_cycles::no_mshrs 11.007739 # average number of cycles each access was blocked
| 453system.iocache.avg_blocked_cycles::no_mshrs 10.859975 # average number of cycles each access was blocked
|
242system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
243system.iocache.fast_writes 0 # number of fast writes performed
244system.iocache.cache_copies 0 # number of cache copies performed
245system.iocache.writebacks::writebacks 46669 # number of writebacks
246system.iocache.writebacks::total 46669 # number of writebacks
| 454system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
455system.iocache.fast_writes 0 # number of fast writes performed
456system.iocache.cache_copies 0 # number of cache copies performed
457system.iocache.writebacks::writebacks 46669 # number of writebacks
458system.iocache.writebacks::total 46669 # number of writebacks
|
247system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses
248system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses
| 459system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 834 # number of ReadReq MSHR misses
460system.iocache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses
|
249system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
250system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
| 461system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
462system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
|
251system.iocache.demand_mshr_misses::pc.south_bridge.ide 47557 # number of demand (read+write) MSHR misses
252system.iocache.demand_mshr_misses::total 47557 # number of demand (read+write) MSHR misses
253system.iocache.overall_mshr_misses::pc.south_bridge.ide 47557 # number of overall MSHR misses
254system.iocache.overall_mshr_misses::total 47557 # number of overall MSHR misses
255system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96185423 # number of ReadReq MSHR miss cycles
256system.iocache.ReadReq_mshr_miss_latency::total 96185423 # number of ReadReq MSHR miss cycles
257system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8334760316 # number of WriteReq MSHR miss cycles
258system.iocache.WriteReq_mshr_miss_latency::total 8334760316 # number of WriteReq MSHR miss cycles
259system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of demand (read+write) MSHR miss cycles
260system.iocache.demand_mshr_miss_latency::total 8430945739 # number of demand (read+write) MSHR miss cycles
261system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of overall MSHR miss cycles
262system.iocache.overall_mshr_miss_latency::total 8430945739 # number of overall MSHR miss cycles
| 463system.iocache.demand_mshr_misses::pc.south_bridge.ide 47554 # number of demand (read+write) MSHR misses
464system.iocache.demand_mshr_misses::total 47554 # number of demand (read+write) MSHR misses
465system.iocache.overall_mshr_misses::pc.south_bridge.ide 47554 # number of overall MSHR misses
466system.iocache.overall_mshr_misses::total 47554 # number of overall MSHR misses
467system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99319185 # number of ReadReq MSHR miss cycles
468system.iocache.ReadReq_mshr_miss_latency::total 99319185 # number of ReadReq MSHR miss cycles
469system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8432090325 # number of WriteReq MSHR miss cycles
470system.iocache.WriteReq_mshr_miss_latency::total 8432090325 # number of WriteReq MSHR miss cycles
471system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of demand (read+write) MSHR miss cycles
472system.iocache.demand_mshr_miss_latency::total 8531409510 # number of demand (read+write) MSHR miss cycles
473system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of overall MSHR miss cycles
474system.iocache.overall_mshr_miss_latency::total 8531409510 # number of overall MSHR miss cycles
|
263system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
264system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
265system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
266system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
267system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
268system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
269system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
270system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
| 475system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
476system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
477system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
478system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
479system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
480system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
481system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
482system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
271system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114916.873357 # average ReadReq mshr miss latency
272system.iocache.ReadReq_avg_mshr_miss_latency::total 114916.873357 # average ReadReq mshr miss latency
273system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 178398.123202 # average WriteReq mshr miss latency
274system.iocache.WriteReq_avg_mshr_miss_latency::total 178398.123202 # average WriteReq mshr miss latency
275system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency
276system.iocache.demand_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency
277system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency
278system.iocache.overall_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency
| 483system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119087.751799 # average ReadReq mshr miss latency
484system.iocache.ReadReq_avg_mshr_miss_latency::total 119087.751799 # average ReadReq mshr miss latency
485system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 180481.385381 # average WriteReq mshr miss latency
486system.iocache.WriteReq_avg_mshr_miss_latency::total 180481.385381 # average WriteReq mshr miss latency
487system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency
488system.iocache.demand_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency
489system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency
490system.iocache.overall_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency
|
279system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
280system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
281system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
282system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
283system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
284system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
285system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
286system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
287system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
288system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
289system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
290system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
291system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
| 491system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
492system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
493system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
494system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
495system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
496system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
497system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
498system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
499system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
500system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
501system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
502system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
503system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
292system.cpu.numCycles 10374671812 # number of cpu cycles simulated
| 504system.iobus.throughput 631272 # Throughput (bytes/s)
505system.iobus.trans_dist::ReadReq 230083 # Transaction distribution
506system.iobus.trans_dist::ReadResp 230083 # Transaction distribution
507system.iobus.trans_dist::WriteReq 57530 # Transaction distribution
508system.iobus.trans_dist::WriteResp 57530 # Transaction distribution
509system.iobus.trans_dist::MessageReq 1656 # Transaction distribution
510system.iobus.trans_dist::MessageResp 1656 # Transaction distribution
511system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
512system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
513system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
514system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
515system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
516system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
517system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
518system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
519system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
520system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
521system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
522system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
523system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
524system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
525system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
526system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
527system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
528system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
529system.iobus.pkt_count_system.bridge.master::total 480118 # Packet count per connected master and slave (bytes)
530system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes)
531system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95108 # Packet count per connected master and slave (bytes)
532system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes)
533system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes)
534system.iobus.pkt_count::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes)
535system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
536system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
537system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
538system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
539system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
540system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
541system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
542system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
543system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
544system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
545system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
546system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
547system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
548system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
549system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
550system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
551system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
552system.iobus.pkt_count::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes)
553system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
554system.iobus.pkt_count::total 578538 # Packet count per connected master and slave (bytes)
555system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
556system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
557system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
558system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
559system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
560system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
561system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
562system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
563system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
564system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
565system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
566system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
567system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
568system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
569system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
570system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
571system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
572system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
573system.iobus.tot_pkt_size_system.bridge.master::total 246342 # Cumulative packet size per connected master and slave (bytes)
574system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes)
575system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027216 # Cumulative packet size per connected master and slave (bytes)
576system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes)
577system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes)
578system.iobus.tot_pkt_size::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes)
579system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
580system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
581system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
582system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
583system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
584system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
585system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
586system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
587system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
588system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
589system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
590system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
591system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
592system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
593system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
594system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
595system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
596system.iobus.tot_pkt_size::system.iocache.cpu_side 3027216 # Cumulative packet size per connected master and slave (bytes)
597system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
598system.iobus.tot_pkt_size::total 3280182 # Cumulative packet size per connected master and slave (bytes)
599system.iobus.data_through_bus 3280182 # Total data (bytes)
600system.iobus.reqLayer0.occupancy 3949664 # Layer occupancy (ticks)
601system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
602system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
603system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
604system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
605system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
606system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
607system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
608system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
609system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
610system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
611system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
612system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
613system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
614system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
615system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
616system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
617system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
618system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks)
619system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
620system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
621system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
622system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
623system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
624system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
625system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
626system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks)
627system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
628system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
629system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
630system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
631system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
632system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
633system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
634system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
635system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
636system.iobus.reqLayer18.occupancy 424330510 # Layer occupancy (ticks)
637system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
638system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
639system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
640system.iobus.respLayer0.occupancy 469308000 # Layer occupancy (ticks)
641system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
642system.iobus.respLayer1.occupancy 52196000 # Layer occupancy (ticks)
643system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
644system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks)
645system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
646system.cpu.numCycles 10392289540 # number of cpu cycles simulated
|
293system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
294system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 647system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
648system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
295system.cpu.committedInsts 128315489 # Number of instructions committed
296system.cpu.committedOps 247353048 # Number of ops (including micro ops) committed
297system.cpu.num_int_alu_accesses 232087369 # Number of integer alu accesses
| 649system.cpu.committedInsts 128304418 # Number of instructions committed
650system.cpu.committedOps 247333117 # Number of ops (including micro ops) committed
651system.cpu.num_int_alu_accesses 232067207 # Number of integer alu accesses
|
298system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
| 652system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
299system.cpu.num_func_calls 2299349 # number of times a function call or return occured
300system.cpu.num_conditional_control_insts 23166071 # number of instructions that are conditional controls
301system.cpu.num_int_insts 232087369 # number of integer instructions
| 653system.cpu.num_func_calls 2300061 # number of times a function call or return occured
654system.cpu.num_conditional_control_insts 23160261 # number of instructions that are conditional controls
655system.cpu.num_int_insts 232067207 # number of integer instructions
|
302system.cpu.num_fp_insts 0 # number of float instructions
| 656system.cpu.num_fp_insts 0 # number of float instructions
|
303system.cpu.num_int_register_reads 567244076 # number of times the integer registers were read
304system.cpu.num_int_register_writes 293343891 # number of times the integer registers were written
| 657system.cpu.num_int_register_reads 567198543 # number of times the integer registers were read
658system.cpu.num_int_register_writes 293301890 # number of times the integer registers were written
|
305system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
306system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
| 659system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
660system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
307system.cpu.num_mem_refs 22240299 # number of memory refs
308system.cpu.num_load_insts 13876403 # Number of load instructions
309system.cpu.num_store_insts 8363896 # Number of store instructions
310system.cpu.num_idle_cycles 9773542516.998116 # Number of idle cycles
311system.cpu.num_busy_cycles 601129295.001884 # Number of busy cycles
312system.cpu.not_idle_fraction 0.057942 # Percentage of non-idle cycles
313system.cpu.idle_fraction 0.942058 # Percentage of idle cycles
| 661system.cpu.num_mem_refs 22245318 # number of memory refs
662system.cpu.num_load_insts 13878816 # Number of load instructions
663system.cpu.num_store_insts 8366502 # Number of store instructions
664system.cpu.num_idle_cycles 9785692797.998116 # Number of idle cycles
665system.cpu.num_busy_cycles 606596742.001883 # Number of busy cycles
666system.cpu.not_idle_fraction 0.058370 # Percentage of non-idle cycles
667system.cpu.idle_fraction 0.941630 # Percentage of idle cycles
|
314system.cpu.kern.inst.arm 0 # number of arm instructions executed
315system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
| 668system.cpu.kern.inst.arm 0 # number of arm instructions executed
669system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
316system.cpu.icache.replacements 790572 # number of replacements
317system.cpu.icache.tagsinuse 510.408986 # Cycle average of tags in use
318system.cpu.icache.total_refs 144555062 # Total number of references to valid blocks.
319system.cpu.icache.sampled_refs 791084 # Sample count of references to valid blocks.
320system.cpu.icache.avg_refs 182.730357 # Average number of references to valid blocks.
321system.cpu.icache.warmup_cycle 160005789000 # Cycle when the warmup percentage was hit.
322system.cpu.icache.occ_blocks::cpu.inst 510.408986 # Average occupied blocks per requestor
323system.cpu.icache.occ_percent::cpu.inst 0.996893 # Average percentage of cache occupancy
324system.cpu.icache.occ_percent::total 0.996893 # Average percentage of cache occupancy
325system.cpu.icache.ReadReq_hits::cpu.inst 144555062 # number of ReadReq hits
326system.cpu.icache.ReadReq_hits::total 144555062 # number of ReadReq hits
327system.cpu.icache.demand_hits::cpu.inst 144555062 # number of demand (read+write) hits
328system.cpu.icache.demand_hits::total 144555062 # number of demand (read+write) hits
329system.cpu.icache.overall_hits::cpu.inst 144555062 # number of overall hits
330system.cpu.icache.overall_hits::total 144555062 # number of overall hits
331system.cpu.icache.ReadReq_misses::cpu.inst 791091 # number of ReadReq misses
332system.cpu.icache.ReadReq_misses::total 791091 # number of ReadReq misses
333system.cpu.icache.demand_misses::cpu.inst 791091 # number of demand (read+write) misses
334system.cpu.icache.demand_misses::total 791091 # number of demand (read+write) misses
335system.cpu.icache.overall_misses::cpu.inst 791091 # number of overall misses
336system.cpu.icache.overall_misses::total 791091 # number of overall misses
337system.cpu.icache.ReadReq_miss_latency::cpu.inst 10944017000 # number of ReadReq miss cycles
338system.cpu.icache.ReadReq_miss_latency::total 10944017000 # number of ReadReq miss cycles
339system.cpu.icache.demand_miss_latency::cpu.inst 10944017000 # number of demand (read+write) miss cycles
340system.cpu.icache.demand_miss_latency::total 10944017000 # number of demand (read+write) miss cycles
341system.cpu.icache.overall_miss_latency::cpu.inst 10944017000 # number of overall miss cycles
342system.cpu.icache.overall_miss_latency::total 10944017000 # number of overall miss cycles
343system.cpu.icache.ReadReq_accesses::cpu.inst 145346153 # number of ReadReq accesses(hits+misses)
344system.cpu.icache.ReadReq_accesses::total 145346153 # number of ReadReq accesses(hits+misses)
345system.cpu.icache.demand_accesses::cpu.inst 145346153 # number of demand (read+write) accesses
346system.cpu.icache.demand_accesses::total 145346153 # number of demand (read+write) accesses
347system.cpu.icache.overall_accesses::cpu.inst 145346153 # number of overall (read+write) accesses
348system.cpu.icache.overall_accesses::total 145346153 # number of overall (read+write) accesses
349system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses
350system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses
351system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses
352system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses
353system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses
354system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses
355system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.081035 # average ReadReq miss latency
356system.cpu.icache.ReadReq_avg_miss_latency::total 13834.081035 # average ReadReq miss latency
357system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.081035 # average overall miss latency
358system.cpu.icache.demand_avg_miss_latency::total 13834.081035 # average overall miss latency
359system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.081035 # average overall miss latency
360system.cpu.icache.overall_avg_miss_latency::total 13834.081035 # average overall miss latency
| 670system.cpu.icache.replacements 791404 # number of replacements
671system.cpu.icache.tagsinuse 510.366672 # Cycle average of tags in use
672system.cpu.icache.total_refs 144533937 # Total number of references to valid blocks.
673system.cpu.icache.sampled_refs 791916 # Sample count of references to valid blocks.
674system.cpu.icache.avg_refs 182.511702 # Average number of references to valid blocks.
675system.cpu.icache.warmup_cycle 161113577000 # Cycle when the warmup percentage was hit.
676system.cpu.icache.occ_blocks::cpu.inst 510.366672 # Average occupied blocks per requestor
677system.cpu.icache.occ_percent::cpu.inst 0.996810 # Average percentage of cache occupancy
678system.cpu.icache.occ_percent::total 0.996810 # Average percentage of cache occupancy
679system.cpu.icache.ReadReq_hits::cpu.inst 144533937 # number of ReadReq hits
680system.cpu.icache.ReadReq_hits::total 144533937 # number of ReadReq hits
681system.cpu.icache.demand_hits::cpu.inst 144533937 # number of demand (read+write) hits
682system.cpu.icache.demand_hits::total 144533937 # number of demand (read+write) hits
683system.cpu.icache.overall_hits::cpu.inst 144533937 # number of overall hits
684system.cpu.icache.overall_hits::total 144533937 # number of overall hits
685system.cpu.icache.ReadReq_misses::cpu.inst 791923 # number of ReadReq misses
686system.cpu.icache.ReadReq_misses::total 791923 # number of ReadReq misses
687system.cpu.icache.demand_misses::cpu.inst 791923 # number of demand (read+write) misses
688system.cpu.icache.demand_misses::total 791923 # number of demand (read+write) misses
689system.cpu.icache.overall_misses::cpu.inst 791923 # number of overall misses
690system.cpu.icache.overall_misses::total 791923 # number of overall misses
691system.cpu.icache.ReadReq_miss_latency::cpu.inst 11177158500 # number of ReadReq miss cycles
692system.cpu.icache.ReadReq_miss_latency::total 11177158500 # number of ReadReq miss cycles
693system.cpu.icache.demand_miss_latency::cpu.inst 11177158500 # number of demand (read+write) miss cycles
694system.cpu.icache.demand_miss_latency::total 11177158500 # number of demand (read+write) miss cycles
695system.cpu.icache.overall_miss_latency::cpu.inst 11177158500 # number of overall miss cycles
696system.cpu.icache.overall_miss_latency::total 11177158500 # number of overall miss cycles
697system.cpu.icache.ReadReq_accesses::cpu.inst 145325860 # number of ReadReq accesses(hits+misses)
698system.cpu.icache.ReadReq_accesses::total 145325860 # number of ReadReq accesses(hits+misses)
699system.cpu.icache.demand_accesses::cpu.inst 145325860 # number of demand (read+write) accesses
700system.cpu.icache.demand_accesses::total 145325860 # number of demand (read+write) accesses
701system.cpu.icache.overall_accesses::cpu.inst 145325860 # number of overall (read+write) accesses
702system.cpu.icache.overall_accesses::total 145325860 # number of overall (read+write) accesses
703system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses
704system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses
705system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses
706system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses
707system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses
708system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses
709system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14113.946053 # average ReadReq miss latency
710system.cpu.icache.ReadReq_avg_miss_latency::total 14113.946053 # average ReadReq miss latency
711system.cpu.icache.demand_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency
712system.cpu.icache.demand_avg_miss_latency::total 14113.946053 # average overall miss latency
713system.cpu.icache.overall_avg_miss_latency::cpu.inst 14113.946053 # average overall miss latency
714system.cpu.icache.overall_avg_miss_latency::total 14113.946053 # average overall miss latency
|
361system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
362system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
363system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
364system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
365system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
366system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
367system.cpu.icache.fast_writes 0 # number of fast writes performed
368system.cpu.icache.cache_copies 0 # number of cache copies performed
| 715system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
716system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
717system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
718system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
719system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
720system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
721system.cpu.icache.fast_writes 0 # number of fast writes performed
722system.cpu.icache.cache_copies 0 # number of cache copies performed
|
369system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791091 # number of ReadReq MSHR misses
370system.cpu.icache.ReadReq_mshr_misses::total 791091 # number of ReadReq MSHR misses
371system.cpu.icache.demand_mshr_misses::cpu.inst 791091 # number of demand (read+write) MSHR misses
372system.cpu.icache.demand_mshr_misses::total 791091 # number of demand (read+write) MSHR misses
373system.cpu.icache.overall_mshr_misses::cpu.inst 791091 # number of overall MSHR misses
374system.cpu.icache.overall_mshr_misses::total 791091 # number of overall MSHR misses
375system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9361835000 # number of ReadReq MSHR miss cycles
376system.cpu.icache.ReadReq_mshr_miss_latency::total 9361835000 # number of ReadReq MSHR miss cycles
377system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9361835000 # number of demand (read+write) MSHR miss cycles
378system.cpu.icache.demand_mshr_miss_latency::total 9361835000 # number of demand (read+write) MSHR miss cycles
379system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9361835000 # number of overall MSHR miss cycles
380system.cpu.icache.overall_mshr_miss_latency::total 9361835000 # number of overall MSHR miss cycles
381system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for ReadReq accesses
382system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005443 # mshr miss rate for ReadReq accesses
383system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for demand accesses
384system.cpu.icache.demand_mshr_miss_rate::total 0.005443 # mshr miss rate for demand accesses
385system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for overall accesses
386system.cpu.icache.overall_mshr_miss_rate::total 0.005443 # mshr miss rate for overall accesses
387system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.081035 # average ReadReq mshr miss latency
388system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.081035 # average ReadReq mshr miss latency
389system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.081035 # average overall mshr miss latency
390system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.081035 # average overall mshr miss latency
391system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.081035 # average overall mshr miss latency
392system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.081035 # average overall mshr miss latency
| 723system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791923 # number of ReadReq MSHR misses
724system.cpu.icache.ReadReq_mshr_misses::total 791923 # number of ReadReq MSHR misses
725system.cpu.icache.demand_mshr_misses::cpu.inst 791923 # number of demand (read+write) MSHR misses
726system.cpu.icache.demand_mshr_misses::total 791923 # number of demand (read+write) MSHR misses
727system.cpu.icache.overall_mshr_misses::cpu.inst 791923 # number of overall MSHR misses
728system.cpu.icache.overall_mshr_misses::total 791923 # number of overall MSHR misses
729system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9593312500 # number of ReadReq MSHR miss cycles
730system.cpu.icache.ReadReq_mshr_miss_latency::total 9593312500 # number of ReadReq MSHR miss cycles
731system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9593312500 # number of demand (read+write) MSHR miss cycles
732system.cpu.icache.demand_mshr_miss_latency::total 9593312500 # number of demand (read+write) MSHR miss cycles
733system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9593312500 # number of overall MSHR miss cycles
734system.cpu.icache.overall_mshr_miss_latency::total 9593312500 # number of overall MSHR miss cycles
735system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for ReadReq accesses
736system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005449 # mshr miss rate for ReadReq accesses
737system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for demand accesses
738system.cpu.icache.demand_mshr_miss_rate::total 0.005449 # mshr miss rate for demand accesses
739system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005449 # mshr miss rate for overall accesses
740system.cpu.icache.overall_mshr_miss_rate::total 0.005449 # mshr miss rate for overall accesses
741system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12113.946053 # average ReadReq mshr miss latency
742system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12113.946053 # average ReadReq mshr miss latency
743system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency
744system.cpu.icache.demand_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency
745system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12113.946053 # average overall mshr miss latency
746system.cpu.icache.overall_avg_mshr_miss_latency::total 12113.946053 # average overall mshr miss latency
|
393system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 747system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
394system.cpu.itb_walker_cache.replacements 3538 # number of replacements
395system.cpu.itb_walker_cache.tagsinuse 3.071073 # Cycle average of tags in use
396system.cpu.itb_walker_cache.total_refs 7817 # Total number of references to valid blocks.
397system.cpu.itb_walker_cache.sampled_refs 3549 # Sample count of references to valid blocks.
398system.cpu.itb_walker_cache.avg_refs 2.202592 # Average number of references to valid blocks.
399system.cpu.itb_walker_cache.warmup_cycle 5161021529000 # Cycle when the warmup percentage was hit.
400system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.071073 # Average occupied blocks per requestor
401system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191942 # Average percentage of cache occupancy
402system.cpu.itb_walker_cache.occ_percent::total 0.191942 # Average percentage of cache occupancy
403system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7819 # number of ReadReq hits
404system.cpu.itb_walker_cache.ReadReq_hits::total 7819 # number of ReadReq hits
| 748system.cpu.itb_walker_cache.replacements 3530 # number of replacements
749system.cpu.itb_walker_cache.tagsinuse 3.075423 # Cycle average of tags in use
750system.cpu.itb_walker_cache.total_refs 7811 # Total number of references to valid blocks.
751system.cpu.itb_walker_cache.sampled_refs 3541 # Sample count of references to valid blocks.
752system.cpu.itb_walker_cache.avg_refs 2.205874 # Average number of references to valid blocks.
753system.cpu.itb_walker_cache.warmup_cycle 5166918586000 # Cycle when the warmup percentage was hit.
754system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.075423 # Average occupied blocks per requestor
755system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192214 # Average percentage of cache occupancy
756system.cpu.itb_walker_cache.occ_percent::total 0.192214 # Average percentage of cache occupancy
757system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7833 # number of ReadReq hits
758system.cpu.itb_walker_cache.ReadReq_hits::total 7833 # number of ReadReq hits
|
405system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
406system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
| 759system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
760system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
407system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7821 # number of demand (read+write) hits
408system.cpu.itb_walker_cache.demand_hits::total 7821 # number of demand (read+write) hits
409system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7821 # number of overall hits
410system.cpu.itb_walker_cache.overall_hits::total 7821 # number of overall hits
411system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4399 # number of ReadReq misses
412system.cpu.itb_walker_cache.ReadReq_misses::total 4399 # number of ReadReq misses
413system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4399 # number of demand (read+write) misses
414system.cpu.itb_walker_cache.demand_misses::total 4399 # number of demand (read+write) misses
415system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4399 # number of overall misses
416system.cpu.itb_walker_cache.overall_misses::total 4399 # number of overall misses
417system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43289000 # number of ReadReq miss cycles
418system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43289000 # number of ReadReq miss cycles
419system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43289000 # number of demand (read+write) miss cycles
420system.cpu.itb_walker_cache.demand_miss_latency::total 43289000 # number of demand (read+write) miss cycles
421system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43289000 # number of overall miss cycles
422system.cpu.itb_walker_cache.overall_miss_latency::total 43289000 # number of overall miss cycles
423system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12218 # number of ReadReq accesses(hits+misses)
424system.cpu.itb_walker_cache.ReadReq_accesses::total 12218 # number of ReadReq accesses(hits+misses)
| 761system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7835 # number of demand (read+write) hits
762system.cpu.itb_walker_cache.demand_hits::total 7835 # number of demand (read+write) hits
763system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7835 # number of overall hits
764system.cpu.itb_walker_cache.overall_hits::total 7835 # number of overall hits
765system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4388 # number of ReadReq misses
766system.cpu.itb_walker_cache.ReadReq_misses::total 4388 # number of ReadReq misses
767system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4388 # number of demand (read+write) misses
768system.cpu.itb_walker_cache.demand_misses::total 4388 # number of demand (read+write) misses
769system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4388 # number of overall misses
770system.cpu.itb_walker_cache.overall_misses::total 4388 # number of overall misses
771system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43163000 # number of ReadReq miss cycles
772system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43163000 # number of ReadReq miss cycles
773system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43163000 # number of demand (read+write) miss cycles
774system.cpu.itb_walker_cache.demand_miss_latency::total 43163000 # number of demand (read+write) miss cycles
775system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43163000 # number of overall miss cycles
776system.cpu.itb_walker_cache.overall_miss_latency::total 43163000 # number of overall miss cycles
777system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses)
778system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses)
|
425system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
426system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
| 779system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
780system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
427system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12220 # number of demand (read+write) accesses
428system.cpu.itb_walker_cache.demand_accesses::total 12220 # number of demand (read+write) accesses
429system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12220 # number of overall (read+write) accesses
430system.cpu.itb_walker_cache.overall_accesses::total 12220 # number of overall (read+write) accesses
431system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.360043 # miss rate for ReadReq accesses
432system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.360043 # miss rate for ReadReq accesses
433system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.359984 # miss rate for demand accesses
434system.cpu.itb_walker_cache.demand_miss_rate::total 0.359984 # miss rate for demand accesses
435system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.359984 # miss rate for overall accesses
436system.cpu.itb_walker_cache.overall_miss_rate::total 0.359984 # miss rate for overall accesses
437system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9840.645601 # average ReadReq miss latency
438system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9840.645601 # average ReadReq miss latency
439system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9840.645601 # average overall miss latency
440system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9840.645601 # average overall miss latency
441system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9840.645601 # average overall miss latency
442system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9840.645601 # average overall miss latency
| 781system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses
782system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses
783system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses
784system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses
785system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.359054 # miss rate for ReadReq accesses
786system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.359054 # miss rate for ReadReq accesses
787system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358995 # miss rate for demand accesses
788system.cpu.itb_walker_cache.demand_miss_rate::total 0.358995 # miss rate for demand accesses
789system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358995 # miss rate for overall accesses
790system.cpu.itb_walker_cache.overall_miss_rate::total 0.358995 # miss rate for overall accesses
791system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9836.599818 # average ReadReq miss latency
792system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9836.599818 # average ReadReq miss latency
793system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency
794system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9836.599818 # average overall miss latency
795system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9836.599818 # average overall miss latency
796system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9836.599818 # average overall miss latency
|
443system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
444system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
445system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
446system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
447system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
448system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
449system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
450system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
| 797system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
798system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
799system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
800system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
801system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
802system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
803system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
804system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
451system.cpu.itb_walker_cache.writebacks::writebacks 650 # number of writebacks
452system.cpu.itb_walker_cache.writebacks::total 650 # number of writebacks
453system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4399 # number of ReadReq MSHR misses
454system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4399 # number of ReadReq MSHR misses
455system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4399 # number of demand (read+write) MSHR misses
456system.cpu.itb_walker_cache.demand_mshr_misses::total 4399 # number of demand (read+write) MSHR misses
457system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4399 # number of overall MSHR misses
458system.cpu.itb_walker_cache.overall_mshr_misses::total 4399 # number of overall MSHR misses
459system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34491000 # number of ReadReq MSHR miss cycles
460system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34491000 # number of ReadReq MSHR miss cycles
461system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34491000 # number of demand (read+write) MSHR miss cycles
462system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34491000 # number of demand (read+write) MSHR miss cycles
463system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34491000 # number of overall MSHR miss cycles
464system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34491000 # number of overall MSHR miss cycles
465system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.360043 # mshr miss rate for ReadReq accesses
466system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.360043 # mshr miss rate for ReadReq accesses
467system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.359984 # mshr miss rate for demand accesses
468system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.359984 # mshr miss rate for demand accesses
469system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.359984 # mshr miss rate for overall accesses
470system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.359984 # mshr miss rate for overall accesses
471system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average ReadReq mshr miss latency
472system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7840.645601 # average ReadReq mshr miss latency
473system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average overall mshr miss latency
474system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7840.645601 # average overall mshr miss latency
475system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7840.645601 # average overall mshr miss latency
476system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7840.645601 # average overall mshr miss latency
| 805system.cpu.itb_walker_cache.writebacks::writebacks 619 # number of writebacks
806system.cpu.itb_walker_cache.writebacks::total 619 # number of writebacks
807system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4388 # number of ReadReq MSHR misses
808system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4388 # number of ReadReq MSHR misses
809system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4388 # number of demand (read+write) MSHR misses
810system.cpu.itb_walker_cache.demand_mshr_misses::total 4388 # number of demand (read+write) MSHR misses
811system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4388 # number of overall MSHR misses
812system.cpu.itb_walker_cache.overall_mshr_misses::total 4388 # number of overall MSHR misses
813system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34387000 # number of ReadReq MSHR miss cycles
814system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34387000 # number of ReadReq MSHR miss cycles
815system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34387000 # number of demand (read+write) MSHR miss cycles
816system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34387000 # number of demand (read+write) MSHR miss cycles
817system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34387000 # number of overall MSHR miss cycles
818system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34387000 # number of overall MSHR miss cycles
819system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.359054 # mshr miss rate for ReadReq accesses
820system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.359054 # mshr miss rate for ReadReq accesses
821system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for demand accesses
822system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358995 # mshr miss rate for demand accesses
823system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358995 # mshr miss rate for overall accesses
824system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358995 # mshr miss rate for overall accesses
825system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average ReadReq mshr miss latency
826system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7836.599818 # average ReadReq mshr miss latency
827system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency
828system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency
829system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7836.599818 # average overall mshr miss latency
830system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7836.599818 # average overall mshr miss latency
|
477system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 831system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
478system.cpu.dtb_walker_cache.replacements 7602 # number of replacements
479system.cpu.dtb_walker_cache.tagsinuse 5.053533 # Cycle average of tags in use
480system.cpu.dtb_walker_cache.total_refs 13277 # Total number of references to valid blocks.
481system.cpu.dtb_walker_cache.sampled_refs 7616 # Sample count of references to valid blocks.
482system.cpu.dtb_walker_cache.avg_refs 1.743304 # Average number of references to valid blocks.
483system.cpu.dtb_walker_cache.warmup_cycle 5155312372000 # Cycle when the warmup percentage was hit.
484system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053533 # Average occupied blocks per requestor
485system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315846 # Average percentage of cache occupancy
486system.cpu.dtb_walker_cache.occ_percent::total 0.315846 # Average percentage of cache occupancy
487system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13278 # number of ReadReq hits
488system.cpu.dtb_walker_cache.ReadReq_hits::total 13278 # number of ReadReq hits
489system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13278 # number of demand (read+write) hits
490system.cpu.dtb_walker_cache.demand_hits::total 13278 # number of demand (read+write) hits
491system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13278 # number of overall hits
492system.cpu.dtb_walker_cache.overall_hits::total 13278 # number of overall hits
493system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8808 # number of ReadReq misses
494system.cpu.dtb_walker_cache.ReadReq_misses::total 8808 # number of ReadReq misses
495system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8808 # number of demand (read+write) misses
496system.cpu.dtb_walker_cache.demand_misses::total 8808 # number of demand (read+write) misses
497system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8808 # number of overall misses
498system.cpu.dtb_walker_cache.overall_misses::total 8808 # number of overall misses
499system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 93210000 # number of ReadReq miss cycles
500system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 93210000 # number of ReadReq miss cycles
501system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 93210000 # number of demand (read+write) miss cycles
502system.cpu.dtb_walker_cache.demand_miss_latency::total 93210000 # number of demand (read+write) miss cycles
503system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 93210000 # number of overall miss cycles
504system.cpu.dtb_walker_cache.overall_miss_latency::total 93210000 # number of overall miss cycles
505system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22086 # number of ReadReq accesses(hits+misses)
506system.cpu.dtb_walker_cache.ReadReq_accesses::total 22086 # number of ReadReq accesses(hits+misses)
507system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22086 # number of demand (read+write) accesses
508system.cpu.dtb_walker_cache.demand_accesses::total 22086 # number of demand (read+write) accesses
509system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22086 # number of overall (read+write) accesses
510system.cpu.dtb_walker_cache.overall_accesses::total 22086 # number of overall (read+write) accesses
511system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398805 # miss rate for ReadReq accesses
512system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398805 # miss rate for ReadReq accesses
513system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398805 # miss rate for demand accesses
514system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398805 # miss rate for demand accesses
515system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398805 # miss rate for overall accesses
516system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398805 # miss rate for overall accesses
517system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10582.425068 # average ReadReq miss latency
518system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10582.425068 # average ReadReq miss latency
519system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10582.425068 # average overall miss latency
520system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10582.425068 # average overall miss latency
521system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10582.425068 # average overall miss latency
522system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10582.425068 # average overall miss latency
| 832system.cpu.dtb_walker_cache.replacements 7412 # number of replacements
833system.cpu.dtb_walker_cache.tagsinuse 5.056524 # Cycle average of tags in use
834system.cpu.dtb_walker_cache.total_refs 13351 # Total number of references to valid blocks.
835system.cpu.dtb_walker_cache.sampled_refs 7427 # Sample count of references to valid blocks.
836system.cpu.dtb_walker_cache.avg_refs 1.797630 # Average number of references to valid blocks.
837system.cpu.dtb_walker_cache.warmup_cycle 5162997491000 # Cycle when the warmup percentage was hit.
838system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.056524 # Average occupied blocks per requestor
839system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316033 # Average percentage of cache occupancy
840system.cpu.dtb_walker_cache.occ_percent::total 0.316033 # Average percentage of cache occupancy
841system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13351 # number of ReadReq hits
842system.cpu.dtb_walker_cache.ReadReq_hits::total 13351 # number of ReadReq hits
843system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13351 # number of demand (read+write) hits
844system.cpu.dtb_walker_cache.demand_hits::total 13351 # number of demand (read+write) hits
845system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13351 # number of overall hits
846system.cpu.dtb_walker_cache.overall_hits::total 13351 # number of overall hits
847system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8618 # number of ReadReq misses
848system.cpu.dtb_walker_cache.ReadReq_misses::total 8618 # number of ReadReq misses
849system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8618 # number of demand (read+write) misses
850system.cpu.dtb_walker_cache.demand_misses::total 8618 # number of demand (read+write) misses
851system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8618 # number of overall misses
852system.cpu.dtb_walker_cache.overall_misses::total 8618 # number of overall misses
853system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 90576000 # number of ReadReq miss cycles
854system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 90576000 # number of ReadReq miss cycles
855system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 90576000 # number of demand (read+write) miss cycles
856system.cpu.dtb_walker_cache.demand_miss_latency::total 90576000 # number of demand (read+write) miss cycles
857system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 90576000 # number of overall miss cycles
858system.cpu.dtb_walker_cache.overall_miss_latency::total 90576000 # number of overall miss cycles
859system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21969 # number of ReadReq accesses(hits+misses)
860system.cpu.dtb_walker_cache.ReadReq_accesses::total 21969 # number of ReadReq accesses(hits+misses)
861system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21969 # number of demand (read+write) accesses
862system.cpu.dtb_walker_cache.demand_accesses::total 21969 # number of demand (read+write) accesses
863system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21969 # number of overall (read+write) accesses
864system.cpu.dtb_walker_cache.overall_accesses::total 21969 # number of overall (read+write) accesses
865system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392280 # miss rate for ReadReq accesses
866system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392280 # miss rate for ReadReq accesses
867system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392280 # miss rate for demand accesses
868system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392280 # miss rate for demand accesses
869system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392280 # miss rate for overall accesses
870system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392280 # miss rate for overall accesses
871system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10510.095150 # average ReadReq miss latency
872system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10510.095150 # average ReadReq miss latency
873system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency
874system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10510.095150 # average overall miss latency
875system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10510.095150 # average overall miss latency
876system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10510.095150 # average overall miss latency
|
523system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
524system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
525system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
526system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
527system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
528system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
529system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
530system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
| 877system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
878system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
879system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
880system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
881system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
882system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
883system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
884system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
531system.cpu.dtb_walker_cache.writebacks::writebacks 2984 # number of writebacks
532system.cpu.dtb_walker_cache.writebacks::total 2984 # number of writebacks
533system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8808 # number of ReadReq MSHR misses
534system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8808 # number of ReadReq MSHR misses
535system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8808 # number of demand (read+write) MSHR misses
536system.cpu.dtb_walker_cache.demand_mshr_misses::total 8808 # number of demand (read+write) MSHR misses
537system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8808 # number of overall MSHR misses
538system.cpu.dtb_walker_cache.overall_mshr_misses::total 8808 # number of overall MSHR misses
539system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 75594000 # number of ReadReq MSHR miss cycles
540system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 75594000 # number of ReadReq MSHR miss cycles
541system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 75594000 # number of demand (read+write) MSHR miss cycles
542system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 75594000 # number of demand (read+write) MSHR miss cycles
543system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 75594000 # number of overall MSHR miss cycles
544system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 75594000 # number of overall MSHR miss cycles
545system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for ReadReq accesses
546system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398805 # mshr miss rate for ReadReq accesses
547system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for demand accesses
548system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398805 # mshr miss rate for demand accesses
549system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398805 # mshr miss rate for overall accesses
550system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398805 # mshr miss rate for overall accesses
551system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average ReadReq mshr miss latency
552system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8582.425068 # average ReadReq mshr miss latency
553system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average overall mshr miss latency
554system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8582.425068 # average overall mshr miss latency
555system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8582.425068 # average overall mshr miss latency
556system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8582.425068 # average overall mshr miss latency
| 885system.cpu.dtb_walker_cache.writebacks::writebacks 2749 # number of writebacks
886system.cpu.dtb_walker_cache.writebacks::total 2749 # number of writebacks
887system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8618 # number of ReadReq MSHR misses
888system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8618 # number of ReadReq MSHR misses
889system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8618 # number of demand (read+write) MSHR misses
890system.cpu.dtb_walker_cache.demand_mshr_misses::total 8618 # number of demand (read+write) MSHR misses
891system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8618 # number of overall MSHR misses
892system.cpu.dtb_walker_cache.overall_mshr_misses::total 8618 # number of overall MSHR misses
893system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 73340000 # number of ReadReq MSHR miss cycles
894system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 73340000 # number of ReadReq MSHR miss cycles
895system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 73340000 # number of demand (read+write) MSHR miss cycles
896system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 73340000 # number of demand (read+write) MSHR miss cycles
897system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 73340000 # number of overall MSHR miss cycles
898system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 73340000 # number of overall MSHR miss cycles
899system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for ReadReq accesses
900system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392280 # mshr miss rate for ReadReq accesses
901system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for demand accesses
902system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392280 # mshr miss rate for demand accesses
903system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392280 # mshr miss rate for overall accesses
904system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392280 # mshr miss rate for overall accesses
905system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average ReadReq mshr miss latency
906system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8510.095150 # average ReadReq mshr miss latency
907system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency
908system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency
909system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8510.095150 # average overall mshr miss latency
910system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8510.095150 # average overall mshr miss latency
|
557system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 911system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
558system.cpu.dcache.replacements 1620743 # number of replacements
559system.cpu.dcache.tagsinuse 511.997667 # Cycle average of tags in use
560system.cpu.dcache.total_refs 20031616 # Total number of references to valid blocks.
561system.cpu.dcache.sampled_refs 1621255 # Sample count of references to valid blocks.
562system.cpu.dcache.avg_refs 12.355623 # Average number of references to valid blocks.
563system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit.
564system.cpu.dcache.occ_blocks::cpu.data 511.997667 # Average occupied blocks per requestor
565system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
566system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
567system.cpu.dcache.ReadReq_hits::cpu.data 11991279 # number of ReadReq hits
568system.cpu.dcache.ReadReq_hits::total 11991279 # number of ReadReq hits
569system.cpu.dcache.WriteReq_hits::cpu.data 8038109 # number of WriteReq hits
570system.cpu.dcache.WriteReq_hits::total 8038109 # number of WriteReq hits
571system.cpu.dcache.demand_hits::cpu.data 20029388 # number of demand (read+write) hits
572system.cpu.dcache.demand_hits::total 20029388 # number of demand (read+write) hits
573system.cpu.dcache.overall_hits::cpu.data 20029388 # number of overall hits
574system.cpu.dcache.overall_hits::total 20029388 # number of overall hits
575system.cpu.dcache.ReadReq_misses::cpu.data 1307954 # number of ReadReq misses
576system.cpu.dcache.ReadReq_misses::total 1307954 # number of ReadReq misses
577system.cpu.dcache.WriteReq_misses::cpu.data 315546 # number of WriteReq misses
578system.cpu.dcache.WriteReq_misses::total 315546 # number of WriteReq misses
579system.cpu.dcache.demand_misses::cpu.data 1623500 # number of demand (read+write) misses
580system.cpu.dcache.demand_misses::total 1623500 # number of demand (read+write) misses
581system.cpu.dcache.overall_misses::cpu.data 1623500 # number of overall misses
582system.cpu.dcache.overall_misses::total 1623500 # number of overall misses
583system.cpu.dcache.ReadReq_miss_latency::cpu.data 18389416000 # number of ReadReq miss cycles
584system.cpu.dcache.ReadReq_miss_latency::total 18389416000 # number of ReadReq miss cycles
585system.cpu.dcache.WriteReq_miss_latency::cpu.data 8586143000 # number of WriteReq miss cycles
586system.cpu.dcache.WriteReq_miss_latency::total 8586143000 # number of WriteReq miss cycles
587system.cpu.dcache.demand_miss_latency::cpu.data 26975559000 # number of demand (read+write) miss cycles
588system.cpu.dcache.demand_miss_latency::total 26975559000 # number of demand (read+write) miss cycles
589system.cpu.dcache.overall_miss_latency::cpu.data 26975559000 # number of overall miss cycles
590system.cpu.dcache.overall_miss_latency::total 26975559000 # number of overall miss cycles
591system.cpu.dcache.ReadReq_accesses::cpu.data 13299233 # number of ReadReq accesses(hits+misses)
592system.cpu.dcache.ReadReq_accesses::total 13299233 # number of ReadReq accesses(hits+misses)
593system.cpu.dcache.WriteReq_accesses::cpu.data 8353655 # number of WriteReq accesses(hits+misses)
594system.cpu.dcache.WriteReq_accesses::total 8353655 # number of WriteReq accesses(hits+misses)
595system.cpu.dcache.demand_accesses::cpu.data 21652888 # number of demand (read+write) accesses
596system.cpu.dcache.demand_accesses::total 21652888 # number of demand (read+write) accesses
597system.cpu.dcache.overall_accesses::cpu.data 21652888 # number of overall (read+write) accesses
598system.cpu.dcache.overall_accesses::total 21652888 # number of overall (read+write) accesses
599system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098348 # miss rate for ReadReq accesses
600system.cpu.dcache.ReadReq_miss_rate::total 0.098348 # miss rate for ReadReq accesses
601system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037773 # miss rate for WriteReq accesses
602system.cpu.dcache.WriteReq_miss_rate::total 0.037773 # miss rate for WriteReq accesses
603system.cpu.dcache.demand_miss_rate::cpu.data 0.074978 # miss rate for demand accesses
604system.cpu.dcache.demand_miss_rate::total 0.074978 # miss rate for demand accesses
605system.cpu.dcache.overall_miss_rate::cpu.data 0.074978 # miss rate for overall accesses
606system.cpu.dcache.overall_miss_rate::total 0.074978 # miss rate for overall accesses
607system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14059.680998 # average ReadReq miss latency
608system.cpu.dcache.ReadReq_avg_miss_latency::total 14059.680998 # average ReadReq miss latency
609system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27210.432076 # average WriteReq miss latency
610system.cpu.dcache.WriteReq_avg_miss_latency::total 27210.432076 # average WriteReq miss latency
611system.cpu.dcache.demand_avg_miss_latency::cpu.data 16615.681552 # average overall miss latency
612system.cpu.dcache.demand_avg_miss_latency::total 16615.681552 # average overall miss latency
613system.cpu.dcache.overall_avg_miss_latency::cpu.data 16615.681552 # average overall miss latency
614system.cpu.dcache.overall_avg_miss_latency::total 16615.681552 # average overall miss latency
| 912system.cpu.dcache.replacements 1622441 # number of replacements
913system.cpu.dcache.tagsinuse 511.992388 # Cycle average of tags in use
914system.cpu.dcache.total_refs 20034872 # Total number of references to valid blocks.
915system.cpu.dcache.sampled_refs 1622953 # Sample count of references to valid blocks.
916system.cpu.dcache.avg_refs 12.344703 # Average number of references to valid blocks.
917system.cpu.dcache.warmup_cycle 48929000 # Cycle when the warmup percentage was hit.
918system.cpu.dcache.occ_blocks::cpu.data 511.992388 # Average occupied blocks per requestor
919system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy
920system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy
921system.cpu.dcache.ReadReq_hits::cpu.data 11992680 # number of ReadReq hits
922system.cpu.dcache.ReadReq_hits::total 11992680 # number of ReadReq hits
923system.cpu.dcache.WriteReq_hits::cpu.data 8039994 # number of WriteReq hits
924system.cpu.dcache.WriteReq_hits::total 8039994 # number of WriteReq hits
925system.cpu.dcache.demand_hits::cpu.data 20032674 # number of demand (read+write) hits
926system.cpu.dcache.demand_hits::total 20032674 # number of demand (read+write) hits
927system.cpu.dcache.overall_hits::cpu.data 20032674 # number of overall hits
928system.cpu.dcache.overall_hits::total 20032674 # number of overall hits
929system.cpu.dcache.ReadReq_misses::cpu.data 1308966 # number of ReadReq misses
930system.cpu.dcache.ReadReq_misses::total 1308966 # number of ReadReq misses
931system.cpu.dcache.WriteReq_misses::cpu.data 316237 # number of WriteReq misses
932system.cpu.dcache.WriteReq_misses::total 316237 # number of WriteReq misses
933system.cpu.dcache.demand_misses::cpu.data 1625203 # number of demand (read+write) misses
934system.cpu.dcache.demand_misses::total 1625203 # number of demand (read+write) misses
935system.cpu.dcache.overall_misses::cpu.data 1625203 # number of overall misses
936system.cpu.dcache.overall_misses::total 1625203 # number of overall misses
937system.cpu.dcache.ReadReq_miss_latency::cpu.data 18848048000 # number of ReadReq miss cycles
938system.cpu.dcache.ReadReq_miss_latency::total 18848048000 # number of ReadReq miss cycles
939system.cpu.dcache.WriteReq_miss_latency::cpu.data 10644655000 # number of WriteReq miss cycles
940system.cpu.dcache.WriteReq_miss_latency::total 10644655000 # number of WriteReq miss cycles
941system.cpu.dcache.demand_miss_latency::cpu.data 29492703000 # number of demand (read+write) miss cycles
942system.cpu.dcache.demand_miss_latency::total 29492703000 # number of demand (read+write) miss cycles
943system.cpu.dcache.overall_miss_latency::cpu.data 29492703000 # number of overall miss cycles
944system.cpu.dcache.overall_miss_latency::total 29492703000 # number of overall miss cycles
945system.cpu.dcache.ReadReq_accesses::cpu.data 13301646 # number of ReadReq accesses(hits+misses)
946system.cpu.dcache.ReadReq_accesses::total 13301646 # number of ReadReq accesses(hits+misses)
947system.cpu.dcache.WriteReq_accesses::cpu.data 8356231 # number of WriteReq accesses(hits+misses)
948system.cpu.dcache.WriteReq_accesses::total 8356231 # number of WriteReq accesses(hits+misses)
949system.cpu.dcache.demand_accesses::cpu.data 21657877 # number of demand (read+write) accesses
950system.cpu.dcache.demand_accesses::total 21657877 # number of demand (read+write) accesses
951system.cpu.dcache.overall_accesses::cpu.data 21657877 # number of overall (read+write) accesses
952system.cpu.dcache.overall_accesses::total 21657877 # number of overall (read+write) accesses
953system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098406 # miss rate for ReadReq accesses
954system.cpu.dcache.ReadReq_miss_rate::total 0.098406 # miss rate for ReadReq accesses
955system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037844 # miss rate for WriteReq accesses
956system.cpu.dcache.WriteReq_miss_rate::total 0.037844 # miss rate for WriteReq accesses
957system.cpu.dcache.demand_miss_rate::cpu.data 0.075040 # miss rate for demand accesses
958system.cpu.dcache.demand_miss_rate::total 0.075040 # miss rate for demand accesses
959system.cpu.dcache.overall_miss_rate::cpu.data 0.075040 # miss rate for overall accesses
960system.cpu.dcache.overall_miss_rate::total 0.075040 # miss rate for overall accesses
961system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.188367 # average ReadReq miss latency
962system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.188367 # average ReadReq miss latency
963system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33660.371810 # average WriteReq miss latency
964system.cpu.dcache.WriteReq_avg_miss_latency::total 33660.371810 # average WriteReq miss latency
965system.cpu.dcache.demand_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency
966system.cpu.dcache.demand_avg_miss_latency::total 18147.088702 # average overall miss latency
967system.cpu.dcache.overall_avg_miss_latency::cpu.data 18147.088702 # average overall miss latency
968system.cpu.dcache.overall_avg_miss_latency::total 18147.088702 # average overall miss latency
|
615system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
616system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
617system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
618system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
619system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
620system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
621system.cpu.dcache.fast_writes 0 # number of fast writes performed
622system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 969system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
970system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
971system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
972system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
973system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
974system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
975system.cpu.dcache.fast_writes 0 # number of fast writes performed
976system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
623system.cpu.dcache.writebacks::writebacks 1538215 # number of writebacks
624system.cpu.dcache.writebacks::total 1538215 # number of writebacks
625system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1307954 # number of ReadReq MSHR misses
626system.cpu.dcache.ReadReq_mshr_misses::total 1307954 # number of ReadReq MSHR misses
627system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315546 # number of WriteReq MSHR misses
628system.cpu.dcache.WriteReq_mshr_misses::total 315546 # number of WriteReq MSHR misses
629system.cpu.dcache.demand_mshr_misses::cpu.data 1623500 # number of demand (read+write) MSHR misses
630system.cpu.dcache.demand_mshr_misses::total 1623500 # number of demand (read+write) MSHR misses
631system.cpu.dcache.overall_mshr_misses::cpu.data 1623500 # number of overall MSHR misses
632system.cpu.dcache.overall_mshr_misses::total 1623500 # number of overall MSHR misses
633system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15773508000 # number of ReadReq MSHR miss cycles
634system.cpu.dcache.ReadReq_mshr_miss_latency::total 15773508000 # number of ReadReq MSHR miss cycles
635system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7955051000 # number of WriteReq MSHR miss cycles
636system.cpu.dcache.WriteReq_mshr_miss_latency::total 7955051000 # number of WriteReq MSHR miss cycles
637system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23728559000 # number of demand (read+write) MSHR miss cycles
638system.cpu.dcache.demand_mshr_miss_latency::total 23728559000 # number of demand (read+write) MSHR miss cycles
639system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23728559000 # number of overall MSHR miss cycles
640system.cpu.dcache.overall_mshr_miss_latency::total 23728559000 # number of overall MSHR miss cycles
641system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200596500 # number of ReadReq MSHR uncacheable cycles
642system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200596500 # number of ReadReq MSHR uncacheable cycles
643system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2522793500 # number of WriteReq MSHR uncacheable cycles
644system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2522793500 # number of WriteReq MSHR uncacheable cycles
645system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723390000 # number of overall MSHR uncacheable cycles
646system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723390000 # number of overall MSHR uncacheable cycles
647system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098348 # mshr miss rate for ReadReq accesses
648system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098348 # mshr miss rate for ReadReq accesses
649system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037773 # mshr miss rate for WriteReq accesses
650system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037773 # mshr miss rate for WriteReq accesses
651system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074978 # mshr miss rate for demand accesses
652system.cpu.dcache.demand_mshr_miss_rate::total 0.074978 # mshr miss rate for demand accesses
653system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074978 # mshr miss rate for overall accesses
654system.cpu.dcache.overall_mshr_miss_rate::total 0.074978 # mshr miss rate for overall accesses
655system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12059.680998 # average ReadReq mshr miss latency
656system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12059.680998 # average ReadReq mshr miss latency
657system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25210.432076 # average WriteReq mshr miss latency
658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25210.432076 # average WriteReq mshr miss latency
659system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14615.681552 # average overall mshr miss latency
660system.cpu.dcache.demand_avg_mshr_miss_latency::total 14615.681552 # average overall mshr miss latency
661system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14615.681552 # average overall mshr miss latency
662system.cpu.dcache.overall_avg_mshr_miss_latency::total 14615.681552 # average overall mshr miss latency
| 977system.cpu.dcache.writebacks::writebacks 1539801 # number of writebacks
978system.cpu.dcache.writebacks::total 1539801 # number of writebacks
979system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308966 # number of ReadReq MSHR misses
980system.cpu.dcache.ReadReq_mshr_misses::total 1308966 # number of ReadReq MSHR misses
981system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316237 # number of WriteReq MSHR misses
982system.cpu.dcache.WriteReq_mshr_misses::total 316237 # number of WriteReq MSHR misses
983system.cpu.dcache.demand_mshr_misses::cpu.data 1625203 # number of demand (read+write) MSHR misses
984system.cpu.dcache.demand_mshr_misses::total 1625203 # number of demand (read+write) MSHR misses
985system.cpu.dcache.overall_mshr_misses::cpu.data 1625203 # number of overall MSHR misses
986system.cpu.dcache.overall_mshr_misses::total 1625203 # number of overall MSHR misses
987system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16230116000 # number of ReadReq MSHR miss cycles
988system.cpu.dcache.ReadReq_mshr_miss_latency::total 16230116000 # number of ReadReq MSHR miss cycles
989system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10012181000 # number of WriteReq MSHR miss cycles
990system.cpu.dcache.WriteReq_mshr_miss_latency::total 10012181000 # number of WriteReq MSHR miss cycles
991system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26242297000 # number of demand (read+write) MSHR miss cycles
992system.cpu.dcache.demand_mshr_miss_latency::total 26242297000 # number of demand (read+write) MSHR miss cycles
993system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26242297000 # number of overall MSHR miss cycles
994system.cpu.dcache.overall_mshr_miss_latency::total 26242297000 # number of overall MSHR miss cycles
995system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94201595500 # number of ReadReq MSHR uncacheable cycles
996system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94201595500 # number of ReadReq MSHR uncacheable cycles
997system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2525692000 # number of WriteReq MSHR uncacheable cycles
998system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2525692000 # number of WriteReq MSHR uncacheable cycles
999system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96727287500 # number of overall MSHR uncacheable cycles
1000system.cpu.dcache.overall_mshr_uncacheable_latency::total 96727287500 # number of overall MSHR uncacheable cycles
1001system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098406 # mshr miss rate for ReadReq accesses
1002system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098406 # mshr miss rate for ReadReq accesses
1003system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037844 # mshr miss rate for WriteReq accesses
1004system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037844 # mshr miss rate for WriteReq accesses
1005system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for demand accesses
1006system.cpu.dcache.demand_mshr_miss_rate::total 0.075040 # mshr miss rate for demand accesses
1007system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075040 # mshr miss rate for overall accesses
1008system.cpu.dcache.overall_mshr_miss_rate::total 0.075040 # mshr miss rate for overall accesses
1009system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12399.188367 # average ReadReq mshr miss latency
1010system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12399.188367 # average ReadReq mshr miss latency
1011system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31660.371810 # average WriteReq mshr miss latency
1012system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31660.371810 # average WriteReq mshr miss latency
1013system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency
1014system.cpu.dcache.demand_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency
1015system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16147.088702 # average overall mshr miss latency
1016system.cpu.dcache.overall_avg_mshr_miss_latency::total 16147.088702 # average overall mshr miss latency
|
663system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
664system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
665system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
666system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
667system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
668system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
669system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 1017system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1018system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1019system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1020system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1021system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1022system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1023system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
670system.cpu.l2cache.replacements 87004 # number of replacements
671system.cpu.l2cache.tagsinuse 64771.472210 # Cycle average of tags in use
672system.cpu.l2cache.total_refs 3487444 # Total number of references to valid blocks.
673system.cpu.l2cache.sampled_refs 151687 # Sample count of references to valid blocks.
674system.cpu.l2cache.avg_refs 22.991054 # Average number of references to valid blocks.
| 1024system.cpu.toL2Bus.throughput 49236259 # Throughput (bytes/s)
1025system.cpu.toL2Bus.trans_dist::ReadReq 2696119 # Transaction distribution
1026system.cpu.toL2Bus.trans_dist::ReadResp 2695598 # Transaction distribution
1027system.cpu.toL2Bus.trans_dist::WriteReq 13727 # Transaction distribution
1028system.cpu.toL2Bus.trans_dist::WriteResp 13727 # Transaction distribution
1029system.cpu.toL2Bus.trans_dist::Writeback 1543169 # Transaction distribution
1030system.cpu.toL2Bus.trans_dist::UpgradeReq 2198 # Transaction distribution
1031system.cpu.toL2Bus.trans_dist::UpgradeResp 2198 # Transaction distribution
1032system.cpu.toL2Bus.trans_dist::ReadExReq 360759 # Transaction distribution
1033system.cpu.toL2Bus.trans_dist::ReadExResp 314063 # Transaction distribution
1034system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1583833 # Packet count per connected master and slave (bytes)
1035system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5979450 # Packet count per connected master and slave (bytes)
1036system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 7815 # Packet count per connected master and slave (bytes)
1037system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 17592 # Packet count per connected master and slave (bytes)
1038system.cpu.toL2Bus.pkt_count 7588690 # Packet count per connected master and slave (bytes)
1039system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50682240 # Cumulative packet size per connected master and slave (bytes)
1040system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 204056779 # Cumulative packet size per connected master and slave (bytes)
1041system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 219328 # Cumulative packet size per connected master and slave (bytes)
1042system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 574336 # Cumulative packet size per connected master and slave (bytes)
1043system.cpu.toL2Bus.tot_pkt_size 255532683 # Cumulative packet size per connected master and slave (bytes)
1044system.cpu.toL2Bus.data_through_bus 255511115 # Total data (bytes)
1045system.cpu.toL2Bus.snoop_data_through_bus 327616 # Total snoop data (bytes)
1046system.cpu.toL2Bus.reqLayer0.occupancy 3834241500 # Layer occupancy (ticks)
1047system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1048system.cpu.toL2Bus.snoopLayer0.occupancy 505500 # Layer occupancy (ticks)
1049system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1050system.cpu.toL2Bus.respLayer0.occupancy 1187884500 # Layer occupancy (ticks)
1051system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1052system.cpu.toL2Bus.respLayer1.occupancy 3023860000 # Layer occupancy (ticks)
1053system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1054system.cpu.toL2Bus.respLayer2.occupancy 6582000 # Layer occupancy (ticks)
1055system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1056system.cpu.toL2Bus.respLayer3.occupancy 12927000 # Layer occupancy (ticks)
1057system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1058system.cpu.l2cache.replacements 86618 # number of replacements
1059system.cpu.l2cache.tagsinuse 64735.286295 # Cycle average of tags in use
1060system.cpu.l2cache.total_refs 3491811 # Total number of references to valid blocks.
1061system.cpu.l2cache.sampled_refs 151264 # Sample count of references to valid blocks.
1062system.cpu.l2cache.avg_refs 23.084217 # Average number of references to valid blocks.
|
675system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 1063system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
676system.cpu.l2cache.occ_blocks::writebacks 50378.956222 # Average occupied blocks per requestor
677system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140585 # Average occupied blocks per requestor
678system.cpu.l2cache.occ_blocks::cpu.inst 3347.055983 # Average occupied blocks per requestor
679system.cpu.l2cache.occ_blocks::cpu.data 11045.319419 # Average occupied blocks per requestor
680system.cpu.l2cache.occ_percent::writebacks 0.768722 # Average percentage of cache occupancy
| 1064system.cpu.l2cache.occ_blocks::writebacks 49971.529408 # Average occupied blocks per requestor
1065system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.027392 # Average occupied blocks per requestor
1066system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.141401 # Average occupied blocks per requestor
1067system.cpu.l2cache.occ_blocks::cpu.inst 3486.795305 # Average occupied blocks per requestor
1068system.cpu.l2cache.occ_blocks::cpu.data 11276.792789 # Average occupied blocks per requestor
1069system.cpu.l2cache.occ_percent::writebacks 0.762505 # Average percentage of cache occupancy
1070system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
681system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
| 1071system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
682system.cpu.l2cache.occ_percent::cpu.inst 0.051072 # Average percentage of cache occupancy
683system.cpu.l2cache.occ_percent::cpu.data 0.168538 # Average percentage of cache occupancy
684system.cpu.l2cache.occ_percent::total 0.988334 # Average percentage of cache occupancy
685system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6442 # number of ReadReq hits
686system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2817 # number of ReadReq hits
687system.cpu.l2cache.ReadReq_hits::cpu.inst 778194 # number of ReadReq hits
688system.cpu.l2cache.ReadReq_hits::cpu.data 1278591 # number of ReadReq hits
689system.cpu.l2cache.ReadReq_hits::total 2066044 # number of ReadReq hits
690system.cpu.l2cache.Writeback_hits::writebacks 1541849 # number of Writeback hits
691system.cpu.l2cache.Writeback_hits::total 1541849 # number of Writeback hits
692system.cpu.l2cache.UpgradeReq_hits::cpu.data 308 # number of UpgradeReq hits
693system.cpu.l2cache.UpgradeReq_hits::total 308 # number of UpgradeReq hits
694system.cpu.l2cache.ReadExReq_hits::cpu.data 199895 # number of ReadExReq hits
695system.cpu.l2cache.ReadExReq_hits::total 199895 # number of ReadExReq hits
696system.cpu.l2cache.demand_hits::cpu.dtb.walker 6442 # number of demand (read+write) hits
697system.cpu.l2cache.demand_hits::cpu.itb.walker 2817 # number of demand (read+write) hits
698system.cpu.l2cache.demand_hits::cpu.inst 778194 # number of demand (read+write) hits
699system.cpu.l2cache.demand_hits::cpu.data 1478486 # number of demand (read+write) hits
700system.cpu.l2cache.demand_hits::total 2265939 # number of demand (read+write) hits
701system.cpu.l2cache.overall_hits::cpu.dtb.walker 6442 # number of overall hits
702system.cpu.l2cache.overall_hits::cpu.itb.walker 2817 # number of overall hits
703system.cpu.l2cache.overall_hits::cpu.inst 778194 # number of overall hits
704system.cpu.l2cache.overall_hits::cpu.data 1478486 # number of overall hits
705system.cpu.l2cache.overall_hits::total 2265939 # number of overall hits
| 1072system.cpu.l2cache.occ_percent::cpu.inst 0.053204 # Average percentage of cache occupancy
1073system.cpu.l2cache.occ_percent::cpu.data 0.172070 # Average percentage of cache occupancy
1074system.cpu.l2cache.occ_percent::total 0.987782 # Average percentage of cache occupancy
1075system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6224 # number of ReadReq hits
1076system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2803 # number of ReadReq hits
1077system.cpu.l2cache.ReadReq_hits::cpu.inst 779038 # number of ReadReq hits
1078system.cpu.l2cache.ReadReq_hits::cpu.data 1279905 # number of ReadReq hits
1079system.cpu.l2cache.ReadReq_hits::total 2067970 # number of ReadReq hits
1080system.cpu.l2cache.Writeback_hits::writebacks 1543169 # number of Writeback hits
1081system.cpu.l2cache.Writeback_hits::total 1543169 # number of Writeback hits
1082system.cpu.l2cache.UpgradeReq_hits::cpu.data 330 # number of UpgradeReq hits
1083system.cpu.l2cache.UpgradeReq_hits::total 330 # number of UpgradeReq hits
1084system.cpu.l2cache.ReadExReq_hits::cpu.data 201356 # number of ReadExReq hits
1085system.cpu.l2cache.ReadExReq_hits::total 201356 # number of ReadExReq hits
1086system.cpu.l2cache.demand_hits::cpu.dtb.walker 6224 # number of demand (read+write) hits
1087system.cpu.l2cache.demand_hits::cpu.itb.walker 2803 # number of demand (read+write) hits
1088system.cpu.l2cache.demand_hits::cpu.inst 779038 # number of demand (read+write) hits
1089system.cpu.l2cache.demand_hits::cpu.data 1481261 # number of demand (read+write) hits
1090system.cpu.l2cache.demand_hits::total 2269326 # number of demand (read+write) hits
1091system.cpu.l2cache.overall_hits::cpu.dtb.walker 6224 # number of overall hits
1092system.cpu.l2cache.overall_hits::cpu.itb.walker 2803 # number of overall hits
1093system.cpu.l2cache.overall_hits::cpu.inst 779038 # number of overall hits
1094system.cpu.l2cache.overall_hits::cpu.data 1481261 # number of overall hits
1095system.cpu.l2cache.overall_hits::total 2269326 # number of overall hits
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822system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14803865 # number of UpgradeReq MSHR miss cycles
823system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4210880830 # number of ReadExReq MSHR miss cycles
824system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4210880830 # number of ReadExReq MSHR miss cycles
825system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles
826system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 628701625 # number of demand (read+write) MSHR miss cycles
827system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5535152416 # number of demand (read+write) MSHR miss cycles
828system.cpu.l2cache.demand_mshr_miss_latency::total 6164135296 # number of demand (read+write) MSHR miss cycles
829system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles
830system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 628701625 # number of overall MSHR miss cycles
831system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5535152416 # number of overall MSHR miss cycles
832system.cpu.l2cache.overall_mshr_miss_latency::total 6164135296 # number of overall MSHR miss cycles
833system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86642612000 # number of ReadReq MSHR uncacheable cycles
834system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86642612000 # number of ReadReq MSHR uncacheable cycles
835system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2356974000 # number of WriteReq MSHR uncacheable cycles
836system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2356974000 # number of WriteReq MSHR uncacheable cycles
837system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88999586000 # number of overall MSHR uncacheable cycles
838system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88999586000 # number of overall MSHR uncacheable cycles
839system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001772 # mshr miss rate for ReadReq accesses
840system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016287 # mshr miss rate for ReadReq accesses
841system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021813 # mshr miss rate for ReadReq accesses
842system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019645 # mshr miss rate for ReadReq accesses
843system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818074 # mshr miss rate for UpgradeReq accesses
844system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818074 # mshr miss rate for UpgradeReq accesses
845system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361998 # mshr miss rate for ReadExReq accesses
846system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361998 # mshr miss rate for ReadExReq accesses
847system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001772 # mshr miss rate for demand accesses
848system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016287 # mshr miss rate for demand accesses
849system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087589 # mshr miss rate for demand accesses
850system.cpu.l2cache.demand_mshr_miss_rate::total 0.063955 # mshr miss rate for demand accesses
851system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001772 # mshr miss rate for overall accesses
852system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016287 # mshr miss rate for overall accesses
853system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087589 # mshr miss rate for overall accesses
854system.cpu.l2cache.overall_mshr_miss_rate::total 0.063955 # mshr miss rate for overall accesses
855system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency
856system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48797.083592 # average ReadReq mshr miss latency
857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46446.113426 # average ReadReq mshr miss latency
858system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 47178.919978 # average ReadReq mshr miss latency
859system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10688.711191 # average UpgradeReq mshr miss latency
860system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10688.711191 # average UpgradeReq mshr miss latency
861system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37126.767385 # average ReadExReq mshr miss latency
862system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37126.767385 # average ReadExReq mshr miss latency
863system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
864system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48797.083592 # average overall mshr miss latency
865system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38998.896760 # average overall mshr miss latency
866system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39814.851415 # average overall mshr miss latency
867system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48797.083592 # average overall mshr miss latency
869system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38998.896760 # average overall mshr miss latency
870system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39814.851415 # average overall mshr miss latency
| 1219system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses
1220system.cpu.l2cache.overall_mshr_misses::cpu.data 140948 # number of overall MSHR misses
1221system.cpu.l2cache.overall_mshr_misses::total 153826 # number of overall MSHR misses
1222system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles
1223system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles
1224system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 851715758 # number of ReadReq MSHR miss cycles
1225system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1771468289 # number of ReadReq MSHR miss cycles
1226system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2623586547 # number of ReadReq MSHR miss cycles
1227system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14290818 # number of UpgradeReq MSHR miss cycles
1228system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14290818 # number of UpgradeReq MSHR miss cycles
1229system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6265697836 # number of ReadExReq MSHR miss cycles
1230system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6265697836 # number of ReadExReq MSHR miss cycles
1231system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
1232system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles
1233system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851715758 # number of demand (read+write) MSHR miss cycles
1234system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8037166125 # number of demand (read+write) MSHR miss cycles
1235system.cpu.l2cache.demand_mshr_miss_latency::total 8889284383 # number of demand (read+write) MSHR miss cycles
1236system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles
1237system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles
1238system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851715758 # number of overall MSHR miss cycles
1239system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8037166125 # number of overall MSHR miss cycles
1240system.cpu.l2cache.overall_mshr_miss_latency::total 8889284383 # number of overall MSHR miss cycles
1241system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86643520000 # number of ReadReq MSHR uncacheable cycles
1242system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86643520000 # number of ReadReq MSHR uncacheable cycles
1243system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2359628500 # number of WriteReq MSHR uncacheable cycles
1244system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2359628500 # number of WriteReq MSHR uncacheable cycles
1245system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89003148500 # number of overall MSHR uncacheable cycles
1246system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89003148500 # number of overall MSHR uncacheable cycles
1247system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses
1248system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for ReadReq accesses
1249system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses
1250system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021610 # mshr miss rate for ReadReq accesses
1251system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019509 # mshr miss rate for ReadReq accesses
1252system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.801921 # mshr miss rate for UpgradeReq accesses
1253system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.801921 # mshr miss rate for UpgradeReq accesses
1254system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358810 # mshr miss rate for ReadExReq accesses
1255system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358810 # mshr miss rate for ReadExReq accesses
1256system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for demand accesses
1257system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for demand accesses
1258system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses
1259system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for demand accesses
1260system.cpu.l2cache.demand_mshr_miss_rate::total 0.063482 # mshr miss rate for demand accesses
1261system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for overall accesses
1262system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for overall accesses
1263system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses
1264system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for overall accesses
1265system.cpu.l2cache.overall_mshr_miss_rate::total 0.063482 # mshr miss rate for overall accesses
1266system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
1267system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
1268system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66168.098042 # average ReadReq mshr miss latency
1269system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62664.695921 # average ReadReq mshr miss latency
1270system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63761.308163 # average ReadReq mshr miss latency
1271system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10696.720060 # average UpgradeReq mshr miss latency
1272system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10696.720060 # average UpgradeReq mshr miss latency
1273system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55606.615572 # average ReadExReq mshr miss latency
1274system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55606.615572 # average ReadExReq mshr miss latency
1275system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
1276system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
1277system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency
1278system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency
1279system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency
1280system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
1281system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
1282system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency
1283system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency
1284system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency
|
871system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
872system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
873system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
874system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
875system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
876system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
877system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
878
879---------- End Simulation Statistics ----------
| 1285system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1286system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1287system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1288system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1289system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1290system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1291system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1292
1293---------- End Simulation Statistics ----------
|