| stats.txt (9314:63e7cfff4188) | stats.txt (9474:23c3e1c0e9e4) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.191113 # Number of seconds simulated 4sim_ticks 5191112864000 # Number of ticks simulated 5final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.191113 # Number of seconds simulated 4sim_ticks 5191112864000 # Number of ticks simulated 5final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1106680 # Simulator instruction rate (inst/s) 8host_op_rate 2133324 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44796411922 # Simulator tick rate (ticks/s) 10host_mem_usage 384016 # Number of bytes of host memory used 11host_seconds 115.88 # Real time elapsed on the host 12sim_insts 128244614 # Number of instructions simulated 13sim_ops 247214600 # Number of ops (including micro ops) simulated | 7host_inst_rate 1076481 # Simulator instruction rate (inst/s) 8host_op_rate 2075111 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43574012985 # Simulator tick rate (ticks/s) 10host_mem_usage 651144 # Number of bytes of host memory used 11host_seconds 119.13 # Real time elapsed on the host 12sim_insts 128244620 # Number of instructions simulated 13sim_ops 247214608 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9026368 # Number of bytes read from this memory 18system.physmem.bytes_read::total 12705024 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 825984 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 825984 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 8129280 # Number of bytes written to this memory --- 152 unchanged lines hidden (view full) --- 174system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 14system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9026368 # Number of bytes read from this memory 18system.physmem.bytes_read::total 12705024 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 825984 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 825984 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 8129280 # Number of bytes written to this memory --- 152 unchanged lines hidden (view full) --- 174system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 182system.physmem.totQLat 2876233269 # Total cycles spent in queuing delays 183system.physmem.totMemAccLat 6438459269 # Sum of mem lat for all requests | 182system.physmem.totQLat 2876225269 # Total cycles spent in queuing delays 183system.physmem.totMemAccLat 6438451269 # Sum of mem lat for all requests |
| 184system.physmem.totBusLat 793712000 # Total cycles spent in databus access 185system.physmem.totBankLat 2768514000 # Total cycles spent in bank access | 184system.physmem.totBusLat 793712000 # Total cycles spent in databus access 185system.physmem.totBankLat 2768514000 # Total cycles spent in bank access |
| 186system.physmem.avgQLat 14495.10 # Average queueing delay per request | 186system.physmem.avgQLat 14495.06 # Average queueing delay per request |
| 187system.physmem.avgBankLat 13952.23 # Average bank access latency per request 188system.physmem.avgBusLat 4000.00 # Average bus latency per request | 187system.physmem.avgBankLat 13952.23 # Average bank access latency per request 188system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 189system.physmem.avgMemAccLat 32447.33 # Average memory access latency | 189system.physmem.avgMemAccLat 32447.29 # Average memory access latency |
| 190system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s 191system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s 192system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s 193system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s 194system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 195system.physmem.busUtil 0.03 # Data bus utilization in percentage 196system.physmem.avgRdQLen 0.00 # Average read queue length over time 197system.physmem.avgWrQLen 9.06 # Average write queue length over time --- 104 unchanged lines hidden (view full) --- 302system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 303system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 304system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 305system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 306system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 307system.cpu.numCycles 10382225728 # number of cpu cycles simulated 308system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 309system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 190system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s 191system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s 192system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s 193system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s 194system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 195system.physmem.busUtil 0.03 # Data bus utilization in percentage 196system.physmem.avgRdQLen 0.00 # Average read queue length over time 197system.physmem.avgWrQLen 9.06 # Average write queue length over time --- 104 unchanged lines hidden (view full) --- 302system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 303system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 304system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 305system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 306system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 307system.cpu.numCycles 10382225728 # number of cpu cycles simulated 308system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 309system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 310system.cpu.committedInsts 128244614 # Number of instructions committed 311system.cpu.committedOps 247214600 # Number of ops (including micro ops) committed 312system.cpu.num_int_alu_accesses 231949861 # Number of integer alu accesses | 310system.cpu.committedInsts 128244620 # Number of instructions committed 311system.cpu.committedOps 247214608 # Number of ops (including micro ops) committed 312system.cpu.num_int_alu_accesses 231949869 # Number of integer alu accesses |
| 313system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 314system.cpu.num_func_calls 0 # number of times a function call or return occured 315system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls | 313system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 314system.cpu.num_func_calls 0 # number of times a function call or return occured 315system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls |
| 316system.cpu.num_int_insts 231949861 # number of integer instructions | 316system.cpu.num_int_insts 231949869 # number of integer instructions |
| 317system.cpu.num_fp_insts 0 # number of float instructions | 317system.cpu.num_fp_insts 0 # number of float instructions |
| 318system.cpu.num_int_register_reads 566905512 # number of times the integer registers were read 319system.cpu.num_int_register_writes 293156466 # number of times the integer registers were written | 318system.cpu.num_int_register_reads 566905534 # number of times the integer registers were read 319system.cpu.num_int_register_writes 293156476 # number of times the integer registers were written |
| 320system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 321system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 320system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 321system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 322system.cpu.num_mem_refs 22227093 # number of memory refs | 322system.cpu.num_mem_refs 22227095 # number of memory refs |
| 323system.cpu.num_load_insts 13866667 # Number of load instructions | 323system.cpu.num_load_insts 13866667 # Number of load instructions |
| 324system.cpu.num_store_insts 8360426 # Number of store instructions | 324system.cpu.num_store_insts 8360428 # Number of store instructions |
| 325system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles 326system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles 327system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles 328system.cpu.idle_fraction 0.942147 # Percentage of idle cycles 329system.cpu.kern.inst.arm 0 # number of arm instructions executed 330system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 331system.cpu.icache.replacements 790930 # number of replacements 332system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use | 325system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles 326system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles 327system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles 328system.cpu.idle_fraction 0.942147 # Percentage of idle cycles 329system.cpu.kern.inst.arm 0 # number of arm instructions executed 330system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 331system.cpu.icache.replacements 790930 # number of replacements 332system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use |
| 333system.cpu.icache.total_refs 144455339 # Total number of references to valid blocks. | 333system.cpu.icache.total_refs 144455345 # Total number of references to valid blocks. |
| 334system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. | 334system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. |
| 335system.cpu.icache.avg_refs 182.521700 # Average number of references to valid blocks. | 335system.cpu.icache.avg_refs 182.521707 # Average number of references to valid blocks. |
| 336system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. 337system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor 338system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy 339system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy | 336system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. 337system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor 338system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy 339system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy |
| 340system.cpu.icache.ReadReq_hits::cpu.inst 144455339 # number of ReadReq hits 341system.cpu.icache.ReadReq_hits::total 144455339 # number of ReadReq hits 342system.cpu.icache.demand_hits::cpu.inst 144455339 # number of demand (read+write) hits 343system.cpu.icache.demand_hits::total 144455339 # number of demand (read+write) hits 344system.cpu.icache.overall_hits::cpu.inst 144455339 # number of overall hits 345system.cpu.icache.overall_hits::total 144455339 # number of overall hits | 340system.cpu.icache.ReadReq_hits::cpu.inst 144455345 # number of ReadReq hits 341system.cpu.icache.ReadReq_hits::total 144455345 # number of ReadReq hits 342system.cpu.icache.demand_hits::cpu.inst 144455345 # number of demand (read+write) hits 343system.cpu.icache.demand_hits::total 144455345 # number of demand (read+write) hits 344system.cpu.icache.overall_hits::cpu.inst 144455345 # number of overall hits 345system.cpu.icache.overall_hits::total 144455345 # number of overall hits |
| 346system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses 347system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses 348system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses 349system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses 350system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses 351system.cpu.icache.overall_misses::total 791449 # number of overall misses 352system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871281000 # number of ReadReq miss cycles 353system.cpu.icache.ReadReq_miss_latency::total 10871281000 # number of ReadReq miss cycles 354system.cpu.icache.demand_miss_latency::cpu.inst 10871281000 # number of demand (read+write) miss cycles 355system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles 356system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles 357system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles | 346system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses 347system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses 348system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses 349system.cpu.icache.demand_misses::total 791449 # number of demand (read+write) misses 350system.cpu.icache.overall_misses::cpu.inst 791449 # number of overall misses 351system.cpu.icache.overall_misses::total 791449 # number of overall misses 352system.cpu.icache.ReadReq_miss_latency::cpu.inst 10871281000 # number of ReadReq miss cycles 353system.cpu.icache.ReadReq_miss_latency::total 10871281000 # number of ReadReq miss cycles 354system.cpu.icache.demand_miss_latency::cpu.inst 10871281000 # number of demand (read+write) miss cycles 355system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles 356system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles 357system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles |
| 358system.cpu.icache.ReadReq_accesses::cpu.inst 145246788 # number of ReadReq accesses(hits+misses) 359system.cpu.icache.ReadReq_accesses::total 145246788 # number of ReadReq accesses(hits+misses) 360system.cpu.icache.demand_accesses::cpu.inst 145246788 # number of demand (read+write) accesses 361system.cpu.icache.demand_accesses::total 145246788 # number of demand (read+write) accesses 362system.cpu.icache.overall_accesses::cpu.inst 145246788 # number of overall (read+write) accesses 363system.cpu.icache.overall_accesses::total 145246788 # number of overall (read+write) accesses | 358system.cpu.icache.ReadReq_accesses::cpu.inst 145246794 # number of ReadReq accesses(hits+misses) 359system.cpu.icache.ReadReq_accesses::total 145246794 # number of ReadReq accesses(hits+misses) 360system.cpu.icache.demand_accesses::cpu.inst 145246794 # number of demand (read+write) accesses 361system.cpu.icache.demand_accesses::total 145246794 # number of demand (read+write) accesses 362system.cpu.icache.overall_accesses::cpu.inst 145246794 # number of overall (read+write) accesses 363system.cpu.icache.overall_accesses::total 145246794 # number of overall (read+write) accesses |
| 364system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses 365system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses 366system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses 367system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses 368system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses 369system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses 370system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.921076 # average ReadReq miss latency 371system.cpu.icache.ReadReq_avg_miss_latency::total 13735.921076 # average ReadReq miss latency --- 195 unchanged lines hidden (view full) --- 567system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8766.151838 # average ReadReq mshr miss latency 568system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency 569system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency 570system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency 571system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency 572system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 573system.cpu.dcache.replacements 1620901 # number of replacements 574system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use | 364system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses 365system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses 366system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses 367system.cpu.icache.demand_miss_rate::total 0.005449 # miss rate for demand accesses 368system.cpu.icache.overall_miss_rate::cpu.inst 0.005449 # miss rate for overall accesses 369system.cpu.icache.overall_miss_rate::total 0.005449 # miss rate for overall accesses 370system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.921076 # average ReadReq miss latency 371system.cpu.icache.ReadReq_avg_miss_latency::total 13735.921076 # average ReadReq miss latency --- 195 unchanged lines hidden (view full) --- 567system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8766.151838 # average ReadReq mshr miss latency 568system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency 569system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency 570system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8766.151838 # average overall mshr miss latency 571system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 # average overall mshr miss latency 572system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 573system.cpu.dcache.replacements 1620901 # number of replacements 574system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use |
| 575system.cpu.dcache.total_refs 20018688 # Total number of references to valid blocks. | 575system.cpu.dcache.total_refs 20018690 # Total number of references to valid blocks. |
| 576system.cpu.dcache.sampled_refs 1621413 # Sample count of references to valid blocks. | 576system.cpu.dcache.sampled_refs 1621413 # Sample count of references to valid blocks. |
| 577system.cpu.dcache.avg_refs 12.346446 # Average number of references to valid blocks. | 577system.cpu.dcache.avg_refs 12.346447 # Average number of references to valid blocks. |
| 578system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit. 579system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor 580system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 581system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy 582system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits 583system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits | 578system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit. 579system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor 580system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 581system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy 582system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits 583system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits |
| 584system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits 585system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits 586system.cpu.dcache.demand_hits::cpu.data 20016506 # number of demand (read+write) hits 587system.cpu.dcache.demand_hits::total 20016506 # number of demand (read+write) hits 588system.cpu.dcache.overall_hits::cpu.data 20016506 # number of overall hits 589system.cpu.dcache.overall_hits::total 20016506 # number of overall hits | 584system.cpu.dcache.WriteReq_hits::cpu.data 8034928 # number of WriteReq hits 585system.cpu.dcache.WriteReq_hits::total 8034928 # number of WriteReq hits 586system.cpu.dcache.demand_hits::cpu.data 20016508 # number of demand (read+write) hits 587system.cpu.dcache.demand_hits::total 20016508 # number of demand (read+write) hits 588system.cpu.dcache.overall_hits::cpu.data 20016508 # number of overall hits 589system.cpu.dcache.overall_hits::total 20016508 # number of overall hits |
| 590system.cpu.dcache.ReadReq_misses::cpu.data 1308145 # number of ReadReq misses 591system.cpu.dcache.ReadReq_misses::total 1308145 # number of ReadReq misses 592system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses 593system.cpu.dcache.WriteReq_misses::total 315486 # number of WriteReq misses 594system.cpu.dcache.demand_misses::cpu.data 1623631 # number of demand (read+write) misses 595system.cpu.dcache.demand_misses::total 1623631 # number of demand (read+write) misses 596system.cpu.dcache.overall_misses::cpu.data 1623631 # number of overall misses 597system.cpu.dcache.overall_misses::total 1623631 # number of overall misses | 590system.cpu.dcache.ReadReq_misses::cpu.data 1308145 # number of ReadReq misses 591system.cpu.dcache.ReadReq_misses::total 1308145 # number of ReadReq misses 592system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses 593system.cpu.dcache.WriteReq_misses::total 315486 # number of WriteReq misses 594system.cpu.dcache.demand_misses::cpu.data 1623631 # number of demand (read+write) misses 595system.cpu.dcache.demand_misses::total 1623631 # number of demand (read+write) misses 596system.cpu.dcache.overall_misses::cpu.data 1623631 # number of overall misses 597system.cpu.dcache.overall_misses::total 1623631 # number of overall misses |
| 598system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313644000 # number of ReadReq miss cycles 599system.cpu.dcache.ReadReq_miss_latency::total 18313644000 # number of ReadReq miss cycles | 598system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313636000 # number of ReadReq miss cycles 599system.cpu.dcache.ReadReq_miss_latency::total 18313636000 # number of ReadReq miss cycles |
| 600system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702717500 # number of WriteReq miss cycles 601system.cpu.dcache.WriteReq_miss_latency::total 8702717500 # number of WriteReq miss cycles | 600system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702717500 # number of WriteReq miss cycles 601system.cpu.dcache.WriteReq_miss_latency::total 8702717500 # number of WriteReq miss cycles |
| 602system.cpu.dcache.demand_miss_latency::cpu.data 27016361500 # number of demand (read+write) miss cycles 603system.cpu.dcache.demand_miss_latency::total 27016361500 # number of demand (read+write) miss cycles 604system.cpu.dcache.overall_miss_latency::cpu.data 27016361500 # number of overall miss cycles 605system.cpu.dcache.overall_miss_latency::total 27016361500 # number of overall miss cycles | 602system.cpu.dcache.demand_miss_latency::cpu.data 27016353500 # number of demand (read+write) miss cycles 603system.cpu.dcache.demand_miss_latency::total 27016353500 # number of demand (read+write) miss cycles 604system.cpu.dcache.overall_miss_latency::cpu.data 27016353500 # number of overall miss cycles 605system.cpu.dcache.overall_miss_latency::total 27016353500 # number of overall miss cycles |
| 606system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses) 607system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses) | 606system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses) 607system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses) |
| 608system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses) 609system.cpu.dcache.WriteReq_accesses::total 8350412 # number of WriteReq accesses(hits+misses) 610system.cpu.dcache.demand_accesses::cpu.data 21640137 # number of demand (read+write) accesses 611system.cpu.dcache.demand_accesses::total 21640137 # number of demand (read+write) accesses 612system.cpu.dcache.overall_accesses::cpu.data 21640137 # number of overall (read+write) accesses 613system.cpu.dcache.overall_accesses::total 21640137 # number of overall (read+write) accesses | 608system.cpu.dcache.WriteReq_accesses::cpu.data 8350414 # number of WriteReq accesses(hits+misses) 609system.cpu.dcache.WriteReq_accesses::total 8350414 # number of WriteReq accesses(hits+misses) 610system.cpu.dcache.demand_accesses::cpu.data 21640139 # number of demand (read+write) accesses 611system.cpu.dcache.demand_accesses::total 21640139 # number of demand (read+write) accesses 612system.cpu.dcache.overall_accesses::cpu.data 21640139 # number of overall (read+write) accesses 613system.cpu.dcache.overall_accesses::total 21640139 # number of overall (read+write) accesses |
| 614system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098433 # miss rate for ReadReq accesses 615system.cpu.dcache.ReadReq_miss_rate::total 0.098433 # miss rate for ReadReq accesses 616system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037781 # miss rate for WriteReq accesses 617system.cpu.dcache.WriteReq_miss_rate::total 0.037781 # miss rate for WriteReq accesses 618system.cpu.dcache.demand_miss_rate::cpu.data 0.075029 # miss rate for demand accesses 619system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses 620system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses 621system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses | 614system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098433 # miss rate for ReadReq accesses 615system.cpu.dcache.ReadReq_miss_rate::total 0.098433 # miss rate for ReadReq accesses 616system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037781 # miss rate for WriteReq accesses 617system.cpu.dcache.WriteReq_miss_rate::total 0.037781 # miss rate for WriteReq accesses 618system.cpu.dcache.demand_miss_rate::cpu.data 0.075029 # miss rate for demand accesses 619system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses 620system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses 621system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses |
| 622system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.704926 # average ReadReq miss latency 623system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.704926 # average ReadReq miss latency | 622system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.698810 # average ReadReq miss latency 623system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.698810 # average ReadReq miss latency |
| 624system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.114712 # average WriteReq miss latency 625system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.114712 # average WriteReq miss latency | 624system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.114712 # average WriteReq miss latency 625system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.114712 # average WriteReq miss latency |
| 626system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency 627system.cpu.dcache.demand_avg_miss_latency::total 16639.471345 # average overall miss latency 628system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency 629system.cpu.dcache.overall_avg_miss_latency::total 16639.471345 # average overall miss latency | 626system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency 627system.cpu.dcache.demand_avg_miss_latency::total 16639.466418 # average overall miss latency 628system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency 629system.cpu.dcache.overall_avg_miss_latency::total 16639.466418 # average overall miss latency |
| 630system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.dcache.fast_writes 0 # number of fast writes performed 637system.cpu.dcache.cache_copies 0 # number of cache copies performed 638system.cpu.dcache.writebacks::writebacks 1538028 # number of writebacks 639system.cpu.dcache.writebacks::total 1538028 # number of writebacks 640system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308145 # number of ReadReq MSHR misses 641system.cpu.dcache.ReadReq_mshr_misses::total 1308145 # number of ReadReq MSHR misses 642system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses 643system.cpu.dcache.WriteReq_mshr_misses::total 315486 # number of WriteReq MSHR misses 644system.cpu.dcache.demand_mshr_misses::cpu.data 1623631 # number of demand (read+write) MSHR misses 645system.cpu.dcache.demand_mshr_misses::total 1623631 # number of demand (read+write) MSHR misses 646system.cpu.dcache.overall_mshr_misses::cpu.data 1623631 # number of overall MSHR misses 647system.cpu.dcache.overall_mshr_misses::total 1623631 # number of overall MSHR misses | 630system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.dcache.fast_writes 0 # number of fast writes performed 637system.cpu.dcache.cache_copies 0 # number of cache copies performed 638system.cpu.dcache.writebacks::writebacks 1538028 # number of writebacks 639system.cpu.dcache.writebacks::total 1538028 # number of writebacks 640system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308145 # number of ReadReq MSHR misses 641system.cpu.dcache.ReadReq_mshr_misses::total 1308145 # number of ReadReq MSHR misses 642system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315486 # number of WriteReq MSHR misses 643system.cpu.dcache.WriteReq_mshr_misses::total 315486 # number of WriteReq MSHR misses 644system.cpu.dcache.demand_mshr_misses::cpu.data 1623631 # number of demand (read+write) MSHR misses 645system.cpu.dcache.demand_mshr_misses::total 1623631 # number of demand (read+write) MSHR misses 646system.cpu.dcache.overall_mshr_misses::cpu.data 1623631 # number of overall MSHR misses 647system.cpu.dcache.overall_mshr_misses::total 1623631 # number of overall MSHR misses |
| 648system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697354000 # number of ReadReq MSHR miss cycles 649system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697354000 # number of ReadReq MSHR miss cycles | 648system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697346000 # number of ReadReq MSHR miss cycles 649system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697346000 # number of ReadReq MSHR miss cycles |
| 650system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071745500 # number of WriteReq MSHR miss cycles 651system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071745500 # number of WriteReq MSHR miss cycles | 650system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071745500 # number of WriteReq MSHR miss cycles 651system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071745500 # number of WriteReq MSHR miss cycles |
| 652system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769099500 # number of demand (read+write) MSHR miss cycles 653system.cpu.dcache.demand_mshr_miss_latency::total 23769099500 # number of demand (read+write) MSHR miss cycles 654system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769099500 # number of overall MSHR miss cycles 655system.cpu.dcache.overall_mshr_miss_latency::total 23769099500 # number of overall MSHR miss cycles | 652system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769091500 # number of demand (read+write) MSHR miss cycles 653system.cpu.dcache.demand_mshr_miss_latency::total 23769091500 # number of demand (read+write) MSHR miss cycles 654system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769091500 # number of overall MSHR miss cycles 655system.cpu.dcache.overall_mshr_miss_latency::total 23769091500 # number of overall MSHR miss cycles |
| 656system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles 657system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles 658system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469978500 # number of WriteReq MSHR uncacheable cycles 659system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469978500 # number of WriteReq MSHR uncacheable cycles 660system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96617154500 # number of overall MSHR uncacheable cycles 661system.cpu.dcache.overall_mshr_uncacheable_latency::total 96617154500 # number of overall MSHR uncacheable cycles 662system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098433 # mshr miss rate for ReadReq accesses 663system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098433 # mshr miss rate for ReadReq accesses 664system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037781 # mshr miss rate for WriteReq accesses 665system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037781 # mshr miss rate for WriteReq accesses 666system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for demand accesses 667system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses 668system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses 669system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses | 656system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles 657system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles 658system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469978500 # number of WriteReq MSHR uncacheable cycles 659system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469978500 # number of WriteReq MSHR uncacheable cycles 660system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96617154500 # number of overall MSHR uncacheable cycles 661system.cpu.dcache.overall_mshr_uncacheable_latency::total 96617154500 # number of overall MSHR uncacheable cycles 662system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098433 # mshr miss rate for ReadReq accesses 663system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098433 # mshr miss rate for ReadReq accesses 664system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037781 # mshr miss rate for WriteReq accesses 665system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037781 # mshr miss rate for WriteReq accesses 666system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for demand accesses 667system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses 668system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses 669system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses |
| 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.704926 # average ReadReq mshr miss latency 671system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.704926 # average ReadReq mshr miss latency | 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.698810 # average ReadReq mshr miss latency 671system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.698810 # average ReadReq mshr miss latency |
| 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712 # average WriteReq mshr miss latency 673system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712 # average WriteReq mshr miss latency | 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712 # average WriteReq mshr miss latency 673system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712 # average WriteReq mshr miss latency |
| 674system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency 675system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency 676system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency 677system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency | 674system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency 675system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency 676system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency 677system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency |
| 678system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 679system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 680system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 681system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 682system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 683system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 684system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 685system.cpu.l2cache.replacements 87015 # number of replacements --- 45 unchanged lines hidden (view full) --- 731system.cpu.l2cache.demand_misses::cpu.data 141963 # number of demand (read+write) misses 732system.cpu.l2cache.demand_misses::total 154875 # number of demand (read+write) misses 733system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 734system.cpu.l2cache.overall_misses::cpu.inst 12907 # number of overall misses 735system.cpu.l2cache.overall_misses::cpu.data 141963 # number of overall misses 736system.cpu.l2cache.overall_misses::total 154875 # number of overall misses 737system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles 738system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711631000 # number of ReadReq miss cycles | 678system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 679system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 680system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 681system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 682system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 683system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 684system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 685system.cpu.l2cache.replacements 87015 # number of replacements --- 45 unchanged lines hidden (view full) --- 731system.cpu.l2cache.demand_misses::cpu.data 141963 # number of demand (read+write) misses 732system.cpu.l2cache.demand_misses::total 154875 # number of demand (read+write) misses 733system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 734system.cpu.l2cache.overall_misses::cpu.inst 12907 # number of overall misses 735system.cpu.l2cache.overall_misses::cpu.data 141963 # number of overall misses 736system.cpu.l2cache.overall_misses::total 154875 # number of overall misses 737system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles 738system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711631000 # number of ReadReq miss cycles |
| 739system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599602500 # number of ReadReq miss cycles 740system.cpu.l2cache.ReadReq_miss_latency::total 2311578500 # number of ReadReq miss cycles | 739system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599594500 # number of ReadReq miss cycles 740system.cpu.l2cache.ReadReq_miss_latency::total 2311570500 # number of ReadReq miss cycles |
| 741system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16623000 # number of UpgradeReq miss cycles 742system.cpu.l2cache.UpgradeReq_miss_latency::total 16623000 # number of UpgradeReq miss cycles 743system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5723743500 # number of ReadExReq miss cycles 744system.cpu.l2cache.ReadExReq_miss_latency::total 5723743500 # number of ReadExReq miss cycles 745system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles 746system.cpu.l2cache.demand_miss_latency::cpu.inst 711631000 # number of demand (read+write) miss cycles | 741system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16623000 # number of UpgradeReq miss cycles 742system.cpu.l2cache.UpgradeReq_miss_latency::total 16623000 # number of UpgradeReq miss cycles 743system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5723743500 # number of ReadExReq miss cycles 744system.cpu.l2cache.ReadExReq_miss_latency::total 5723743500 # number of ReadExReq miss cycles 745system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles 746system.cpu.l2cache.demand_miss_latency::cpu.inst 711631000 # number of demand (read+write) miss cycles |
| 747system.cpu.l2cache.demand_miss_latency::cpu.data 7323346000 # number of demand (read+write) miss cycles 748system.cpu.l2cache.demand_miss_latency::total 8035322000 # number of demand (read+write) miss cycles | 747system.cpu.l2cache.demand_miss_latency::cpu.data 7323338000 # number of demand (read+write) miss cycles 748system.cpu.l2cache.demand_miss_latency::total 8035314000 # number of demand (read+write) miss cycles |
| 749system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles 750system.cpu.l2cache.overall_miss_latency::cpu.inst 711631000 # number of overall miss cycles | 749system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles 750system.cpu.l2cache.overall_miss_latency::cpu.inst 711631000 # number of overall miss cycles |
| 751system.cpu.l2cache.overall_miss_latency::cpu.data 7323346000 # number of overall miss cycles 752system.cpu.l2cache.overall_miss_latency::total 8035322000 # number of overall miss cycles | 751system.cpu.l2cache.overall_miss_latency::cpu.data 7323338000 # number of overall miss cycles 752system.cpu.l2cache.overall_miss_latency::total 8035314000 # number of overall miss cycles |
| 753system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6912 # number of ReadReq accesses(hits+misses) 754system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3081 # number of ReadReq accesses(hits+misses) 755system.cpu.l2cache.ReadReq_accesses::cpu.inst 791436 # number of ReadReq accesses(hits+misses) 756system.cpu.l2cache.ReadReq_accesses::cpu.data 1307310 # number of ReadReq accesses(hits+misses) 757system.cpu.l2cache.ReadReq_accesses::total 2108739 # number of ReadReq accesses(hits+misses) 758system.cpu.l2cache.Writeback_accesses::writebacks 1542259 # number of Writeback accesses(hits+misses) 759system.cpu.l2cache.Writeback_accesses::total 1542259 # number of Writeback accesses(hits+misses) 760system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1664 # number of UpgradeReq accesses(hits+misses) --- 23 unchanged lines hidden (view full) --- 784system.cpu.l2cache.demand_miss_rate::cpu.data 0.087598 # miss rate for demand accesses 785system.cpu.l2cache.demand_miss_rate::total 0.063944 # miss rate for demand accesses 786system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001623 # miss rate for overall accesses 787system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016308 # miss rate for overall accesses 788system.cpu.l2cache.overall_miss_rate::cpu.data 0.087598 # miss rate for overall accesses 789system.cpu.l2cache.overall_miss_rate::total 0.063944 # miss rate for overall accesses 790system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency 791system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.275432 # average ReadReq miss latency | 753system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6912 # number of ReadReq accesses(hits+misses) 754system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3081 # number of ReadReq accesses(hits+misses) 755system.cpu.l2cache.ReadReq_accesses::cpu.inst 791436 # number of ReadReq accesses(hits+misses) 756system.cpu.l2cache.ReadReq_accesses::cpu.data 1307310 # number of ReadReq accesses(hits+misses) 757system.cpu.l2cache.ReadReq_accesses::total 2108739 # number of ReadReq accesses(hits+misses) 758system.cpu.l2cache.Writeback_accesses::writebacks 1542259 # number of Writeback accesses(hits+misses) 759system.cpu.l2cache.Writeback_accesses::total 1542259 # number of Writeback accesses(hits+misses) 760system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1664 # number of UpgradeReq accesses(hits+misses) --- 23 unchanged lines hidden (view full) --- 784system.cpu.l2cache.demand_miss_rate::cpu.data 0.087598 # miss rate for demand accesses 785system.cpu.l2cache.demand_miss_rate::total 0.063944 # miss rate for demand accesses 786system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001623 # miss rate for overall accesses 787system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016308 # miss rate for overall accesses 788system.cpu.l2cache.overall_miss_rate::cpu.data 0.087598 # miss rate for overall accesses 789system.cpu.l2cache.overall_miss_rate::total 0.063944 # miss rate for overall accesses 790system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency 791system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.275432 # average ReadReq miss latency |
| 792system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.660711 # average ReadReq miss latency 793system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.505382 # average ReadReq miss latency | 792system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.379348 # average ReadReq miss latency 793system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.311888 # average ReadReq miss latency |
| 794system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency 795system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency 796system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.132300 # average ReadExReq miss latency 797system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.132300 # average ReadExReq miss latency 798system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency 799system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency | 794system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency 795system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency 796system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.132300 # average ReadExReq miss latency 797system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.132300 # average ReadExReq miss latency 798system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency 799system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency |
| 800system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::total 51882.627926 # average overall miss latency | 800system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::total 51882.576271 # average overall miss latency |
| 802system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency | 802system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency |
| 804system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::total 51882.627926 # average overall miss latency | 804system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::total 51882.576271 # average overall miss latency |
| 806system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 811system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 812system.cpu.l2cache.fast_writes 0 # number of fast writes performed 813system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 826system.cpu.l2cache.demand_mshr_misses::cpu.data 141963 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::total 154875 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.inst 12907 # number of overall MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.data 141963 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544173395 # number of ReadReq MSHR miss cycles | 806system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 811system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 812system.cpu.l2cache.fast_writes 0 # number of fast writes performed 813system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 826system.cpu.l2cache.demand_mshr_misses::cpu.data 141963 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::total 154875 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.inst 12907 # number of overall MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.data 141963 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles 833system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544173395 # number of ReadReq MSHR miss cycles |
| 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230984255 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775437660 # number of ReadReq MSHR miss cycles | 834system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230976255 # number of ReadReq MSHR miss cycles 835system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775429660 # number of ReadReq MSHR miss cycles |
| 836system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles 837system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249333352 # number of ReadExReq MSHR miss cycles 839system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249333352 # number of ReadExReq MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280010 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544173395 # number of demand (read+write) MSHR miss cycles | 836system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles 837system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles 838system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249333352 # number of ReadExReq MSHR miss cycles 839system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4249333352 # number of ReadExReq MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 280010 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 544173395 # number of demand (read+write) MSHR miss cycles |
| 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480317607 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::total 6024771012 # number of demand (read+write) MSHR miss cycles | 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480309607 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::total 6024763012 # number of demand (read+write) MSHR miss cycles |
| 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280010 # number of overall MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544173395 # number of overall MSHR miss cycles | 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280010 # number of overall MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 544173395 # number of overall MSHR miss cycles |
| 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480317607 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::total 6024771012 # number of overall MSHR miss cycles | 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480309607 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::total 6024763012 # number of overall MSHR miss cycles |
| 848system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86592298500 # number of ReadReq MSHR uncacheable cycles 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86592298500 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2307004500 # number of WriteReq MSHR uncacheable cycles 851system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2307004500 # number of WriteReq MSHR uncacheable cycles 852system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88899303000 # number of overall MSHR uncacheable cycles 853system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88899303000 # number of overall MSHR uncacheable cycles 854system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for ReadReq accesses 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for ReadReq accesses --- 8 unchanged lines hidden (view full) --- 864system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for demand accesses 865system.cpu.l2cache.demand_mshr_miss_rate::total 0.063944 # mshr miss rate for demand accesses 866system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for overall accesses 867system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for overall accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses 870system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.105989 # average ReadReq mshr miss latency | 848system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86592298500 # number of ReadReq MSHR uncacheable cycles 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86592298500 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2307004500 # number of WriteReq MSHR uncacheable cycles 851system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2307004500 # number of WriteReq MSHR uncacheable cycles 852system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88899303000 # number of overall MSHR uncacheable cycles 853system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88899303000 # number of overall MSHR uncacheable cycles 854system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for ReadReq accesses 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for ReadReq accesses --- 8 unchanged lines hidden (view full) --- 864system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for demand accesses 865system.cpu.l2cache.demand_mshr_miss_rate::total 0.063944 # mshr miss rate for demand accesses 866system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001623 # mshr miss rate for overall accesses 867system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016308 # mshr miss rate for overall accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087598 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses 870system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.105989 # average ReadReq mshr miss latency |
| 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.209369 # average ReadReq mshr miss latency 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.016205 # average ReadReq mshr miss latency | 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43293.928006 # average ReadReq mshr miss latency 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42941.822711 # average ReadReq mshr miss latency |
| 874system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency 875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency 876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198 # average ReadExReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.167198 # average ReadExReq mshr miss latency 878system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency 879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency | 874system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency 875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency 876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198 # average ReadExReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37429.167198 # average ReadExReq mshr miss latency 878system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency 879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency |
| 880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency | 880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency |
| 882system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency 883system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency | 882system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency 883system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42161.105989 # average overall mshr miss latency |
| 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency | 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency |
| 886system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 887system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 888system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 889system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 890system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 891system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 892system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 893 894---------- End Simulation Statistics ---------- | 886system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 887system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 888system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 889system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 890system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 891system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 892system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 893 894---------- End Simulation Statistics ---------- |