Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.187896 # Number of seconds simulated
4sim_ticks 5187896410000 # Number of ticks simulated
5final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 834857 # Simulator instruction rate (inst/s)
8host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 33766110220 # Simulator tick rate (ticks/s)
10host_mem_usage 354356 # Number of bytes of host memory used
11host_seconds 153.64 # Real time elapsed on the host

7host_inst_rate 812782 # Simulator instruction rate (inst/s)
8host_op_rate 1566838 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 32873266023 # Simulator tick rate (ticks/s)
10host_mem_usage 347504 # Number of bytes of host memory used
11host_seconds 157.82 # Real time elapsed on the host

12sim_insts 128269216 # Number of instructions simulated
13sim_ops 247270559 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.inst 826944 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8996288 # Number of bytes read from this memory
18system.physmem.bytes_read::total 12690880 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 826944 # Number of instructions bytes read from this memory

--- 34 unchanged lines hidden (view full) ---

54system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses
55system.iocache.ReadReq_misses::total 838 # number of ReadReq misses
56system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
57system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
58system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses
59system.iocache.demand_misses::total 47558 # number of demand (read+write) misses
60system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses
61system.iocache.overall_misses::total 47558 # number of overall misses

62system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles
63system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles

62system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130086932 # number of ReadReq miss cycles
63system.iocache.ReadReq_miss_latency::total 130086932 # number of ReadReq miss cycles

64system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles
65system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles

66system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles
67system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles
68system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles
69system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles

66system.iocache.demand_miss_latency::pc.south_bridge.ide 10826250092 # number of demand (read+write) miss cycles
67system.iocache.demand_miss_latency::total 10826250092 # number of demand (read+write) miss cycles
68system.iocache.overall_miss_latency::pc.south_bridge.ide 10826250092 # number of overall miss cycles
69system.iocache.overall_miss_latency::total 10826250092 # number of overall miss cycles

70system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses)
71system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses)
72system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
73system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
74system.iocache.demand_accesses::pc.south_bridge.ide 47558 # number of demand (read+write) accesses
75system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses
76system.iocache.overall_accesses::pc.south_bridge.ide 47558 # number of overall (read+write) accesses
77system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses
78system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
79system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
80system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
81system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
82system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
83system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
84system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
85system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses

86system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency
87system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency

86system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155235.002387 # average ReadReq miss latency
87system.iocache.ReadReq_avg_miss_latency::total 155235.002387 # average ReadReq miss latency

88system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency
89system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency

90system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency
91system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency
92system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency
93system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency
94system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked

90system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency
91system.iocache.demand_avg_miss_latency::total 227643.090374 # average overall miss latency
92system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency
93system.iocache.overall_avg_miss_latency::total 227643.090374 # average overall miss latency
94system.iocache.blocked_cycles::no_mshrs 90078 # number of cycles access was blocked

95system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
96system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked
97system.iocache.blocked::no_targets 0 # number of cycles access was blocked

98system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked

98system.iocache.avg_blocked_cycles::no_mshrs 8.170340 # average number of cycles each access was blocked

99system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
100system.iocache.fast_writes 0 # number of fast writes performed
101system.iocache.cache_copies 0 # number of cache copies performed
102system.iocache.writebacks::writebacks 46667 # number of writebacks
103system.iocache.writebacks::total 46667 # number of writebacks
104system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 838 # number of ReadReq MSHR misses
105system.iocache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses
106system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
107system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
108system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 # number of demand (read+write) MSHR misses
109system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses
110system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses
111system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses

112system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles
113system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles
114system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles
115system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles
116system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles
117system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles
118system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles
119system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles

112system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86510932 # number of ReadReq MSHR miss cycles
113system.iocache.ReadReq_mshr_miss_latency::total 86510932 # number of ReadReq MSHR miss cycles
114system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266723160 # number of WriteReq MSHR miss cycles
115system.iocache.WriteReq_mshr_miss_latency::total 8266723160 # number of WriteReq MSHR miss cycles
116system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of demand (read+write) MSHR miss cycles
117system.iocache.demand_mshr_miss_latency::total 8353234092 # number of demand (read+write) MSHR miss cycles
118system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8353234092 # number of overall MSHR miss cycles
119system.iocache.overall_mshr_miss_latency::total 8353234092 # number of overall MSHR miss cycles

120system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
121system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
122system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
123system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
124system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
125system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
126system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
127system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses

128system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency
129system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency
130system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency
131system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency
132system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency
133system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency
134system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency
135system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency

128system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103235.002387 # average ReadReq mshr miss latency
129system.iocache.ReadReq_avg_mshr_miss_latency::total 103235.002387 # average ReadReq mshr miss latency
130system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176941.848459 # average WriteReq mshr miss latency
131system.iocache.WriteReq_avg_mshr_miss_latency::total 176941.848459 # average WriteReq mshr miss latency
132system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency
133system.iocache.demand_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency
134system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175643.090374 # average overall mshr miss latency
135system.iocache.overall_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency

136system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
137system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
138system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
139system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
140system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
141system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
142system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
143system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).

--- 288 unchanged lines hidden (view full) ---

432system.cpu.dcache.ReadReq_misses::cpu.data 1306270 # number of ReadReq misses
433system.cpu.dcache.ReadReq_misses::total 1306270 # number of ReadReq misses
434system.cpu.dcache.WriteReq_misses::cpu.data 314797 # number of WriteReq misses
435system.cpu.dcache.WriteReq_misses::total 314797 # number of WriteReq misses
436system.cpu.dcache.demand_misses::cpu.data 1621067 # number of demand (read+write) misses
437system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses
438system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses
439system.cpu.dcache.overall_misses::total 1621067 # number of overall misses

440system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles
441system.cpu.dcache.ReadReq_miss_latency::total 18175236500 # number of ReadReq miss cycles

440system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175237000 # number of ReadReq miss cycles
441system.cpu.dcache.ReadReq_miss_latency::total 18175237000 # number of ReadReq miss cycles

442system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles
443system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles

444system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles
445system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles
446system.cpu.dcache.overall_miss_latency::cpu.data 27078679000 # number of overall miss cycles
447system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles

444system.cpu.dcache.demand_miss_latency::cpu.data 27078679500 # number of demand (read+write) miss cycles
445system.cpu.dcache.demand_miss_latency::total 27078679500 # number of demand (read+write) miss cycles
446system.cpu.dcache.overall_miss_latency::cpu.data 27078679500 # number of overall miss cycles
447system.cpu.dcache.overall_miss_latency::total 27078679500 # number of overall miss cycles

448system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses)
449system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses)
450system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses)
451system.cpu.dcache.WriteReq_accesses::total 8353033 # number of WriteReq accesses(hits+misses)
452system.cpu.dcache.demand_accesses::cpu.data 21651863 # number of demand (read+write) accesses
453system.cpu.dcache.demand_accesses::total 21651863 # number of demand (read+write) accesses
454system.cpu.dcache.overall_accesses::cpu.data 21651863 # number of overall (read+write) accesses
455system.cpu.dcache.overall_accesses::total 21651863 # number of overall (read+write) accesses
456system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098224 # miss rate for ReadReq accesses
457system.cpu.dcache.ReadReq_miss_rate::total 0.098224 # miss rate for ReadReq accesses
458system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037687 # miss rate for WriteReq accesses
459system.cpu.dcache.WriteReq_miss_rate::total 0.037687 # miss rate for WriteReq accesses
460system.cpu.dcache.demand_miss_rate::cpu.data 0.074870 # miss rate for demand accesses
461system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses
462system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses
463system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses

464system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency
465system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency

464system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843999 # average ReadReq miss latency
465system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843999 # average ReadReq miss latency

466system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency
467system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency

468system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency
469system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency
470system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency
471system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency

468system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency
469system.cpu.dcache.demand_avg_miss_latency::total 16704.232151 # average overall miss latency
470system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency
471system.cpu.dcache.overall_avg_miss_latency::total 16704.232151 # average overall miss latency

472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
473system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
476system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
477system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
478system.cpu.dcache.fast_writes 0 # number of fast writes performed
479system.cpu.dcache.cache_copies 0 # number of cache copies performed
480system.cpu.dcache.writebacks::writebacks 1535863 # number of writebacks
481system.cpu.dcache.writebacks::total 1535863 # number of writebacks
482system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306270 # number of ReadReq MSHR misses
483system.cpu.dcache.ReadReq_mshr_misses::total 1306270 # number of ReadReq MSHR misses
484system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314797 # number of WriteReq MSHR misses
485system.cpu.dcache.WriteReq_mshr_misses::total 314797 # number of WriteReq MSHR misses
486system.cpu.dcache.demand_mshr_misses::cpu.data 1621067 # number of demand (read+write) MSHR misses
487system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses
488system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses
489system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses

490system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562696500 # number of ReadReq MSHR miss cycles
491system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562696500 # number of ReadReq MSHR miss cycles

490system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562697000 # number of ReadReq MSHR miss cycles
491system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562697000 # number of ReadReq MSHR miss cycles

492system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles
493system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles

494system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545000 # number of demand (read+write) MSHR miss cycles
495system.cpu.dcache.demand_mshr_miss_latency::total 23836545000 # number of demand (read+write) MSHR miss cycles
496system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545000 # number of overall MSHR miss cycles
497system.cpu.dcache.overall_mshr_miss_latency::total 23836545000 # number of overall MSHR miss cycles

494system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545500 # number of demand (read+write) MSHR miss cycles
495system.cpu.dcache.demand_mshr_miss_latency::total 23836545500 # number of demand (read+write) MSHR miss cycles
496system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545500 # number of overall MSHR miss cycles
497system.cpu.dcache.overall_mshr_miss_latency::total 23836545500 # number of overall MSHR miss cycles

498system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles
499system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles

500system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469435000 # number of WriteReq MSHR uncacheable cycles
501system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469435000 # number of WriteReq MSHR uncacheable cycles
502system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616389000 # number of overall MSHR uncacheable cycles
503system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616389000 # number of overall MSHR uncacheable cycles

500system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469434500 # number of WriteReq MSHR uncacheable cycles
501system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469434500 # number of WriteReq MSHR uncacheable cycles
502system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616388500 # number of overall MSHR uncacheable cycles
503system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616388500 # number of overall MSHR uncacheable cycles

504system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses
505system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses
506system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses
507system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037687 # mshr miss rate for WriteReq accesses
508system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for demand accesses
509system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses
510system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses
511system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses

512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843616 # average ReadReq mshr miss latency
513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843616 # average ReadReq mshr miss latency

512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843999 # average ReadReq mshr miss latency
513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843999 # average ReadReq mshr miss latency

514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency
515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency

516system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency
517system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency
518system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency
519system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency

516system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency
517system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency
518system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency
519system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency

520system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
521system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
522system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
523system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
524system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
525system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
526system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
527system.cpu.l2cache.replacements 86829 # number of replacements

--- 139 unchanged lines hidden (view full) ---

667system.cpu.l2cache.demand_mshr_misses::cpu.inst 12922 # number of demand (read+write) MSHR misses
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674system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles

675system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles
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678system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles
679system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles
680system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles
681system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles
682system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles

683system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles
684system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles
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683system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329500 # number of demand (read+write) MSHR miss cycles
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686system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles

687system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles
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687system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329500 # number of overall MSHR miss cycles
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690system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles
691system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles
692system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles
693system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305699000 # number of WriteReq MSHR uncacheable cycles
694system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893260000 # number of overall MSHR uncacheable cycles
695system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893260000 # number of overall MSHR uncacheable cycles
696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for ReadReq accesses
697system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for ReadReq accesses

--- 7 unchanged lines hidden (view full) ---

705system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for demand accesses
706system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for demand accesses
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708system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for overall accesses
709system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for overall accesses
710system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses
711system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses
712system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency

713system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency
714system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency
715system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency

713system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.785637 # average ReadReq mshr miss latency
714system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40516.325519 # average ReadReq mshr miss latency
715system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40365.103850 # average ReadReq mshr miss latency

716system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency
717system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency
718system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency
719system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency
720system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency

721system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency
722system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency
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721system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency
722system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency
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724system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency

725system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency
726system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency
727system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency

725system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency
726system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency
727system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency