1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 5.196023 # Number of seconds simulated
4sim_ticks 5196022575000 # Number of ticks simulated
5final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 5.187896 # Number of seconds simulated
4sim_ticks 5187896410000 # Number of ticks simulated
5final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1315892 # Simulator instruction rate (inst/s)
8host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 53344387183 # Simulator tick rate (ticks/s)
10host_mem_usage 354072 # Number of bytes of host memory used
11host_seconds 97.41 # Real time elapsed on the host
12sim_insts 128174734 # Number of instructions simulated
13sim_ops 247089109 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2880320 # Number of bytes read from this memory
| 7host_inst_rate 834857 # Simulator instruction rate (inst/s)
8host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 33766110220 # Simulator tick rate (ticks/s)
10host_mem_usage 354356 # Number of bytes of host memory used
11host_seconds 153.64 # Real time elapsed on the host
12sim_insts 128269216 # Number of instructions simulated
13sim_ops 247270559 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory
|
15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
| 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
16system.physmem.bytes_read::cpu.inst 824192 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8956288 # Number of bytes read from this memory
18system.physmem.bytes_read::total 12661120 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 824192 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 824192 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 8085888 # Number of bytes written to this memory
22system.physmem.bytes_written::total 8085888 # Number of bytes written to this memory
23system.physmem.num_reads::pc.south_bridge.ide 45005 # Number of read requests responded to by this memory
| 16system.physmem.bytes_read::cpu.inst 826944 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8996288 # Number of bytes read from this memory
18system.physmem.bytes_read::total 12690880 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 826944 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 826944 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 8107200 # Number of bytes written to this memory
22system.physmem.bytes_written::total 8107200 # Number of bytes written to this memory
23system.physmem.num_reads::pc.south_bridge.ide 44802 # Number of read requests responded to by this memory
|
24system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
| 24system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
25system.physmem.num_reads::cpu.inst 12878 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 139942 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 197830 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 126342 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 126342 # Number of write requests responded to by this memory
30system.physmem.bw_read::pc.south_bridge.ide 554332 # Total read bandwidth from this memory (bytes/s)
| 25system.physmem.num_reads::cpu.inst 12921 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 140567 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 198295 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 126675 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 126675 # Number of write requests responded to by this memory
30system.physmem.bw_read::pc.south_bridge.ide 552696 # Total read bandwidth from this memory (bytes/s)
|
31system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
| 31system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
|
32system.physmem.bw_read::cpu.inst 158620 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.data 1723682 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 2436695 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 158620 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 158620 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s)
| 32system.physmem.bw_read::cpu.inst 159399 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.data 1734092 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 2446248 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 159399 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 159399 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 1562714 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 1562714 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 1562714 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::pc.south_bridge.ide 552696 # Total bandwidth to/from this memory (bytes/s)
|
41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
| 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
|
42system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s)
45system.cpu.l2cache.replacements 86330 # number of replacements
46system.cpu.l2cache.tagsinuse 64759.737076 # Cycle average of tags in use
47system.cpu.l2cache.total_refs 3491284 # Total number of references to valid blocks.
48system.cpu.l2cache.sampled_refs 151054 # Sample count of references to valid blocks.
49system.cpu.l2cache.avg_refs 23.112821 # Average number of references to valid blocks.
50system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
51system.cpu.l2cache.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor
52system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor
53system.cpu.l2cache.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor
54system.cpu.l2cache.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor
55system.cpu.l2cache.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy
56system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
57system.cpu.l2cache.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy
58system.cpu.l2cache.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy
59system.cpu.l2cache.occ_percent::total 0.988155 # Average percentage of cache occupancy
60system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits
61system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits
62system.cpu.l2cache.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits
63system.cpu.l2cache.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits
64system.cpu.l2cache.ReadReq_hits::total 2068208 # number of ReadReq hits
65system.cpu.l2cache.Writeback_hits::writebacks 1543462 # number of Writeback hits
66system.cpu.l2cache.Writeback_hits::total 1543462 # number of Writeback hits
67system.cpu.l2cache.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits
68system.cpu.l2cache.UpgradeReq_hits::total 302 # number of UpgradeReq hits
69system.cpu.l2cache.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits
70system.cpu.l2cache.ReadExReq_hits::total 200678 # number of ReadExReq hits
71system.cpu.l2cache.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits
72system.cpu.l2cache.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits
73system.cpu.l2cache.demand_hits::cpu.inst 778172 # number of demand (read+write) hits
74system.cpu.l2cache.demand_hits::cpu.data 1481001 # number of demand (read+write) hits
75system.cpu.l2cache.demand_hits::total 2268886 # number of demand (read+write) hits
76system.cpu.l2cache.overall_hits::cpu.dtb.walker 6719 # number of overall hits
77system.cpu.l2cache.overall_hits::cpu.itb.walker 2994 # number of overall hits
78system.cpu.l2cache.overall_hits::cpu.inst 778172 # number of overall hits
79system.cpu.l2cache.overall_hits::cpu.data 1481001 # number of overall hits
80system.cpu.l2cache.overall_hits::total 2268886 # number of overall hits
81system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
82system.cpu.l2cache.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses
83system.cpu.l2cache.ReadReq_misses::cpu.data 28353 # number of ReadReq misses
84system.cpu.l2cache.ReadReq_misses::total 41237 # number of ReadReq misses
85system.cpu.l2cache.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses
86system.cpu.l2cache.UpgradeReq_misses::total 1338 # number of UpgradeReq misses
87system.cpu.l2cache.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses
88system.cpu.l2cache.ReadExReq_misses::total 112514 # number of ReadExReq misses
89system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
90system.cpu.l2cache.demand_misses::cpu.inst 12879 # number of demand (read+write) misses
91system.cpu.l2cache.demand_misses::cpu.data 140867 # number of demand (read+write) misses
92system.cpu.l2cache.demand_misses::total 153751 # number of demand (read+write) misses
93system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
94system.cpu.l2cache.overall_misses::cpu.inst 12879 # number of overall misses
95system.cpu.l2cache.overall_misses::cpu.data 140867 # number of overall misses
96system.cpu.l2cache.overall_misses::total 153751 # number of overall misses
97system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles
98system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles
99system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles
100system.cpu.l2cache.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles
101system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles
102system.cpu.l2cache.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles
103system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles
104system.cpu.l2cache.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles
105system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles
106system.cpu.l2cache.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles
107system.cpu.l2cache.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles
108system.cpu.l2cache.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles
109system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles
110system.cpu.l2cache.overall_miss_latency::cpu.inst 670083000 # number of overall miss cycles
111system.cpu.l2cache.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles
112system.cpu.l2cache.overall_miss_latency::total 8011639500 # number of overall miss cycles
113system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses)
114system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses)
115system.cpu.l2cache.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses)
116system.cpu.l2cache.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses)
117system.cpu.l2cache.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses)
118system.cpu.l2cache.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses)
119system.cpu.l2cache.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses)
120system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses)
121system.cpu.l2cache.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses)
122system.cpu.l2cache.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses)
123system.cpu.l2cache.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses)
124system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses
125system.cpu.l2cache.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses
126system.cpu.l2cache.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses
127system.cpu.l2cache.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses
128system.cpu.l2cache.demand_accesses::total 2422637 # number of demand (read+write) accesses
129system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses
130system.cpu.l2cache.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses
131system.cpu.l2cache.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses
132system.cpu.l2cache.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses
133system.cpu.l2cache.overall_accesses::total 2422637 # number of overall (read+write) accesses
134system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses
135system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses
136system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses
137system.cpu.l2cache.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses
138system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses
139system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses
140system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses
141system.cpu.l2cache.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses
142system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses
143system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses
144system.cpu.l2cache.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses
145system.cpu.l2cache.demand_miss_rate::total 0.063464 # miss rate for demand accesses
146system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses
147system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses
148system.cpu.l2cache.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses
149system.cpu.l2cache.overall_miss_rate::total 0.063464 # miss rate for overall accesses
150system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
151system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency
152system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency
153system.cpu.l2cache.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency
154system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency
155system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency
156system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency
157system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency
158system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
159system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency
160system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency
161system.cpu.l2cache.demand_avg_miss_latency::total 52107.885477 # average overall miss latency
162system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
163system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency
164system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency
165system.cpu.l2cache.overall_avg_miss_latency::total 52107.885477 # average overall miss latency
166system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
167system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
168system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
169system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
170system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
171system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
172system.cpu.l2cache.fast_writes 0 # number of fast writes performed
173system.cpu.l2cache.cache_copies 0 # number of cache copies performed
174system.cpu.l2cache.writebacks::writebacks 79675 # number of writebacks
175system.cpu.l2cache.writebacks::total 79675 # number of writebacks
176system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
177system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses
178system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses
179system.cpu.l2cache.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses
180system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses
181system.cpu.l2cache.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses
182system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses
183system.cpu.l2cache.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses
184system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
185system.cpu.l2cache.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses
186system.cpu.l2cache.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses
187system.cpu.l2cache.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses
188system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
189system.cpu.l2cache.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses
190system.cpu.l2cache.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses
191system.cpu.l2cache.overall_mshr_misses::total 153751 # number of overall MSHR misses
192system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles
193system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles
194system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles
195system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles
196system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles
197system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles
198system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles
199system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles
200system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
201system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles
202system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles
203system.cpu.l2cache.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles
204system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
205system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles
206system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles
207system.cpu.l2cache.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles
208system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles
209system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles
210system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles
211system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles
212system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles
213system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles
214system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses
215system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses
216system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses
217system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses
218system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses
219system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses
220system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses
221system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses
222system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses
223system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses
224system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses
225system.cpu.l2cache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses
226system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses
227system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses
228system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses
229system.cpu.l2cache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses
230system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
231system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency
232system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency
233system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency
234system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency
235system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency
236system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency
237system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency
238system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
239system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency
240system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency
241system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency
242system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
243system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency
244system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency
245system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency
246system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
247system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
248system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
249system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
250system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
251system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
252system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 42system.physmem.bw_total::cpu.inst 159399 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::cpu.data 1734092 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::total 4008962 # Total bandwidth to/from this memory (bytes/s)
|
253system.iocache.replacements 47503 # number of replacements
| 45system.iocache.replacements 47503 # number of replacements
|
254system.iocache.tagsinuse 0.108744 # Cycle average of tags in use
| 46system.iocache.tagsinuse 0.106662 # Cycle average of tags in use
|
255system.iocache.total_refs 0 # Total number of references to valid blocks.
256system.iocache.sampled_refs 47519 # Sample count of references to valid blocks.
257system.iocache.avg_refs 0 # Average number of references to valid blocks.
| 47system.iocache.total_refs 0 # Total number of references to valid blocks.
48system.iocache.sampled_refs 47519 # Sample count of references to valid blocks.
49system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
258system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit.
259system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor
260system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy
261system.iocache.occ_percent::total 0.006796 # Average percentage of cache occupancy
| 50system.iocache.warmup_cycle 5044925516000 # Cycle when the warmup percentage was hit.
51system.iocache.occ_blocks::pc.south_bridge.ide 0.106662 # Average occupied blocks per requestor
52system.iocache.occ_percent::pc.south_bridge.ide 0.006666 # Average percentage of cache occupancy
53system.iocache.occ_percent::total 0.006666 # Average percentage of cache occupancy
|
262system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses
263system.iocache.ReadReq_misses::total 838 # number of ReadReq misses
264system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
265system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
266system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses
267system.iocache.demand_misses::total 47558 # number of demand (read+write) misses
268system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses
269system.iocache.overall_misses::total 47558 # number of overall misses
| 54system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses
55system.iocache.ReadReq_misses::total 838 # number of ReadReq misses
56system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
57system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
58system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses
59system.iocache.demand_misses::total 47558 # number of demand (read+write) misses
60system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses
61system.iocache.overall_misses::total 47558 # number of overall misses
|
270system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 129993932 # number of ReadReq miss cycles
271system.iocache.ReadReq_miss_latency::total 129993932 # number of ReadReq miss cycles
272system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10714208160 # number of WriteReq miss cycles
273system.iocache.WriteReq_miss_latency::total 10714208160 # number of WriteReq miss cycles
274system.iocache.demand_miss_latency::pc.south_bridge.ide 10844202092 # number of demand (read+write) miss cycles
275system.iocache.demand_miss_latency::total 10844202092 # number of demand (read+write) miss cycles
276system.iocache.overall_miss_latency::pc.south_bridge.ide 10844202092 # number of overall miss cycles
277system.iocache.overall_miss_latency::total 10844202092 # number of overall miss cycles
| 62system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles
63system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles
64system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles
65system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles
66system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles
67system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles
68system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles
69system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles
|
278system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses)
279system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses)
280system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
281system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
282system.iocache.demand_accesses::pc.south_bridge.ide 47558 # number of demand (read+write) accesses
283system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses
284system.iocache.overall_accesses::pc.south_bridge.ide 47558 # number of overall (read+write) accesses
285system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses
286system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
287system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
288system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
289system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
290system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
291system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
292system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
293system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
| 70system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses)
71system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses)
72system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
73system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
74system.iocache.demand_accesses::pc.south_bridge.ide 47558 # number of demand (read+write) accesses
75system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses
76system.iocache.overall_accesses::pc.south_bridge.ide 47558 # number of overall (read+write) accesses
77system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses
78system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
79system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
80system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
81system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
82system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
83system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
84system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
85system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
294system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155124.023866 # average ReadReq miss latency
295system.iocache.ReadReq_avg_miss_latency::total 155124.023866 # average ReadReq miss latency
296system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229328.085616 # average WriteReq miss latency
297system.iocache.WriteReq_avg_miss_latency::total 229328.085616 # average WriteReq miss latency
298system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency
299system.iocache.demand_avg_miss_latency::total 228020.566298 # average overall miss latency
300system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228020.566298 # average overall miss latency
301system.iocache.overall_avg_miss_latency::total 228020.566298 # average overall miss latency
302system.iocache.blocked_cycles::no_mshrs 89624012 # number of cycles access was blocked
| 86system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency
87system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency
88system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency
89system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency
90system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency
91system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency
92system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency
93system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency
94system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked
|
303system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
| 95system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
304system.iocache.blocked::no_mshrs 10977 # number of cycles access was blocked
| 96system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked
|
305system.iocache.blocked::no_targets 0 # number of cycles access was blocked
| 97system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
306system.iocache.avg_blocked_cycles::no_mshrs 8164.709119 # average number of cycles each access was blocked
| 98system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked
|
307system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
308system.iocache.fast_writes 0 # number of fast writes performed
309system.iocache.cache_copies 0 # number of cache copies performed
310system.iocache.writebacks::writebacks 46667 # number of writebacks
311system.iocache.writebacks::total 46667 # number of writebacks
312system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 838 # number of ReadReq MSHR misses
313system.iocache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses
314system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
315system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
316system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 # number of demand (read+write) MSHR misses
317system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses
318system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses
319system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses
| 99system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
100system.iocache.fast_writes 0 # number of fast writes performed
101system.iocache.cache_copies 0 # number of cache copies performed
102system.iocache.writebacks::writebacks 46667 # number of writebacks
103system.iocache.writebacks::total 46667 # number of writebacks
104system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 838 # number of ReadReq MSHR misses
105system.iocache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses
106system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
107system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
108system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 # number of demand (read+write) MSHR misses
109system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses
110system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses
111system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses
|
320system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86387000 # number of ReadReq MSHR miss cycles
321system.iocache.ReadReq_mshr_miss_latency::total 86387000 # number of ReadReq MSHR miss cycles
322system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8284511992 # number of WriteReq MSHR miss cycles
323system.iocache.WriteReq_mshr_miss_latency::total 8284511992 # number of WriteReq MSHR miss cycles
324system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of demand (read+write) MSHR miss cycles
325system.iocache.demand_mshr_miss_latency::total 8370898992 # number of demand (read+write) MSHR miss cycles
326system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8370898992 # number of overall MSHR miss cycles
327system.iocache.overall_mshr_miss_latency::total 8370898992 # number of overall MSHR miss cycles
| 112system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles
113system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles
114system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8266468944 # number of WriteReq MSHR miss cycles
115system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles
116system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles
117system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles
118system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of overall MSHR miss cycles
119system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles
|
328system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
329system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
330system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
331system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
332system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
333system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
334system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
335system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
| 120system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
121system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
122system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
123system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
124system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
125system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
126system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
127system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
336system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103087.112172 # average ReadReq mshr miss latency
337system.iocache.ReadReq_avg_mshr_miss_latency::total 103087.112172 # average ReadReq mshr miss latency
338system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177322.602568 # average WriteReq mshr miss latency
339system.iocache.WriteReq_avg_mshr_miss_latency::total 177322.602568 # average WriteReq mshr miss latency
340system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency
341system.iocache.demand_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency
342system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176014.529459 # average overall mshr miss latency
343system.iocache.overall_avg_mshr_miss_latency::total 176014.529459 # average overall mshr miss latency
| 128system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency
129system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency
130system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency
131system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency
132system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency
133system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency
134system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency
135system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency
|
344system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
345system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
346system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
347system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
348system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
349system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
350system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
351system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
352system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
353system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
354system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
355system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
356system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
| 136system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
137system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
138system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
139system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
140system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
141system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
142system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
143system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
144system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
145system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
146system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
147system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
148system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
357system.cpu.numCycles 10392045150 # number of cpu cycles simulated
| 149system.cpu.numCycles 10375792820 # number of cpu cycles simulated
|
358system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
359system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 150system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
151system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
360system.cpu.committedInsts 128174734 # Number of instructions committed
361system.cpu.committedOps 247089109 # Number of ops (including micro ops) committed
362system.cpu.num_int_alu_accesses 231827885 # Number of integer alu accesses
| 152system.cpu.committedInsts 128269216 # Number of instructions committed
153system.cpu.committedOps 247270559 # Number of ops (including micro ops) committed
154system.cpu.num_int_alu_accesses 232005526 # Number of integer alu accesses
|
363system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
364system.cpu.num_func_calls 0 # number of times a function call or return occured
| 155system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
156system.cpu.num_func_calls 0 # number of times a function call or return occured
|
365system.cpu.num_conditional_control_insts 23138722 # number of instructions that are conditional controls
366system.cpu.num_int_insts 231827885 # number of integer instructions
| 157system.cpu.num_conditional_control_insts 23152914 # number of instructions that are conditional controls
158system.cpu.num_int_insts 232005526 # number of integer instructions
|
367system.cpu.num_fp_insts 0 # number of float instructions
| 159system.cpu.num_fp_insts 0 # number of float instructions
|
368system.cpu.num_int_register_reads 566609561 # number of times the integer registers were read
369system.cpu.num_int_register_writes 292994515 # number of times the integer registers were written
| 160system.cpu.num_int_register_reads 567048885 # number of times the integer registers were read
161system.cpu.num_int_register_writes 293217624 # number of times the integer registers were written
|
370system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
371system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
| 162system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
163system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
372system.cpu.num_mem_refs 22210252 # number of memory refs
373system.cpu.num_load_insts 13855140 # Number of load instructions
374system.cpu.num_store_insts 8355112 # Number of store instructions
375system.cpu.num_idle_cycles 9776628704.958118 # Number of idle cycles
376system.cpu.num_busy_cycles 615416445.041882 # Number of busy cycles
377system.cpu.not_idle_fraction 0.059220 # Percentage of non-idle cycles
378system.cpu.idle_fraction 0.940780 # Percentage of idle cycles
| 164system.cpu.num_mem_refs 22238817 # number of memory refs
165system.cpu.num_load_insts 13875768 # Number of load instructions
166system.cpu.num_store_insts 8363049 # Number of store instructions
167system.cpu.num_idle_cycles 9774979498.742117 # Number of idle cycles
168system.cpu.num_busy_cycles 600813321.257884 # Number of busy cycles
169system.cpu.not_idle_fraction 0.057905 # Percentage of non-idle cycles
170system.cpu.idle_fraction 0.942095 # Percentage of idle cycles
|
379system.cpu.kern.inst.arm 0 # number of arm instructions executed
380system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
| 171system.cpu.kern.inst.arm 0 # number of arm instructions executed
172system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
381system.cpu.icache.replacements 790545 # number of replacements
382system.cpu.icache.tagsinuse 510.338891 # Cycle average of tags in use
383system.cpu.icache.total_refs 144363546 # Total number of references to valid blocks.
384system.cpu.icache.sampled_refs 791057 # Sample count of references to valid blocks.
385system.cpu.icache.avg_refs 182.494493 # Average number of references to valid blocks.
386system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit.
387system.cpu.icache.occ_blocks::cpu.inst 510.338891 # Average occupied blocks per requestor
388system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy
389system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy
390system.cpu.icache.ReadReq_hits::cpu.inst 144363546 # number of ReadReq hits
391system.cpu.icache.ReadReq_hits::total 144363546 # number of ReadReq hits
392system.cpu.icache.demand_hits::cpu.inst 144363546 # number of demand (read+write) hits
393system.cpu.icache.demand_hits::total 144363546 # number of demand (read+write) hits
394system.cpu.icache.overall_hits::cpu.inst 144363546 # number of overall hits
395system.cpu.icache.overall_hits::total 144363546 # number of overall hits
396system.cpu.icache.ReadReq_misses::cpu.inst 791064 # number of ReadReq misses
397system.cpu.icache.ReadReq_misses::total 791064 # number of ReadReq misses
398system.cpu.icache.demand_misses::cpu.inst 791064 # number of demand (read+write) misses
399system.cpu.icache.demand_misses::total 791064 # number of demand (read+write) misses
400system.cpu.icache.overall_misses::cpu.inst 791064 # number of overall misses
401system.cpu.icache.overall_misses::total 791064 # number of overall misses
402system.cpu.icache.ReadReq_miss_latency::cpu.inst 11792673000 # number of ReadReq miss cycles
403system.cpu.icache.ReadReq_miss_latency::total 11792673000 # number of ReadReq miss cycles
404system.cpu.icache.demand_miss_latency::cpu.inst 11792673000 # number of demand (read+write) miss cycles
405system.cpu.icache.demand_miss_latency::total 11792673000 # number of demand (read+write) miss cycles
406system.cpu.icache.overall_miss_latency::cpu.inst 11792673000 # number of overall miss cycles
407system.cpu.icache.overall_miss_latency::total 11792673000 # number of overall miss cycles
408system.cpu.icache.ReadReq_accesses::cpu.inst 145154610 # number of ReadReq accesses(hits+misses)
409system.cpu.icache.ReadReq_accesses::total 145154610 # number of ReadReq accesses(hits+misses)
410system.cpu.icache.demand_accesses::cpu.inst 145154610 # number of demand (read+write) accesses
411system.cpu.icache.demand_accesses::total 145154610 # number of demand (read+write) accesses
412system.cpu.icache.overall_accesses::cpu.inst 145154610 # number of overall (read+write) accesses
413system.cpu.icache.overall_accesses::total 145154610 # number of overall (read+write) accesses
414system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses
415system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses
416system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses
417system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses
418system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses
419system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses
420system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14907.356421 # average ReadReq miss latency
421system.cpu.icache.ReadReq_avg_miss_latency::total 14907.356421 # average ReadReq miss latency
422system.cpu.icache.demand_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency
423system.cpu.icache.demand_avg_miss_latency::total 14907.356421 # average overall miss latency
424system.cpu.icache.overall_avg_miss_latency::cpu.inst 14907.356421 # average overall miss latency
425system.cpu.icache.overall_avg_miss_latency::total 14907.356421 # average overall miss latency
| 173system.cpu.icache.replacements 793131 # number of replacements
174system.cpu.icache.tagsinuse 510.350730 # Cycle average of tags in use
175system.cpu.icache.total_refs 144484487 # Total number of references to valid blocks.
176system.cpu.icache.sampled_refs 793643 # Sample count of references to valid blocks.
177system.cpu.icache.avg_refs 182.052241 # Average number of references to valid blocks.
178system.cpu.icache.warmup_cycle 160314386000 # Cycle when the warmup percentage was hit.
179system.cpu.icache.occ_blocks::cpu.inst 510.350730 # Average occupied blocks per requestor
180system.cpu.icache.occ_percent::cpu.inst 0.996779 # Average percentage of cache occupancy
181system.cpu.icache.occ_percent::total 0.996779 # Average percentage of cache occupancy
182system.cpu.icache.ReadReq_hits::cpu.inst 144484487 # number of ReadReq hits
183system.cpu.icache.ReadReq_hits::total 144484487 # number of ReadReq hits
184system.cpu.icache.demand_hits::cpu.inst 144484487 # number of demand (read+write) hits
185system.cpu.icache.demand_hits::total 144484487 # number of demand (read+write) hits
186system.cpu.icache.overall_hits::cpu.inst 144484487 # number of overall hits
187system.cpu.icache.overall_hits::total 144484487 # number of overall hits
188system.cpu.icache.ReadReq_misses::cpu.inst 793650 # number of ReadReq misses
189system.cpu.icache.ReadReq_misses::total 793650 # number of ReadReq misses
190system.cpu.icache.demand_misses::cpu.inst 793650 # number of demand (read+write) misses
191system.cpu.icache.demand_misses::total 793650 # number of demand (read+write) misses
192system.cpu.icache.overall_misses::cpu.inst 793650 # number of overall misses
193system.cpu.icache.overall_misses::total 793650 # number of overall misses
194system.cpu.icache.ReadReq_miss_latency::cpu.inst 10860662000 # number of ReadReq miss cycles
195system.cpu.icache.ReadReq_miss_latency::total 10860662000 # number of ReadReq miss cycles
196system.cpu.icache.demand_miss_latency::cpu.inst 10860662000 # number of demand (read+write) miss cycles
197system.cpu.icache.demand_miss_latency::total 10860662000 # number of demand (read+write) miss cycles
198system.cpu.icache.overall_miss_latency::cpu.inst 10860662000 # number of overall miss cycles
199system.cpu.icache.overall_miss_latency::total 10860662000 # number of overall miss cycles
200system.cpu.icache.ReadReq_accesses::cpu.inst 145278137 # number of ReadReq accesses(hits+misses)
201system.cpu.icache.ReadReq_accesses::total 145278137 # number of ReadReq accesses(hits+misses)
202system.cpu.icache.demand_accesses::cpu.inst 145278137 # number of demand (read+write) accesses
203system.cpu.icache.demand_accesses::total 145278137 # number of demand (read+write) accesses
204system.cpu.icache.overall_accesses::cpu.inst 145278137 # number of overall (read+write) accesses
205system.cpu.icache.overall_accesses::total 145278137 # number of overall (read+write) accesses
206system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005463 # miss rate for ReadReq accesses
207system.cpu.icache.ReadReq_miss_rate::total 0.005463 # miss rate for ReadReq accesses
208system.cpu.icache.demand_miss_rate::cpu.inst 0.005463 # miss rate for demand accesses
209system.cpu.icache.demand_miss_rate::total 0.005463 # miss rate for demand accesses
210system.cpu.icache.overall_miss_rate::cpu.inst 0.005463 # miss rate for overall accesses
211system.cpu.icache.overall_miss_rate::total 0.005463 # miss rate for overall accesses
212system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13684.447804 # average ReadReq miss latency
213system.cpu.icache.ReadReq_avg_miss_latency::total 13684.447804 # average ReadReq miss latency
214system.cpu.icache.demand_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency
215system.cpu.icache.demand_avg_miss_latency::total 13684.447804 # average overall miss latency
216system.cpu.icache.overall_avg_miss_latency::cpu.inst 13684.447804 # average overall miss latency
217system.cpu.icache.overall_avg_miss_latency::total 13684.447804 # average overall miss latency
|
426system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
427system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
428system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
429system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
430system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
431system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
432system.cpu.icache.fast_writes 0 # number of fast writes performed
433system.cpu.icache.cache_copies 0 # number of cache copies performed
| 218system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
219system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
220system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
221system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
222system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
223system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
224system.cpu.icache.fast_writes 0 # number of fast writes performed
225system.cpu.icache.cache_copies 0 # number of cache copies performed
|
434system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791064 # number of ReadReq MSHR misses
435system.cpu.icache.ReadReq_mshr_misses::total 791064 # number of ReadReq MSHR misses
436system.cpu.icache.demand_mshr_misses::cpu.inst 791064 # number of demand (read+write) MSHR misses
437system.cpu.icache.demand_mshr_misses::total 791064 # number of demand (read+write) MSHR misses
438system.cpu.icache.overall_mshr_misses::cpu.inst 791064 # number of overall MSHR misses
439system.cpu.icache.overall_mshr_misses::total 791064 # number of overall MSHR misses
440system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9418462000 # number of ReadReq MSHR miss cycles
441system.cpu.icache.ReadReq_mshr_miss_latency::total 9418462000 # number of ReadReq MSHR miss cycles
442system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9418462000 # number of demand (read+write) MSHR miss cycles
443system.cpu.icache.demand_mshr_miss_latency::total 9418462000 # number of demand (read+write) MSHR miss cycles
444system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9418462000 # number of overall MSHR miss cycles
445system.cpu.icache.overall_mshr_miss_latency::total 9418462000 # number of overall MSHR miss cycles
446system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses
447system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses
448system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses
449system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses
450system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses
451system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses
452system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11906.068283 # average ReadReq mshr miss latency
453system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11906.068283 # average ReadReq mshr miss latency
454system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency
455system.cpu.icache.demand_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency
456system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11906.068283 # average overall mshr miss latency
457system.cpu.icache.overall_avg_mshr_miss_latency::total 11906.068283 # average overall mshr miss latency
| 226system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793650 # number of ReadReq MSHR misses
227system.cpu.icache.ReadReq_mshr_misses::total 793650 # number of ReadReq MSHR misses
228system.cpu.icache.demand_mshr_misses::cpu.inst 793650 # number of demand (read+write) MSHR misses
229system.cpu.icache.demand_mshr_misses::total 793650 # number of demand (read+write) MSHR misses
230system.cpu.icache.overall_mshr_misses::cpu.inst 793650 # number of overall MSHR misses
231system.cpu.icache.overall_mshr_misses::total 793650 # number of overall MSHR misses
232system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9273362000 # number of ReadReq MSHR miss cycles
233system.cpu.icache.ReadReq_mshr_miss_latency::total 9273362000 # number of ReadReq MSHR miss cycles
234system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9273362000 # number of demand (read+write) MSHR miss cycles
235system.cpu.icache.demand_mshr_miss_latency::total 9273362000 # number of demand (read+write) MSHR miss cycles
236system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9273362000 # number of overall MSHR miss cycles
237system.cpu.icache.overall_mshr_miss_latency::total 9273362000 # number of overall MSHR miss cycles
238system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for ReadReq accesses
239system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005463 # mshr miss rate for ReadReq accesses
240system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for demand accesses
241system.cpu.icache.demand_mshr_miss_rate::total 0.005463 # mshr miss rate for demand accesses
242system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005463 # mshr miss rate for overall accesses
243system.cpu.icache.overall_mshr_miss_rate::total 0.005463 # mshr miss rate for overall accesses
244system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.447804 # average ReadReq mshr miss latency
245system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.447804 # average ReadReq mshr miss latency
246system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency
247system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency
248system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.447804 # average overall mshr miss latency
249system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.447804 # average overall mshr miss latency
|
458system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 250system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
459system.cpu.itb_walker_cache.replacements 3550 # number of replacements
460system.cpu.itb_walker_cache.tagsinuse 3.065778 # Cycle average of tags in use
461system.cpu.itb_walker_cache.total_refs 7809 # Total number of references to valid blocks.
462system.cpu.itb_walker_cache.sampled_refs 3562 # Sample count of references to valid blocks.
463system.cpu.itb_walker_cache.avg_refs 2.192308 # Average number of references to valid blocks.
464system.cpu.itb_walker_cache.warmup_cycle 5171078849000 # Cycle when the warmup percentage was hit.
465system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.065778 # Average occupied blocks per requestor
466system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191611 # Average percentage of cache occupancy
467system.cpu.itb_walker_cache.occ_percent::total 0.191611 # Average percentage of cache occupancy
468system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7809 # number of ReadReq hits
469system.cpu.itb_walker_cache.ReadReq_hits::total 7809 # number of ReadReq hits
| 251system.cpu.itb_walker_cache.replacements 3599 # number of replacements
252system.cpu.itb_walker_cache.tagsinuse 3.063919 # Cycle average of tags in use
253system.cpu.itb_walker_cache.total_refs 7874 # Total number of references to valid blocks.
254system.cpu.itb_walker_cache.sampled_refs 3610 # Sample count of references to valid blocks.
255system.cpu.itb_walker_cache.avg_refs 2.181163 # Average number of references to valid blocks.
256system.cpu.itb_walker_cache.warmup_cycle 5162043257000 # Cycle when the warmup percentage was hit.
257system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.063919 # Average occupied blocks per requestor
258system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191495 # Average percentage of cache occupancy
259system.cpu.itb_walker_cache.occ_percent::total 0.191495 # Average percentage of cache occupancy
260system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7876 # number of ReadReq hits
261system.cpu.itb_walker_cache.ReadReq_hits::total 7876 # number of ReadReq hits
|
470system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
471system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
| 262system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
263system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
472system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7811 # number of demand (read+write) hits
473system.cpu.itb_walker_cache.demand_hits::total 7811 # number of demand (read+write) hits
474system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7811 # number of overall hits
475system.cpu.itb_walker_cache.overall_hits::total 7811 # number of overall hits
476system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4415 # number of ReadReq misses
477system.cpu.itb_walker_cache.ReadReq_misses::total 4415 # number of ReadReq misses
478system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4415 # number of demand (read+write) misses
479system.cpu.itb_walker_cache.demand_misses::total 4415 # number of demand (read+write) misses
480system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4415 # number of overall misses
481system.cpu.itb_walker_cache.overall_misses::total 4415 # number of overall misses
482system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 53239000 # number of ReadReq miss cycles
483system.cpu.itb_walker_cache.ReadReq_miss_latency::total 53239000 # number of ReadReq miss cycles
484system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 53239000 # number of demand (read+write) miss cycles
485system.cpu.itb_walker_cache.demand_miss_latency::total 53239000 # number of demand (read+write) miss cycles
486system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 53239000 # number of overall miss cycles
487system.cpu.itb_walker_cache.overall_miss_latency::total 53239000 # number of overall miss cycles
488system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12224 # number of ReadReq accesses(hits+misses)
489system.cpu.itb_walker_cache.ReadReq_accesses::total 12224 # number of ReadReq accesses(hits+misses)
| 264system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7878 # number of demand (read+write) hits
265system.cpu.itb_walker_cache.demand_hits::total 7878 # number of demand (read+write) hits
266system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7878 # number of overall hits
267system.cpu.itb_walker_cache.overall_hits::total 7878 # number of overall hits
268system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses
269system.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses
270system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses
271system.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses
272system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses
273system.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses
274system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43455000 # number of ReadReq miss cycles
275system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43455000 # number of ReadReq miss cycles
276system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43455000 # number of demand (read+write) miss cycles
277system.cpu.itb_walker_cache.demand_miss_latency::total 43455000 # number of demand (read+write) miss cycles
278system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43455000 # number of overall miss cycles
279system.cpu.itb_walker_cache.overall_miss_latency::total 43455000 # number of overall miss cycles
280system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12331 # number of ReadReq accesses(hits+misses)
281system.cpu.itb_walker_cache.ReadReq_accesses::total 12331 # number of ReadReq accesses(hits+misses)
|
490system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
491system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
| 282system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
283system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
492system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12226 # number of demand (read+write) accesses
493system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses
494system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses
495system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses
496system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361175 # miss rate for ReadReq accesses
497system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361175 # miss rate for ReadReq accesses
498system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361116 # miss rate for demand accesses
499system.cpu.itb_walker_cache.demand_miss_rate::total 0.361116 # miss rate for demand accesses
500system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361116 # miss rate for overall accesses
501system.cpu.itb_walker_cache.overall_miss_rate::total 0.361116 # miss rate for overall accesses
502system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12058.663647 # average ReadReq miss latency
503system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12058.663647 # average ReadReq miss latency
504system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency
505system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12058.663647 # average overall miss latency
506system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12058.663647 # average overall miss latency
507system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12058.663647 # average overall miss latency
| 284system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12333 # number of demand (read+write) accesses
285system.cpu.itb_walker_cache.demand_accesses::total 12333 # number of demand (read+write) accesses
286system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12333 # number of overall (read+write) accesses
287system.cpu.itb_walker_cache.overall_accesses::total 12333 # number of overall (read+write) accesses
288system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.361285 # miss rate for ReadReq accesses
289system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.361285 # miss rate for ReadReq accesses
290system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.361226 # miss rate for demand accesses
291system.cpu.itb_walker_cache.demand_miss_rate::total 0.361226 # miss rate for demand accesses
292system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.361226 # miss rate for overall accesses
293system.cpu.itb_walker_cache.overall_miss_rate::total 0.361226 # miss rate for overall accesses
294system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9754.208754 # average ReadReq miss latency
295system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9754.208754 # average ReadReq miss latency
296system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency
297system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9754.208754 # average overall miss latency
298system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9754.208754 # average overall miss latency
299system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9754.208754 # average overall miss latency
|
508system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
509system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
510system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
511system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
512system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
513system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
514system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
515system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
| 300system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
301system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
302system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
303system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
304system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
305system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
306system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
307system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
516system.cpu.itb_walker_cache.writebacks::writebacks 830 # number of writebacks
517system.cpu.itb_walker_cache.writebacks::total 830 # number of writebacks
518system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4415 # number of ReadReq MSHR misses
519system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4415 # number of ReadReq MSHR misses
520system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4415 # number of demand (read+write) MSHR misses
521system.cpu.itb_walker_cache.demand_mshr_misses::total 4415 # number of demand (read+write) MSHR misses
522system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4415 # number of overall MSHR misses
523system.cpu.itb_walker_cache.overall_mshr_misses::total 4415 # number of overall MSHR misses
524system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39994000 # number of ReadReq MSHR miss cycles
525system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39994000 # number of ReadReq MSHR miss cycles
526system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39994000 # number of demand (read+write) MSHR miss cycles
527system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39994000 # number of demand (read+write) MSHR miss cycles
528system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39994000 # number of overall MSHR miss cycles
529system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39994000 # number of overall MSHR miss cycles
530system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361175 # mshr miss rate for ReadReq accesses
531system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361175 # mshr miss rate for ReadReq accesses
532system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for demand accesses
533system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361116 # mshr miss rate for demand accesses
534system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361116 # mshr miss rate for overall accesses
535system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361116 # mshr miss rate for overall accesses
536system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average ReadReq mshr miss latency
537system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9058.663647 # average ReadReq mshr miss latency
538system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency
539system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency
540system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9058.663647 # average overall mshr miss latency
541system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9058.663647 # average overall mshr miss latency
| 308system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks
309system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks
310system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4455 # number of ReadReq MSHR misses
311system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4455 # number of ReadReq MSHR misses
312system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4455 # number of demand (read+write) MSHR misses
313system.cpu.itb_walker_cache.demand_mshr_misses::total 4455 # number of demand (read+write) MSHR misses
314system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4455 # number of overall MSHR misses
315system.cpu.itb_walker_cache.overall_mshr_misses::total 4455 # number of overall MSHR misses
316system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34545000 # number of ReadReq MSHR miss cycles
317system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34545000 # number of ReadReq MSHR miss cycles
318system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34545000 # number of demand (read+write) MSHR miss cycles
319system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34545000 # number of demand (read+write) MSHR miss cycles
320system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34545000 # number of overall MSHR miss cycles
321system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34545000 # number of overall MSHR miss cycles
322system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.361285 # mshr miss rate for ReadReq accesses
323system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.361285 # mshr miss rate for ReadReq accesses
324system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for demand accesses
325system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.361226 # mshr miss rate for demand accesses
326system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.361226 # mshr miss rate for overall accesses
327system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.361226 # mshr miss rate for overall accesses
328system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average ReadReq mshr miss latency
329system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7754.208754 # average ReadReq mshr miss latency
330system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency
331system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency
332system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7754.208754 # average overall mshr miss latency
333system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7754.208754 # average overall mshr miss latency
|
542system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 334system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
543system.cpu.dtb_walker_cache.replacements 7810 # number of replacements
544system.cpu.dtb_walker_cache.tagsinuse 5.052392 # Cycle average of tags in use
545system.cpu.dtb_walker_cache.total_refs 12921 # Total number of references to valid blocks.
546system.cpu.dtb_walker_cache.sampled_refs 7826 # Sample count of references to valid blocks.
547system.cpu.dtb_walker_cache.avg_refs 1.651035 # Average number of references to valid blocks.
548system.cpu.dtb_walker_cache.warmup_cycle 5166488673000 # Cycle when the warmup percentage was hit.
549system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052392 # Average occupied blocks per requestor
550system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315774 # Average percentage of cache occupancy
551system.cpu.dtb_walker_cache.occ_percent::total 0.315774 # Average percentage of cache occupancy
552system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12921 # number of ReadReq hits
553system.cpu.dtb_walker_cache.ReadReq_hits::total 12921 # number of ReadReq hits
554system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12921 # number of demand (read+write) hits
555system.cpu.dtb_walker_cache.demand_hits::total 12921 # number of demand (read+write) hits
556system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12921 # number of overall hits
557system.cpu.dtb_walker_cache.overall_hits::total 12921 # number of overall hits
558system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9010 # number of ReadReq misses
559system.cpu.dtb_walker_cache.ReadReq_misses::total 9010 # number of ReadReq misses
560system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9010 # number of demand (read+write) misses
561system.cpu.dtb_walker_cache.demand_misses::total 9010 # number of demand (read+write) misses
562system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9010 # number of overall misses
563system.cpu.dtb_walker_cache.overall_misses::total 9010 # number of overall misses
564system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 118862500 # number of ReadReq miss cycles
565system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 118862500 # number of ReadReq miss cycles
566system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 118862500 # number of demand (read+write) miss cycles
567system.cpu.dtb_walker_cache.demand_miss_latency::total 118862500 # number of demand (read+write) miss cycles
568system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 118862500 # number of overall miss cycles
569system.cpu.dtb_walker_cache.overall_miss_latency::total 118862500 # number of overall miss cycles
570system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21931 # number of ReadReq accesses(hits+misses)
571system.cpu.dtb_walker_cache.ReadReq_accesses::total 21931 # number of ReadReq accesses(hits+misses)
572system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21931 # number of demand (read+write) accesses
573system.cpu.dtb_walker_cache.demand_accesses::total 21931 # number of demand (read+write) accesses
574system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21931 # number of overall (read+write) accesses
575system.cpu.dtb_walker_cache.overall_accesses::total 21931 # number of overall (read+write) accesses
576system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.410834 # miss rate for ReadReq accesses
577system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.410834 # miss rate for ReadReq accesses
578system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.410834 # miss rate for demand accesses
579system.cpu.dtb_walker_cache.demand_miss_rate::total 0.410834 # miss rate for demand accesses
580system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.410834 # miss rate for overall accesses
581system.cpu.dtb_walker_cache.overall_miss_rate::total 0.410834 # miss rate for overall accesses
582system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13192.286349 # average ReadReq miss latency
583system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13192.286349 # average ReadReq miss latency
584system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency
585system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13192.286349 # average overall miss latency
586system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13192.286349 # average overall miss latency
587system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13192.286349 # average overall miss latency
| 335system.cpu.dtb_walker_cache.replacements 7423 # number of replacements
336system.cpu.dtb_walker_cache.tagsinuse 5.046109 # Cycle average of tags in use
337system.cpu.dtb_walker_cache.total_refs 13594 # Total number of references to valid blocks.
338system.cpu.dtb_walker_cache.sampled_refs 7438 # Sample count of references to valid blocks.
339system.cpu.dtb_walker_cache.avg_refs 1.827642 # Average number of references to valid blocks.
340system.cpu.dtb_walker_cache.warmup_cycle 5159593477000 # Cycle when the warmup percentage was hit.
341system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.046109 # Average occupied blocks per requestor
342system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315382 # Average percentage of cache occupancy
343system.cpu.dtb_walker_cache.occ_percent::total 0.315382 # Average percentage of cache occupancy
344system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13598 # number of ReadReq hits
345system.cpu.dtb_walker_cache.ReadReq_hits::total 13598 # number of ReadReq hits
346system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13598 # number of demand (read+write) hits
347system.cpu.dtb_walker_cache.demand_hits::total 13598 # number of demand (read+write) hits
348system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13598 # number of overall hits
349system.cpu.dtb_walker_cache.overall_hits::total 13598 # number of overall hits
350system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8635 # number of ReadReq misses
351system.cpu.dtb_walker_cache.ReadReq_misses::total 8635 # number of ReadReq misses
352system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8635 # number of demand (read+write) misses
353system.cpu.dtb_walker_cache.demand_misses::total 8635 # number of demand (read+write) misses
354system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8635 # number of overall misses
355system.cpu.dtb_walker_cache.overall_misses::total 8635 # number of overall misses
356system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91582000 # number of ReadReq miss cycles
357system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91582000 # number of ReadReq miss cycles
358system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91582000 # number of demand (read+write) miss cycles
359system.cpu.dtb_walker_cache.demand_miss_latency::total 91582000 # number of demand (read+write) miss cycles
360system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91582000 # number of overall miss cycles
361system.cpu.dtb_walker_cache.overall_miss_latency::total 91582000 # number of overall miss cycles
362system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22233 # number of ReadReq accesses(hits+misses)
363system.cpu.dtb_walker_cache.ReadReq_accesses::total 22233 # number of ReadReq accesses(hits+misses)
364system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22233 # number of demand (read+write) accesses
365system.cpu.dtb_walker_cache.demand_accesses::total 22233 # number of demand (read+write) accesses
366system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22233 # number of overall (read+write) accesses
367system.cpu.dtb_walker_cache.overall_accesses::total 22233 # number of overall (read+write) accesses
368system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.388387 # miss rate for ReadReq accesses
369system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.388387 # miss rate for ReadReq accesses
370system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.388387 # miss rate for demand accesses
371system.cpu.dtb_walker_cache.demand_miss_rate::total 0.388387 # miss rate for demand accesses
372system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.388387 # miss rate for overall accesses
373system.cpu.dtb_walker_cache.overall_miss_rate::total 0.388387 # miss rate for overall accesses
374system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10605.906196 # average ReadReq miss latency
375system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10605.906196 # average ReadReq miss latency
376system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency
377system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10605.906196 # average overall miss latency
378system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10605.906196 # average overall miss latency
379system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10605.906196 # average overall miss latency
|
588system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
589system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
590system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
591system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
592system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
593system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
594system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
595system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
| 380system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
381system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
382system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
383system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
384system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
385system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
386system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
387system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
596system.cpu.dtb_walker_cache.writebacks::writebacks 3142 # number of writebacks
597system.cpu.dtb_walker_cache.writebacks::total 3142 # number of writebacks
598system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9010 # number of ReadReq MSHR misses
599system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9010 # number of ReadReq MSHR misses
600system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9010 # number of demand (read+write) MSHR misses
601system.cpu.dtb_walker_cache.demand_mshr_misses::total 9010 # number of demand (read+write) MSHR misses
602system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9010 # number of overall MSHR misses
603system.cpu.dtb_walker_cache.overall_mshr_misses::total 9010 # number of overall MSHR misses
604system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 91832000 # number of ReadReq MSHR miss cycles
605system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 91832000 # number of ReadReq MSHR miss cycles
606system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 91832000 # number of demand (read+write) MSHR miss cycles
607system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 91832000 # number of demand (read+write) MSHR miss cycles
608system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 91832000 # number of overall MSHR miss cycles
609system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 91832000 # number of overall MSHR miss cycles
610system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for ReadReq accesses
611system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.410834 # mshr miss rate for ReadReq accesses
612system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for demand accesses
613system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.410834 # mshr miss rate for demand accesses
614system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.410834 # mshr miss rate for overall accesses
615system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.410834 # mshr miss rate for overall accesses
616system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average ReadReq mshr miss latency
617system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10192.230855 # average ReadReq mshr miss latency
618system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency
619system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency
620system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10192.230855 # average overall mshr miss latency
621system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10192.230855 # average overall mshr miss latency
| 388system.cpu.dtb_walker_cache.writebacks::writebacks 2904 # number of writebacks
389system.cpu.dtb_walker_cache.writebacks::total 2904 # number of writebacks
390system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8635 # number of ReadReq MSHR misses
391system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8635 # number of ReadReq MSHR misses
392system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8635 # number of demand (read+write) MSHR misses
393system.cpu.dtb_walker_cache.demand_mshr_misses::total 8635 # number of demand (read+write) MSHR misses
394system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8635 # number of overall MSHR misses
395system.cpu.dtb_walker_cache.overall_mshr_misses::total 8635 # number of overall MSHR misses
396system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74312000 # number of ReadReq MSHR miss cycles
397system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74312000 # number of ReadReq MSHR miss cycles
398system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74312000 # number of demand (read+write) MSHR miss cycles
399system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74312000 # number of demand (read+write) MSHR miss cycles
400system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74312000 # number of overall MSHR miss cycles
401system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74312000 # number of overall MSHR miss cycles
402system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for ReadReq accesses
403system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.388387 # mshr miss rate for ReadReq accesses
404system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for demand accesses
405system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.388387 # mshr miss rate for demand accesses
406system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.388387 # mshr miss rate for overall accesses
407system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.388387 # mshr miss rate for overall accesses
408system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average ReadReq mshr miss latency
409system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8605.906196 # average ReadReq mshr miss latency
410system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency
411system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency
412system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8605.906196 # average overall mshr miss latency
413system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8605.906196 # average overall mshr miss latency
|
622system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 414system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
623system.cpu.dcache.replacements 1622132 # number of replacements
624system.cpu.dcache.tagsinuse 511.997396 # Cycle average of tags in use
625system.cpu.dcache.total_refs 20004026 # Total number of references to valid blocks.
626system.cpu.dcache.sampled_refs 1622644 # Sample count of references to valid blocks.
627system.cpu.dcache.avg_refs 12.328044 # Average number of references to valid blocks.
628system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit.
629system.cpu.dcache.occ_blocks::cpu.data 511.997396 # Average occupied blocks per requestor
| 415system.cpu.dcache.replacements 1618325 # number of replacements
416system.cpu.dcache.tagsinuse 511.997377 # Cycle average of tags in use
417system.cpu.dcache.total_refs 20032981 # Total number of references to valid blocks.
418system.cpu.dcache.sampled_refs 1618837 # Sample count of references to valid blocks.
419system.cpu.dcache.avg_refs 12.374922 # Average number of references to valid blocks.
420system.cpu.dcache.warmup_cycle 43788000 # Cycle when the warmup percentage was hit.
421system.cpu.dcache.occ_blocks::cpu.data 511.997377 # Average occupied blocks per requestor
|
630system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
631system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
| 422system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
423system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
|
632system.cpu.dcache.ReadReq_hits::cpu.data 11972131 # number of ReadReq hits
633system.cpu.dcache.ReadReq_hits::total 11972131 # number of ReadReq hits
634system.cpu.dcache.WriteReq_hits::cpu.data 8029723 # number of WriteReq hits
635system.cpu.dcache.WriteReq_hits::total 8029723 # number of WriteReq hits
636system.cpu.dcache.demand_hits::cpu.data 20001854 # number of demand (read+write) hits
637system.cpu.dcache.demand_hits::total 20001854 # number of demand (read+write) hits
638system.cpu.dcache.overall_hits::cpu.data 20001854 # number of overall hits
639system.cpu.dcache.overall_hits::total 20001854 # number of overall hits
640system.cpu.dcache.ReadReq_misses::cpu.data 1309489 # number of ReadReq misses
641system.cpu.dcache.ReadReq_misses::total 1309489 # number of ReadReq misses
642system.cpu.dcache.WriteReq_misses::cpu.data 315369 # number of WriteReq misses
643system.cpu.dcache.WriteReq_misses::total 315369 # number of WriteReq misses
644system.cpu.dcache.demand_misses::cpu.data 1624858 # number of demand (read+write) misses
645system.cpu.dcache.demand_misses::total 1624858 # number of demand (read+write) misses
646system.cpu.dcache.overall_misses::cpu.data 1624858 # number of overall misses
647system.cpu.dcache.overall_misses::total 1624858 # number of overall misses
648system.cpu.dcache.ReadReq_miss_latency::cpu.data 19885711500 # number of ReadReq miss cycles
649system.cpu.dcache.ReadReq_miss_latency::total 19885711500 # number of ReadReq miss cycles
650system.cpu.dcache.WriteReq_miss_latency::cpu.data 9346101000 # number of WriteReq miss cycles
651system.cpu.dcache.WriteReq_miss_latency::total 9346101000 # number of WriteReq miss cycles
652system.cpu.dcache.demand_miss_latency::cpu.data 29231812500 # number of demand (read+write) miss cycles
653system.cpu.dcache.demand_miss_latency::total 29231812500 # number of demand (read+write) miss cycles
654system.cpu.dcache.overall_miss_latency::cpu.data 29231812500 # number of overall miss cycles
655system.cpu.dcache.overall_miss_latency::total 29231812500 # number of overall miss cycles
656system.cpu.dcache.ReadReq_accesses::cpu.data 13281620 # number of ReadReq accesses(hits+misses)
657system.cpu.dcache.ReadReq_accesses::total 13281620 # number of ReadReq accesses(hits+misses)
658system.cpu.dcache.WriteReq_accesses::cpu.data 8345092 # number of WriteReq accesses(hits+misses)
659system.cpu.dcache.WriteReq_accesses::total 8345092 # number of WriteReq accesses(hits+misses)
660system.cpu.dcache.demand_accesses::cpu.data 21626712 # number of demand (read+write) accesses
661system.cpu.dcache.demand_accesses::total 21626712 # number of demand (read+write) accesses
662system.cpu.dcache.overall_accesses::cpu.data 21626712 # number of overall (read+write) accesses
663system.cpu.dcache.overall_accesses::total 21626712 # number of overall (read+write) accesses
664system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098594 # miss rate for ReadReq accesses
665system.cpu.dcache.ReadReq_miss_rate::total 0.098594 # miss rate for ReadReq accesses
666system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037791 # miss rate for WriteReq accesses
667system.cpu.dcache.WriteReq_miss_rate::total 0.037791 # miss rate for WriteReq accesses
668system.cpu.dcache.demand_miss_rate::cpu.data 0.075132 # miss rate for demand accesses
669system.cpu.dcache.demand_miss_rate::total 0.075132 # miss rate for demand accesses
670system.cpu.dcache.overall_miss_rate::cpu.data 0.075132 # miss rate for overall accesses
671system.cpu.dcache.overall_miss_rate::total 0.075132 # miss rate for overall accesses
672system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15185.856086 # average ReadReq miss latency
673system.cpu.dcache.ReadReq_avg_miss_latency::total 15185.856086 # average ReadReq miss latency
674system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29635.446096 # average WriteReq miss latency
675system.cpu.dcache.WriteReq_avg_miss_latency::total 29635.446096 # average WriteReq miss latency
676system.cpu.dcache.demand_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency
677system.cpu.dcache.demand_avg_miss_latency::total 17990.379775 # average overall miss latency
678system.cpu.dcache.overall_avg_miss_latency::cpu.data 17990.379775 # average overall miss latency
679system.cpu.dcache.overall_avg_miss_latency::total 17990.379775 # average overall miss latency
| 424system.cpu.dcache.ReadReq_hits::cpu.data 11992560 # number of ReadReq hits
425system.cpu.dcache.ReadReq_hits::total 11992560 # number of ReadReq hits
426system.cpu.dcache.WriteReq_hits::cpu.data 8038236 # number of WriteReq hits
427system.cpu.dcache.WriteReq_hits::total 8038236 # number of WriteReq hits
428system.cpu.dcache.demand_hits::cpu.data 20030796 # number of demand (read+write) hits
429system.cpu.dcache.demand_hits::total 20030796 # number of demand (read+write) hits
430system.cpu.dcache.overall_hits::cpu.data 20030796 # number of overall hits
431system.cpu.dcache.overall_hits::total 20030796 # number of overall hits
432system.cpu.dcache.ReadReq_misses::cpu.data 1306270 # number of ReadReq misses
433system.cpu.dcache.ReadReq_misses::total 1306270 # number of ReadReq misses
434system.cpu.dcache.WriteReq_misses::cpu.data 314797 # number of WriteReq misses
435system.cpu.dcache.WriteReq_misses::total 314797 # number of WriteReq misses
436system.cpu.dcache.demand_misses::cpu.data 1621067 # number of demand (read+write) misses
437system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses
438system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses
439system.cpu.dcache.overall_misses::total 1621067 # number of overall misses
440system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles
441system.cpu.dcache.ReadReq_miss_latency::total 18175236500 # number of ReadReq miss cycles
442system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles
443system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles
444system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles
445system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles
446system.cpu.dcache.overall_miss_latency::cpu.data 27078679000 # number of overall miss cycles
447system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles
448system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses)
449system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses)
450system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses)
451system.cpu.dcache.WriteReq_accesses::total 8353033 # number of WriteReq accesses(hits+misses)
452system.cpu.dcache.demand_accesses::cpu.data 21651863 # number of demand (read+write) accesses
453system.cpu.dcache.demand_accesses::total 21651863 # number of demand (read+write) accesses
454system.cpu.dcache.overall_accesses::cpu.data 21651863 # number of overall (read+write) accesses
455system.cpu.dcache.overall_accesses::total 21651863 # number of overall (read+write) accesses
456system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098224 # miss rate for ReadReq accesses
457system.cpu.dcache.ReadReq_miss_rate::total 0.098224 # miss rate for ReadReq accesses
458system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037687 # miss rate for WriteReq accesses
459system.cpu.dcache.WriteReq_miss_rate::total 0.037687 # miss rate for WriteReq accesses
460system.cpu.dcache.demand_miss_rate::cpu.data 0.074870 # miss rate for demand accesses
461system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses
462system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses
463system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses
464system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency
465system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency
466system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency
467system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency
468system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency
469system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency
470system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency
471system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency
|
680system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
681system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
682system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
683system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
684system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
685system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
686system.cpu.dcache.fast_writes 0 # number of fast writes performed
687system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
473system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
476system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
477system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
478system.cpu.dcache.fast_writes 0 # number of fast writes performed
479system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
688system.cpu.dcache.writebacks::writebacks 1539490 # number of writebacks
689system.cpu.dcache.writebacks::total 1539490 # number of writebacks
690system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309489 # number of ReadReq MSHR misses
691system.cpu.dcache.ReadReq_mshr_misses::total 1309489 # number of ReadReq MSHR misses
692system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315369 # number of WriteReq MSHR misses
693system.cpu.dcache.WriteReq_mshr_misses::total 315369 # number of WriteReq MSHR misses
694system.cpu.dcache.demand_mshr_misses::cpu.data 1624858 # number of demand (read+write) MSHR misses
695system.cpu.dcache.demand_mshr_misses::total 1624858 # number of demand (read+write) MSHR misses
696system.cpu.dcache.overall_mshr_misses::cpu.data 1624858 # number of overall MSHR misses
697system.cpu.dcache.overall_mshr_misses::total 1624858 # number of overall MSHR misses
698system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15957199501 # number of ReadReq MSHR miss cycles
699system.cpu.dcache.ReadReq_mshr_miss_latency::total 15957199501 # number of ReadReq MSHR miss cycles
700system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8399992000 # number of WriteReq MSHR miss cycles
701system.cpu.dcache.WriteReq_mshr_miss_latency::total 8399992000 # number of WriteReq MSHR miss cycles
702system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24357191501 # number of demand (read+write) MSHR miss cycles
703system.cpu.dcache.demand_mshr_miss_latency::total 24357191501 # number of demand (read+write) MSHR miss cycles
704system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24357191501 # number of overall MSHR miss cycles
705system.cpu.dcache.overall_mshr_miss_latency::total 24357191501 # number of overall MSHR miss cycles
706system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 93628676500 # number of ReadReq MSHR uncacheable cycles
707system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 93628676500 # number of ReadReq MSHR uncacheable cycles
708system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467841500 # number of WriteReq MSHR uncacheable cycles
709system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467841500 # number of WriteReq MSHR uncacheable cycles
710system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096518000 # number of overall MSHR uncacheable cycles
711system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096518000 # number of overall MSHR uncacheable cycles
712system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098594 # mshr miss rate for ReadReq accesses
713system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098594 # mshr miss rate for ReadReq accesses
714system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037791 # mshr miss rate for WriteReq accesses
715system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037791 # mshr miss rate for WriteReq accesses
716system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for demand accesses
717system.cpu.dcache.demand_mshr_miss_rate::total 0.075132 # mshr miss rate for demand accesses
718system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075132 # mshr miss rate for overall accesses
719system.cpu.dcache.overall_mshr_miss_rate::total 0.075132 # mshr miss rate for overall accesses
720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12185.821722 # average ReadReq mshr miss latency
721system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12185.821722 # average ReadReq mshr miss latency
722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26635.439755 # average WriteReq mshr miss latency
723system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26635.439755 # average WriteReq mshr miss latency
724system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency
725system.cpu.dcache.demand_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency
726system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14990.350850 # average overall mshr miss latency
727system.cpu.dcache.overall_avg_mshr_miss_latency::total 14990.350850 # average overall mshr miss latency
| 480system.cpu.dcache.writebacks::writebacks 1535863 # number of writebacks
481system.cpu.dcache.writebacks::total 1535863 # number of writebacks
482system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306270 # number of ReadReq MSHR misses
483system.cpu.dcache.ReadReq_mshr_misses::total 1306270 # number of ReadReq MSHR misses
484system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314797 # number of WriteReq MSHR misses
485system.cpu.dcache.WriteReq_mshr_misses::total 314797 # number of WriteReq MSHR misses
486system.cpu.dcache.demand_mshr_misses::cpu.data 1621067 # number of demand (read+write) MSHR misses
487system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses
488system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses
489system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses
490system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562696500 # number of ReadReq MSHR miss cycles
491system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562696500 # number of ReadReq MSHR miss cycles
492system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles
493system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles
494system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545000 # number of demand (read+write) MSHR miss cycles
495system.cpu.dcache.demand_mshr_miss_latency::total 23836545000 # number of demand (read+write) MSHR miss cycles
496system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545000 # number of overall MSHR miss cycles
497system.cpu.dcache.overall_mshr_miss_latency::total 23836545000 # number of overall MSHR miss cycles
498system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles
499system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles
500system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469435000 # number of WriteReq MSHR uncacheable cycles
501system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469435000 # number of WriteReq MSHR uncacheable cycles
502system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616389000 # number of overall MSHR uncacheable cycles
503system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616389000 # number of overall MSHR uncacheable cycles
504system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses
505system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses
506system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses
507system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037687 # mshr miss rate for WriteReq accesses
508system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for demand accesses
509system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses
510system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses
511system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses
512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843616 # average ReadReq mshr miss latency
513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843616 # average ReadReq mshr miss latency
514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency
515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency
516system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency
517system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency
518system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency
519system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency
|
728system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
729system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
730system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
731system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
732system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
733system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
734system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
| 520system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
521system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
522system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
523system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
524system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
525system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
526system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
| 527system.cpu.l2cache.replacements 86829 # number of replacements
528system.cpu.l2cache.tagsinuse 64762.717222 # Cycle average of tags in use
529system.cpu.l2cache.total_refs 3488042 # Total number of references to valid blocks.
530system.cpu.l2cache.sampled_refs 151520 # Sample count of references to valid blocks.
531system.cpu.l2cache.avg_refs 23.020341 # Average number of references to valid blocks.
532system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
533system.cpu.l2cache.occ_blocks::writebacks 50387.154618 # Average occupied blocks per requestor
534system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140509 # Average occupied blocks per requestor
535system.cpu.l2cache.occ_blocks::cpu.inst 3354.597125 # Average occupied blocks per requestor
536system.cpu.l2cache.occ_blocks::cpu.data 11020.824971 # Average occupied blocks per requestor
537system.cpu.l2cache.occ_percent::writebacks 0.768847 # Average percentage of cache occupancy
538system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
539system.cpu.l2cache.occ_percent::cpu.inst 0.051187 # Average percentage of cache occupancy
540system.cpu.l2cache.occ_percent::cpu.data 0.168164 # Average percentage of cache occupancy
541system.cpu.l2cache.occ_percent::total 0.988201 # Average percentage of cache occupancy
542system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6338 # number of ReadReq hits
543system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2820 # number of ReadReq hits
544system.cpu.l2cache.ReadReq_hits::cpu.inst 780715 # number of ReadReq hits
545system.cpu.l2cache.ReadReq_hits::cpu.data 1277261 # number of ReadReq hits
546system.cpu.l2cache.ReadReq_hits::total 2067134 # number of ReadReq hits
547system.cpu.l2cache.Writeback_hits::writebacks 1539467 # number of Writeback hits
548system.cpu.l2cache.Writeback_hits::total 1539467 # number of Writeback hits
549system.cpu.l2cache.UpgradeReq_hits::cpu.data 313 # number of UpgradeReq hits
550system.cpu.l2cache.UpgradeReq_hits::total 313 # number of UpgradeReq hits
551system.cpu.l2cache.ReadExReq_hits::cpu.data 199347 # number of ReadExReq hits
552system.cpu.l2cache.ReadExReq_hits::total 199347 # number of ReadExReq hits
553system.cpu.l2cache.demand_hits::cpu.dtb.walker 6338 # number of demand (read+write) hits
554system.cpu.l2cache.demand_hits::cpu.itb.walker 2820 # number of demand (read+write) hits
555system.cpu.l2cache.demand_hits::cpu.inst 780715 # number of demand (read+write) hits
556system.cpu.l2cache.demand_hits::cpu.data 1476608 # number of demand (read+write) hits
557system.cpu.l2cache.demand_hits::total 2266481 # number of demand (read+write) hits
558system.cpu.l2cache.overall_hits::cpu.dtb.walker 6338 # number of overall hits
559system.cpu.l2cache.overall_hits::cpu.itb.walker 2820 # number of overall hits
560system.cpu.l2cache.overall_hits::cpu.inst 780715 # number of overall hits
561system.cpu.l2cache.overall_hits::cpu.data 1476608 # number of overall hits
562system.cpu.l2cache.overall_hits::total 2266481 # number of overall hits
563system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
564system.cpu.l2cache.ReadReq_misses::cpu.inst 12922 # number of ReadReq misses
565system.cpu.l2cache.ReadReq_misses::cpu.data 28238 # number of ReadReq misses
566system.cpu.l2cache.ReadReq_misses::total 41165 # number of ReadReq misses
567system.cpu.l2cache.UpgradeReq_misses::cpu.data 1345 # number of UpgradeReq misses
568system.cpu.l2cache.UpgradeReq_misses::total 1345 # number of UpgradeReq misses
569system.cpu.l2cache.ReadExReq_misses::cpu.data 113260 # number of ReadExReq misses
570system.cpu.l2cache.ReadExReq_misses::total 113260 # number of ReadExReq misses
571system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
572system.cpu.l2cache.demand_misses::cpu.inst 12922 # number of demand (read+write) misses
573system.cpu.l2cache.demand_misses::cpu.data 141498 # number of demand (read+write) misses
574system.cpu.l2cache.demand_misses::total 154425 # number of demand (read+write) misses
575system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
576system.cpu.l2cache.overall_misses::cpu.inst 12922 # number of overall misses
577system.cpu.l2cache.overall_misses::cpu.data 141498 # number of overall misses
578system.cpu.l2cache.overall_misses::total 154425 # number of overall misses
579system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles
580system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 672549000 # number of ReadReq miss cycles
581system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1483044000 # number of ReadReq miss cycles
582system.cpu.l2cache.ReadReq_miss_latency::total 2155853000 # number of ReadReq miss cycles
583system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 33608000 # number of UpgradeReq miss cycles
584system.cpu.l2cache.UpgradeReq_miss_latency::total 33608000 # number of UpgradeReq miss cycles
585system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5892280500 # number of ReadExReq miss cycles
586system.cpu.l2cache.ReadExReq_miss_latency::total 5892280500 # number of ReadExReq miss cycles
587system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles
588system.cpu.l2cache.demand_miss_latency::cpu.inst 672549000 # number of demand (read+write) miss cycles
589system.cpu.l2cache.demand_miss_latency::cpu.data 7375324500 # number of demand (read+write) miss cycles
590system.cpu.l2cache.demand_miss_latency::total 8048133500 # number of demand (read+write) miss cycles
591system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles
592system.cpu.l2cache.overall_miss_latency::cpu.inst 672549000 # number of overall miss cycles
593system.cpu.l2cache.overall_miss_latency::cpu.data 7375324500 # number of overall miss cycles
594system.cpu.l2cache.overall_miss_latency::total 8048133500 # number of overall miss cycles
595system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6338 # number of ReadReq accesses(hits+misses)
596system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2825 # number of ReadReq accesses(hits+misses)
597system.cpu.l2cache.ReadReq_accesses::cpu.inst 793637 # number of ReadReq accesses(hits+misses)
598system.cpu.l2cache.ReadReq_accesses::cpu.data 1305499 # number of ReadReq accesses(hits+misses)
599system.cpu.l2cache.ReadReq_accesses::total 2108299 # number of ReadReq accesses(hits+misses)
600system.cpu.l2cache.Writeback_accesses::writebacks 1539467 # number of Writeback accesses(hits+misses)
601system.cpu.l2cache.Writeback_accesses::total 1539467 # number of Writeback accesses(hits+misses)
602system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1658 # number of UpgradeReq accesses(hits+misses)
603system.cpu.l2cache.UpgradeReq_accesses::total 1658 # number of UpgradeReq accesses(hits+misses)
604system.cpu.l2cache.ReadExReq_accesses::cpu.data 312607 # number of ReadExReq accesses(hits+misses)
605system.cpu.l2cache.ReadExReq_accesses::total 312607 # number of ReadExReq accesses(hits+misses)
606system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6338 # number of demand (read+write) accesses
607system.cpu.l2cache.demand_accesses::cpu.itb.walker 2825 # number of demand (read+write) accesses
608system.cpu.l2cache.demand_accesses::cpu.inst 793637 # number of demand (read+write) accesses
609system.cpu.l2cache.demand_accesses::cpu.data 1618106 # number of demand (read+write) accesses
610system.cpu.l2cache.demand_accesses::total 2420906 # number of demand (read+write) accesses
611system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6338 # number of overall (read+write) accesses
612system.cpu.l2cache.overall_accesses::cpu.itb.walker 2825 # number of overall (read+write) accesses
613system.cpu.l2cache.overall_accesses::cpu.inst 793637 # number of overall (read+write) accesses
614system.cpu.l2cache.overall_accesses::cpu.data 1618106 # number of overall (read+write) accesses
615system.cpu.l2cache.overall_accesses::total 2420906 # number of overall (read+write) accesses
616system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001770 # miss rate for ReadReq accesses
617system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016282 # miss rate for ReadReq accesses
618system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021630 # miss rate for ReadReq accesses
619system.cpu.l2cache.ReadReq_miss_rate::total 0.019525 # miss rate for ReadReq accesses
620system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.811218 # miss rate for UpgradeReq accesses
621system.cpu.l2cache.UpgradeReq_miss_rate::total 0.811218 # miss rate for UpgradeReq accesses
622system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362308 # miss rate for ReadExReq accesses
623system.cpu.l2cache.ReadExReq_miss_rate::total 0.362308 # miss rate for ReadExReq accesses
624system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001770 # miss rate for demand accesses
625system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016282 # miss rate for demand accesses
626system.cpu.l2cache.demand_miss_rate::cpu.data 0.087447 # miss rate for demand accesses
627system.cpu.l2cache.demand_miss_rate::total 0.063788 # miss rate for demand accesses
628system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001770 # miss rate for overall accesses
629system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016282 # miss rate for overall accesses
630system.cpu.l2cache.overall_miss_rate::cpu.data 0.087447 # miss rate for overall accesses
631system.cpu.l2cache.overall_miss_rate::total 0.063788 # miss rate for overall accesses
632system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
633system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52046.819378 # average ReadReq miss latency
634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52519.441887 # average ReadReq miss latency
635system.cpu.l2cache.ReadReq_avg_miss_latency::total 52371.019070 # average ReadReq miss latency
636system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24987.360595 # average UpgradeReq miss latency
637system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24987.360595 # average UpgradeReq miss latency
638system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52024.373124 # average ReadExReq miss latency
639system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52024.373124 # average ReadExReq miss latency
640system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
641system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52046.819378 # average overall miss latency
642system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52123.171352 # average overall miss latency
643system.cpu.l2cache.demand_avg_miss_latency::total 52116.778371 # average overall miss latency
644system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
645system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52046.819378 # average overall miss latency
646system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52123.171352 # average overall miss latency
647system.cpu.l2cache.overall_avg_miss_latency::total 52116.778371 # average overall miss latency
648system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
649system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
650system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
651system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
652system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
653system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
654system.cpu.l2cache.fast_writes 0 # number of fast writes performed
655system.cpu.l2cache.cache_copies 0 # number of cache copies performed
656system.cpu.l2cache.writebacks::writebacks 80008 # number of writebacks
657system.cpu.l2cache.writebacks::total 80008 # number of writebacks
658system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
659system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12922 # number of ReadReq MSHR misses
660system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28238 # number of ReadReq MSHR misses
661system.cpu.l2cache.ReadReq_mshr_misses::total 41165 # number of ReadReq MSHR misses
662system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1345 # number of UpgradeReq MSHR misses
663system.cpu.l2cache.UpgradeReq_mshr_misses::total 1345 # number of UpgradeReq MSHR misses
664system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113260 # number of ReadExReq MSHR misses
665system.cpu.l2cache.ReadExReq_mshr_misses::total 113260 # number of ReadExReq MSHR misses
666system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
667system.cpu.l2cache.demand_mshr_misses::cpu.inst 12922 # number of demand (read+write) MSHR misses
668system.cpu.l2cache.demand_mshr_misses::cpu.data 141498 # number of demand (read+write) MSHR misses
669system.cpu.l2cache.demand_mshr_misses::total 154425 # number of demand (read+write) MSHR misses
670system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
671system.cpu.l2cache.overall_mshr_misses::cpu.inst 12922 # number of overall MSHR misses
672system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses
673system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses
674system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles
675system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles
676system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles
677system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles
678system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles
679system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles
680system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles
681system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles
682system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
683system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles
684system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles
685system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles
686system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
687system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles
688system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles
689system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles
690system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles
691system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles
692system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles
693system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305699000 # number of WriteReq MSHR uncacheable cycles
694system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88893260000 # number of overall MSHR uncacheable cycles
695system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88893260000 # number of overall MSHR uncacheable cycles
696system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for ReadReq accesses
697system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for ReadReq accesses
698system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021630 # mshr miss rate for ReadReq accesses
699system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019525 # mshr miss rate for ReadReq accesses
700system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811218 # mshr miss rate for UpgradeReq accesses
701system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811218 # mshr miss rate for UpgradeReq accesses
702system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362308 # mshr miss rate for ReadExReq accesses
703system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362308 # mshr miss rate for ReadExReq accesses
704system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for demand accesses
705system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for demand accesses
706system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for demand accesses
707system.cpu.l2cache.demand_mshr_miss_rate::total 0.063788 # mshr miss rate for demand accesses
708system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001770 # mshr miss rate for overall accesses
709system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016282 # mshr miss rate for overall accesses
710system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses
711system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses
712system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
713system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency
714system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency
715system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency
716system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency
717system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency
718system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency
719system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency
720system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
721system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency
722system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency
723system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency
724system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
725system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency
726system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency
727system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency
728system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
729system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
730system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
731system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
732system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
733system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
734system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
735
736---------- End Simulation Statistics ----------
| 735
736---------- End Simulation Statistics ----------
|