| stats.txt (9229:65f927bda74d) | stats.txt (9283:490958b032d6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.196023 # Number of seconds simulated 4sim_ticks 5196022575000 # Number of ticks simulated 5final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1315892 # Simulator instruction rate (inst/s) 8host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s) --- 28 unchanged lines hidden (view full) --- 37system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.196023 # Number of seconds simulated 4sim_ticks 5196022575000 # Number of ticks simulated 5final_tick 5196022575000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1315892 # Simulator instruction rate (inst/s) 8host_op_rate 2536713 # Simulator op (including micro ops) rate (op/s) --- 28 unchanged lines hidden (view full) --- 37system.physmem.bw_write::writebacks 1556169 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 1556169 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 1556169 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::pc.south_bridge.ide 554332 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 158620 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 1723682 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::total 3992863 # Total bandwidth to/from this memory (bytes/s) |
| 45system.l2c.replacements 86330 # number of replacements 46system.l2c.tagsinuse 64759.737076 # Cycle average of tags in use 47system.l2c.total_refs 3491284 # Total number of references to valid blocks. 48system.l2c.sampled_refs 151054 # Sample count of references to valid blocks. 49system.l2c.avg_refs 23.112821 # Average number of references to valid blocks. 50system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 51system.l2c.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor 52system.l2c.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor 53system.l2c.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor 54system.l2c.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor 55system.l2c.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy 56system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 57system.l2c.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy 58system.l2c.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy 59system.l2c.occ_percent::total 0.988155 # Average percentage of cache occupancy 60system.l2c.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits 61system.l2c.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits 62system.l2c.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits 63system.l2c.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits 64system.l2c.ReadReq_hits::total 2068208 # number of ReadReq hits 65system.l2c.Writeback_hits::writebacks 1543462 # number of Writeback hits 66system.l2c.Writeback_hits::total 1543462 # number of Writeback hits 67system.l2c.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits 68system.l2c.UpgradeReq_hits::total 302 # number of UpgradeReq hits 69system.l2c.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits 70system.l2c.ReadExReq_hits::total 200678 # number of ReadExReq hits 71system.l2c.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits 72system.l2c.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits 73system.l2c.demand_hits::cpu.inst 778172 # number of demand (read+write) hits 74system.l2c.demand_hits::cpu.data 1481001 # number of demand (read+write) hits 75system.l2c.demand_hits::total 2268886 # number of demand (read+write) hits 76system.l2c.overall_hits::cpu.dtb.walker 6719 # number of overall hits 77system.l2c.overall_hits::cpu.itb.walker 2994 # number of overall hits 78system.l2c.overall_hits::cpu.inst 778172 # number of overall hits 79system.l2c.overall_hits::cpu.data 1481001 # number of overall hits 80system.l2c.overall_hits::total 2268886 # number of overall hits 81system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 82system.l2c.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses 83system.l2c.ReadReq_misses::cpu.data 28353 # number of ReadReq misses 84system.l2c.ReadReq_misses::total 41237 # number of ReadReq misses 85system.l2c.UpgradeReq_misses::cpu.data 1338 # number of UpgradeReq misses 86system.l2c.UpgradeReq_misses::total 1338 # number of UpgradeReq misses 87system.l2c.ReadExReq_misses::cpu.data 112514 # number of ReadExReq misses 88system.l2c.ReadExReq_misses::total 112514 # number of ReadExReq misses 89system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 90system.l2c.demand_misses::cpu.inst 12879 # number of demand (read+write) misses 91system.l2c.demand_misses::cpu.data 140867 # number of demand (read+write) misses 92system.l2c.demand_misses::total 153751 # number of demand (read+write) misses 93system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses 94system.l2c.overall_misses::cpu.inst 12879 # number of overall misses 95system.l2c.overall_misses::cpu.data 140867 # number of overall misses 96system.l2c.overall_misses::total 153751 # number of overall misses 97system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles 98system.l2c.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles 99system.l2c.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles 100system.l2c.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles 101system.l2c.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles 102system.l2c.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles 103system.l2c.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles 104system.l2c.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles 105system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles 106system.l2c.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles 107system.l2c.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles 108system.l2c.demand_miss_latency::total 8011639500 # number of demand (read+write) miss cycles 109system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles 110system.l2c.overall_miss_latency::cpu.inst 670083000 # number of overall miss cycles 111system.l2c.overall_miss_latency::cpu.data 7341296500 # number of overall miss cycles 112system.l2c.overall_miss_latency::total 8011639500 # number of overall miss cycles 113system.l2c.ReadReq_accesses::cpu.dtb.walker 6719 # number of ReadReq accesses(hits+misses) 114system.l2c.ReadReq_accesses::cpu.itb.walker 2999 # number of ReadReq accesses(hits+misses) 115system.l2c.ReadReq_accesses::cpu.inst 791051 # number of ReadReq accesses(hits+misses) 116system.l2c.ReadReq_accesses::cpu.data 1308676 # number of ReadReq accesses(hits+misses) 117system.l2c.ReadReq_accesses::total 2109445 # number of ReadReq accesses(hits+misses) 118system.l2c.Writeback_accesses::writebacks 1543462 # number of Writeback accesses(hits+misses) 119system.l2c.Writeback_accesses::total 1543462 # number of Writeback accesses(hits+misses) 120system.l2c.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses) 121system.l2c.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses) 122system.l2c.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses) 123system.l2c.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses) 124system.l2c.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses 125system.l2c.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses 126system.l2c.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses 127system.l2c.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses 128system.l2c.demand_accesses::total 2422637 # number of demand (read+write) accesses 129system.l2c.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses 130system.l2c.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses 131system.l2c.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses 132system.l2c.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses 133system.l2c.overall_accesses::total 2422637 # number of overall (read+write) accesses 134system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses 135system.l2c.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses 136system.l2c.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses 137system.l2c.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses 138system.l2c.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses 139system.l2c.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses 140system.l2c.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses 141system.l2c.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses 142system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses 143system.l2c.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses 144system.l2c.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses 145system.l2c.demand_miss_rate::total 0.063464 # miss rate for demand accesses 146system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses 147system.l2c.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses 148system.l2c.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses 149system.l2c.overall_miss_rate::total 0.063464 # miss rate for overall accesses 150system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 151system.l2c.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency 152system.l2c.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency 153system.l2c.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency 154system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency 155system.l2c.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency 156system.l2c.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency 157system.l2c.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency 158system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 159system.l2c.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency 160system.l2c.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency 161system.l2c.demand_avg_miss_latency::total 52107.885477 # average overall miss latency 162system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 163system.l2c.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency 164system.l2c.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency 165system.l2c.overall_avg_miss_latency::total 52107.885477 # average overall miss latency 166system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 167system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 168system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 169system.l2c.blocked::no_targets 0 # number of cycles access was blocked 170system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 171system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172system.l2c.fast_writes 0 # number of fast writes performed 173system.l2c.cache_copies 0 # number of cache copies performed 174system.l2c.writebacks::writebacks 79675 # number of writebacks 175system.l2c.writebacks::total 79675 # number of writebacks 176system.l2c.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 177system.l2c.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses 178system.l2c.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses 179system.l2c.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses 180system.l2c.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses 181system.l2c.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses 182system.l2c.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses 183system.l2c.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses 184system.l2c.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 185system.l2c.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses 186system.l2c.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses 187system.l2c.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses 188system.l2c.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 189system.l2c.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses 190system.l2c.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses 191system.l2c.overall_mshr_misses::total 153751 # number of overall MSHR misses 192system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles 193system.l2c.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles 194system.l2c.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles 195system.l2c.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles 196system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles 197system.l2c.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles 198system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles 199system.l2c.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles 200system.l2c.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles 201system.l2c.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles 202system.l2c.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles 203system.l2c.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles 204system.l2c.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles 205system.l2c.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles 206system.l2c.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles 207system.l2c.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles 208system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles 209system.l2c.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles 210system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles 211system.l2c.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles 212system.l2c.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles 213system.l2c.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles 214system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses 215system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses 216system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses 217system.l2c.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses 218system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses 219system.l2c.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses 220system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses 221system.l2c.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses 222system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses 223system.l2c.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses 224system.l2c.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses 225system.l2c.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses 226system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses 227system.l2c.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses 228system.l2c.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses 229system.l2c.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses 230system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 231system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency 232system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency 233system.l2c.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency 234system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency 235system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency 236system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency 237system.l2c.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency 238system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 239system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency 240system.l2c.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency 241system.l2c.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency 242system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 243system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency 244system.l2c.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency 245system.l2c.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency 246system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 247system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 248system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 249system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 250system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 251system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 252system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 45system.cpu.l2cache.replacements 86330 # number of replacements 46system.cpu.l2cache.tagsinuse 64759.737076 # Cycle average of tags in use 47system.cpu.l2cache.total_refs 3491284 # Total number of references to valid blocks. 48system.cpu.l2cache.sampled_refs 151054 # Sample count of references to valid blocks. 49system.cpu.l2cache.avg_refs 23.112821 # Average number of references to valid blocks. 50system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 51system.cpu.l2cache.occ_blocks::writebacks 50074.264340 # Average occupied blocks per requestor 52system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140725 # Average occupied blocks per requestor 53system.cpu.l2cache.occ_blocks::cpu.inst 3394.913598 # Average occupied blocks per requestor 54system.cpu.l2cache.occ_blocks::cpu.data 11290.418413 # Average occupied blocks per requestor 55system.cpu.l2cache.occ_percent::writebacks 0.764073 # Average percentage of cache occupancy 56system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 57system.cpu.l2cache.occ_percent::cpu.inst 0.051802 # Average percentage of cache occupancy 58system.cpu.l2cache.occ_percent::cpu.data 0.172278 # Average percentage of cache occupancy 59system.cpu.l2cache.occ_percent::total 0.988155 # Average percentage of cache occupancy 60system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6719 # number of ReadReq hits 61system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2994 # number of ReadReq hits 62system.cpu.l2cache.ReadReq_hits::cpu.inst 778172 # number of ReadReq hits 63system.cpu.l2cache.ReadReq_hits::cpu.data 1280323 # number of ReadReq hits 64system.cpu.l2cache.ReadReq_hits::total 2068208 # number of ReadReq hits 65system.cpu.l2cache.Writeback_hits::writebacks 1543462 # number of Writeback hits 66system.cpu.l2cache.Writeback_hits::total 1543462 # number of Writeback hits 67system.cpu.l2cache.UpgradeReq_hits::cpu.data 302 # number of UpgradeReq hits 68system.cpu.l2cache.UpgradeReq_hits::total 302 # number of UpgradeReq hits 69system.cpu.l2cache.ReadExReq_hits::cpu.data 200678 # number of ReadExReq hits 70system.cpu.l2cache.ReadExReq_hits::total 200678 # number of ReadExReq hits 71system.cpu.l2cache.demand_hits::cpu.dtb.walker 6719 # number of demand (read+write) hits 72system.cpu.l2cache.demand_hits::cpu.itb.walker 2994 # number of demand (read+write) hits 73system.cpu.l2cache.demand_hits::cpu.inst 778172 # number of demand (read+write) hits 74system.cpu.l2cache.demand_hits::cpu.data 1481001 # number of demand (read+write) hits 75system.cpu.l2cache.demand_hits::total 2268886 # number of demand (read+write) hits 76system.cpu.l2cache.overall_hits::cpu.dtb.walker 6719 # number of overall hits 77system.cpu.l2cache.overall_hits::cpu.itb.walker 2994 # number of overall hits 78system.cpu.l2cache.overall_hits::cpu.inst 778172 # number of overall hits 79system.cpu.l2cache.overall_hits::cpu.data 1481001 # number of overall hits 80system.cpu.l2cache.overall_hits::total 2268886 # number of overall hits 81system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 82system.cpu.l2cache.ReadReq_misses::cpu.inst 12879 # number of ReadReq misses 83system.cpu.l2cache.ReadReq_misses::cpu.data 28353 # number of ReadReq misses 84system.cpu.l2cache.ReadReq_misses::total 41237 # number of ReadReq misses 85system.cpu.l2cache.UpgradeReq_misses::cpu.data 1338 # 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number of ReadReq miss cycles 98system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 670083000 # number of ReadReq miss cycles 99system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1488776500 # number of ReadReq miss cycles 100system.cpu.l2cache.ReadReq_miss_latency::total 2159119500 # number of ReadReq miss cycles 101system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 33785000 # number of UpgradeReq miss cycles 102system.cpu.l2cache.UpgradeReq_miss_latency::total 33785000 # number of UpgradeReq miss cycles 103system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5852520000 # number of ReadExReq miss cycles 104system.cpu.l2cache.ReadExReq_miss_latency::total 5852520000 # number of ReadExReq miss cycles 105system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles 106system.cpu.l2cache.demand_miss_latency::cpu.inst 670083000 # number of demand (read+write) miss cycles 107system.cpu.l2cache.demand_miss_latency::cpu.data 7341296500 # number of demand (read+write) miss cycles 108system.cpu.l2cache.demand_miss_latency::total 8011639500 # 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number of Writeback accesses(hits+misses) 120system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1640 # number of UpgradeReq accesses(hits+misses) 121system.cpu.l2cache.UpgradeReq_accesses::total 1640 # number of UpgradeReq accesses(hits+misses) 122system.cpu.l2cache.ReadExReq_accesses::cpu.data 313192 # number of ReadExReq accesses(hits+misses) 123system.cpu.l2cache.ReadExReq_accesses::total 313192 # number of ReadExReq accesses(hits+misses) 124system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6719 # number of demand (read+write) accesses 125system.cpu.l2cache.demand_accesses::cpu.itb.walker 2999 # number of demand (read+write) accesses 126system.cpu.l2cache.demand_accesses::cpu.inst 791051 # number of demand (read+write) accesses 127system.cpu.l2cache.demand_accesses::cpu.data 1621868 # number of demand (read+write) accesses 128system.cpu.l2cache.demand_accesses::total 2422637 # number of demand (read+write) accesses 129system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6719 # number of overall (read+write) accesses 130system.cpu.l2cache.overall_accesses::cpu.itb.walker 2999 # number of overall (read+write) accesses 131system.cpu.l2cache.overall_accesses::cpu.inst 791051 # number of overall (read+write) accesses 132system.cpu.l2cache.overall_accesses::cpu.data 1621868 # number of overall (read+write) accesses 133system.cpu.l2cache.overall_accesses::total 2422637 # number of overall (read+write) accesses 134system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses 135system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016281 # miss rate for ReadReq accesses 136system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021665 # miss rate for ReadReq accesses 137system.cpu.l2cache.ReadReq_miss_rate::total 0.019549 # miss rate for ReadReq accesses 138system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.815854 # miss rate for UpgradeReq accesses 139system.cpu.l2cache.UpgradeReq_miss_rate::total 0.815854 # miss rate for UpgradeReq accesses 140system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359249 # miss rate for ReadExReq accesses 141system.cpu.l2cache.ReadExReq_miss_rate::total 0.359249 # miss rate for ReadExReq accesses 142system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses 143system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016281 # miss rate for demand accesses 144system.cpu.l2cache.demand_miss_rate::cpu.data 0.086855 # miss rate for demand accesses 145system.cpu.l2cache.demand_miss_rate::total 0.063464 # miss rate for demand accesses 146system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses 147system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016281 # miss rate for overall accesses 148system.cpu.l2cache.overall_miss_rate::cpu.data 0.086855 # miss rate for overall accesses 149system.cpu.l2cache.overall_miss_rate::total 0.063464 # miss rate for overall accesses 150system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 151system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.117167 # average ReadReq miss latency 152system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52508.605791 # average ReadReq miss latency 153system.cpu.l2cache.ReadReq_avg_miss_latency::total 52358.791862 # average ReadReq miss latency 154system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 25250.373692 # average UpgradeReq miss latency 155system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 25250.373692 # average UpgradeReq miss latency 156system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52015.926907 # average ReadExReq miss latency 157system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52015.926907 # average ReadExReq miss latency 158system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 159system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency 160system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency 161system.cpu.l2cache.demand_avg_miss_latency::total 52107.885477 # average overall miss latency 162system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 163system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.117167 # average overall miss latency 164system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52115.090830 # average overall miss latency 165system.cpu.l2cache.overall_avg_miss_latency::total 52107.885477 # average overall miss latency 166system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 167system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 168system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 169system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 170system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 171system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172system.cpu.l2cache.fast_writes 0 # number of fast writes performed 173system.cpu.l2cache.cache_copies 0 # number of cache copies performed 174system.cpu.l2cache.writebacks::writebacks 79675 # number of writebacks 175system.cpu.l2cache.writebacks::total 79675 # number of writebacks 176system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 177system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12879 # number of ReadReq MSHR misses 178system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28353 # number of ReadReq MSHR misses 179system.cpu.l2cache.ReadReq_mshr_misses::total 41237 # number of ReadReq MSHR misses 180system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1338 # number of UpgradeReq MSHR misses 181system.cpu.l2cache.UpgradeReq_mshr_misses::total 1338 # number of UpgradeReq MSHR misses 182system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112514 # number of ReadExReq MSHR misses 183system.cpu.l2cache.ReadExReq_mshr_misses::total 112514 # number of ReadExReq MSHR misses 184system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 185system.cpu.l2cache.demand_mshr_misses::cpu.inst 12879 # number of demand (read+write) MSHR misses 186system.cpu.l2cache.demand_mshr_misses::cpu.data 140867 # number of demand (read+write) MSHR misses 187system.cpu.l2cache.demand_mshr_misses::total 153751 # number of demand (read+write) MSHR misses 188system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 189system.cpu.l2cache.overall_mshr_misses::cpu.inst 12879 # number of overall MSHR misses 190system.cpu.l2cache.overall_mshr_misses::cpu.data 140867 # number of overall MSHR misses 191system.cpu.l2cache.overall_mshr_misses::total 153751 # number of overall MSHR misses 192system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles 193system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 515526000 # number of ReadReq MSHR miss cycles 194system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1148536000 # number of ReadReq MSHR miss cycles 195system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1664262000 # number of ReadReq MSHR miss cycles 196system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 53936000 # number of UpgradeReq MSHR miss cycles 197system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 53936000 # number of UpgradeReq MSHR miss cycles 198system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4502349000 # number of ReadExReq MSHR miss cycles 199system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4502349000 # number of ReadExReq MSHR miss cycles 200system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles 201system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 515526000 # number of demand (read+write) MSHR miss cycles 202system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5650885000 # number of demand (read+write) MSHR miss cycles 203system.cpu.l2cache.demand_mshr_miss_latency::total 6166611000 # number of demand (read+write) MSHR miss cycles 204system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles 205system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 515526000 # number of overall MSHR miss cycles 206system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5650885000 # number of overall MSHR miss cycles 207system.cpu.l2cache.overall_mshr_miss_latency::total 6166611000 # number of overall MSHR miss cycles 208system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles 209system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles 210system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2306155000 # number of WriteReq MSHR uncacheable cycles 211system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2306155000 # number of WriteReq MSHR uncacheable cycles 212system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88423605000 # number of overall MSHR uncacheable cycles 213system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88423605000 # number of overall MSHR uncacheable cycles 214system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses 215system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for ReadReq accesses 216system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021665 # mshr miss rate for ReadReq accesses 217system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019549 # mshr miss rate for ReadReq accesses 218system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.815854 # mshr miss rate for UpgradeReq accesses 219system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.815854 # mshr miss rate for UpgradeReq accesses 220system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.359249 # mshr miss rate for ReadExReq accesses 221system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.359249 # mshr miss rate for ReadExReq accesses 222system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses 223system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for demand accesses 224system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for demand accesses 225system.cpu.l2cache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses 226system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses 227system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016281 # mshr miss rate for overall accesses 228system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086855 # mshr miss rate for overall accesses 229system.cpu.l2cache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses 230system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 231system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40028.418355 # average ReadReq mshr miss latency 232system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40508.447078 # average ReadReq mshr miss latency 233system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40358.464486 # average ReadReq mshr miss latency 234system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40310.911809 # average UpgradeReq mshr miss latency 235system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40310.911809 # average UpgradeReq mshr miss latency 236system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.900244 # average ReadExReq mshr miss latency 237system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.900244 # average ReadExReq mshr miss latency 238system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 239system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency 240system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency 241system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency 242system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 243system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40028.418355 # average overall mshr miss latency 244system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40115.037589 # average overall mshr miss latency 245system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40107.778161 # average overall mshr miss latency 246system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 247system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 248system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 249system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 250system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 251system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 252system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 253system.iocache.replacements 47503 # number of replacements 254system.iocache.tagsinuse 0.108744 # Cycle average of tags in use 255system.iocache.total_refs 0 # Total number of references to valid blocks. 256system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. 257system.iocache.avg_refs 0 # Average number of references to valid blocks. 258system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. 259system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor 260system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy --- 476 unchanged lines hidden --- | 253system.iocache.replacements 47503 # number of replacements 254system.iocache.tagsinuse 0.108744 # Cycle average of tags in use 255system.iocache.total_refs 0 # Total number of references to valid blocks. 256system.iocache.sampled_refs 47519 # Sample count of references to valid blocks. 257system.iocache.avg_refs 0 # Average number of references to valid blocks. 258system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit. 259system.iocache.occ_blocks::pc.south_bridge.ide 0.108744 # Average occupied blocks per requestor 260system.iocache.occ_percent::pc.south_bridge.ide 0.006796 # Average percentage of cache occupancy --- 476 unchanged lines hidden --- |