1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 5.191766 # Number of seconds simulated
4sim_ticks 5191766314000 # Number of ticks simulated
5final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 5.196043 # Number of seconds simulated
4sim_ticks 5196043137000 # Number of ticks simulated
5final_tick 5196043137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 787684 # Simulator instruction rate (inst/s)
8host_op_rate 1511929 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 29598304712 # Simulator tick rate (ticks/s)
10host_mem_usage 358992 # Number of bytes of host memory used
11host_seconds 175.41 # Real time elapsed on the host
12sim_insts 138165780 # Number of instructions simulated
13sim_ops 265203824 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory
| 7host_inst_rate 1241473 # Simulator instruction rate (inst/s)
8host_op_rate 2393258 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 50303585789 # Simulator tick rate (ticks/s)
10host_mem_usage 354304 # Number of bytes of host memory used
11host_seconds 103.29 # Real time elapsed on the host
12sim_insts 128236332 # Number of instructions simulated
13sim_ops 247208442 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2881344 # Number of bytes read from this memory
|
15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
| 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
16system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8939328 # Number of bytes read from this memory
18system.physmem.bytes_read::total 12651968 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 821248 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 8080768 # Number of bytes written to this memory
22system.physmem.bytes_written::total 8080768 # Number of bytes written to this memory
23system.physmem.num_reads::pc.south_bridge.ide 45173 # Number of read requests responded to by this memory
| 16system.physmem.bytes_read::cpu.inst 824320 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8950528 # Number of bytes read from this memory
18system.physmem.bytes_read::total 12656512 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 824320 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 824320 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 8081152 # Number of bytes written to this memory
22system.physmem.bytes_written::total 8081152 # Number of bytes written to this memory
23system.physmem.num_reads::pc.south_bridge.ide 45021 # Number of read requests responded to by this memory
|
24system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
| 24system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
25system.physmem.num_reads::cpu.inst 12832 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 139677 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 197687 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 126262 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 126262 # Number of write requests responded to by this memory
30system.physmem.bw_read::pc.south_bridge.ide 556857 # Total read bandwidth from this memory (bytes/s)
| 25system.physmem.num_reads::cpu.inst 12880 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 139852 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 197758 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 126268 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 126268 # Number of write requests responded to by this memory
30system.physmem.bw_read::pc.south_bridge.ide 554527 # Total read bandwidth from this memory (bytes/s)
|
31system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
| 31system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
|
32system.physmem.bw_read::cpu.inst 158183 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.data 1721828 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 2436929 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 158183 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 158183 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 1556458 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 1556458 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 1556458 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::pc.south_bridge.ide 556857 # Total bandwidth to/from this memory (bytes/s)
| 32system.physmem.bw_read::cpu.inst 158644 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.data 1722566 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 2435798 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 158644 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 158644 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 1555251 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 1555251 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 1555251 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::pc.south_bridge.ide 554527 # Total bandwidth to/from this memory (bytes/s)
|
41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
| 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
|
42system.physmem.bw_total::cpu.inst 158183 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::cpu.data 1721828 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s)
45system.l2c.replacements 86221 # number of replacements
46system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use
47system.l2c.total_refs 3490237 # Total number of references to valid blocks.
48system.l2c.sampled_refs 150947 # Sample count of references to valid blocks.
49system.l2c.avg_refs 23.122268 # Average number of references to valid blocks.
| 42system.physmem.bw_total::cpu.inst 158644 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::cpu.data 1722566 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::total 3991049 # Total bandwidth to/from this memory (bytes/s)
45system.l2c.replacements 86291 # number of replacements
46system.l2c.tagsinuse 64759.780052 # Cycle average of tags in use
47system.l2c.total_refs 3494113 # Total number of references to valid blocks.
48system.l2c.sampled_refs 150981 # Sample count of references to valid blocks.
49system.l2c.avg_refs 23.142733 # Average number of references to valid blocks.
|
50system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 50system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
51system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor
52system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor
53system.l2c.occ_blocks::cpu.inst 3484.481205 # Average occupied blocks per requestor
54system.l2c.occ_blocks::cpu.data 11111.678558 # Average occupied blocks per requestor
55system.l2c.occ_percent::writebacks 0.765539 # Average percentage of cache occupancy
| 51system.l2c.occ_blocks::writebacks 50071.847750 # Average occupied blocks per requestor
52system.l2c.occ_blocks::cpu.itb.walker 0.141309 # Average occupied blocks per requestor
53system.l2c.occ_blocks::cpu.inst 3396.359734 # Average occupied blocks per requestor
54system.l2c.occ_blocks::cpu.data 11291.431260 # Average occupied blocks per requestor
55system.l2c.occ_percent::writebacks 0.764036 # Average percentage of cache occupancy
|
56system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
| 56system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
57system.l2c.occ_percent::cpu.inst 0.053169 # Average percentage of cache occupancy
58system.l2c.occ_percent::cpu.data 0.169551 # Average percentage of cache occupancy
59system.l2c.occ_percent::total 0.988261 # Average percentage of cache occupancy
60system.l2c.ReadReq_hits::cpu.dtb.walker 6306 # number of ReadReq hits
61system.l2c.ReadReq_hits::cpu.itb.walker 2757 # number of ReadReq hits
62system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits
63system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits
64system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits
65system.l2c.Writeback_hits::writebacks 1541329 # number of Writeback hits
66system.l2c.Writeback_hits::total 1541329 # number of Writeback hits
67system.l2c.UpgradeReq_hits::cpu.data 319 # number of UpgradeReq hits
68system.l2c.UpgradeReq_hits::total 319 # number of UpgradeReq hits
69system.l2c.ReadExReq_hits::cpu.data 200451 # number of ReadExReq hits
70system.l2c.ReadExReq_hits::total 200451 # number of ReadExReq hits
71system.l2c.demand_hits::cpu.dtb.walker 6306 # number of demand (read+write) hits
72system.l2c.demand_hits::cpu.itb.walker 2757 # number of demand (read+write) hits
73system.l2c.demand_hits::cpu.inst 777565 # number of demand (read+write) hits
74system.l2c.demand_hits::cpu.data 1479802 # number of demand (read+write) hits
75system.l2c.demand_hits::total 2266430 # number of demand (read+write) hits
76system.l2c.overall_hits::cpu.dtb.walker 6306 # number of overall hits
77system.l2c.overall_hits::cpu.itb.walker 2757 # number of overall hits
78system.l2c.overall_hits::cpu.inst 777565 # number of overall hits
79system.l2c.overall_hits::cpu.data 1479802 # number of overall hits
80system.l2c.overall_hits::total 2266430 # number of overall hits
| 57system.l2c.occ_percent::cpu.inst 0.051824 # Average percentage of cache occupancy
58system.l2c.occ_percent::cpu.data 0.172294 # Average percentage of cache occupancy
59system.l2c.occ_percent::total 0.988156 # Average percentage of cache occupancy
60system.l2c.ReadReq_hits::cpu.dtb.walker 6458 # number of ReadReq hits
61system.l2c.ReadReq_hits::cpu.itb.walker 2811 # number of ReadReq hits
62system.l2c.ReadReq_hits::cpu.inst 779608 # number of ReadReq hits
63system.l2c.ReadReq_hits::cpu.data 1280721 # number of ReadReq hits
64system.l2c.ReadReq_hits::total 2069598 # number of ReadReq hits
65system.l2c.Writeback_hits::writebacks 1543757 # number of Writeback hits
66system.l2c.Writeback_hits::total 1543757 # number of Writeback hits
67system.l2c.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits
68system.l2c.UpgradeReq_hits::total 305 # number of UpgradeReq hits
69system.l2c.ReadExReq_hits::cpu.data 200867 # number of ReadExReq hits
70system.l2c.ReadExReq_hits::total 200867 # number of ReadExReq hits
71system.l2c.demand_hits::cpu.dtb.walker 6458 # number of demand (read+write) hits
72system.l2c.demand_hits::cpu.itb.walker 2811 # number of demand (read+write) hits
73system.l2c.demand_hits::cpu.inst 779608 # number of demand (read+write) hits
74system.l2c.demand_hits::cpu.data 1481588 # number of demand (read+write) hits
75system.l2c.demand_hits::total 2270465 # number of demand (read+write) hits
76system.l2c.overall_hits::cpu.dtb.walker 6458 # number of overall hits
77system.l2c.overall_hits::cpu.itb.walker 2811 # number of overall hits
78system.l2c.overall_hits::cpu.inst 779608 # number of overall hits
79system.l2c.overall_hits::cpu.data 1481588 # number of overall hits
80system.l2c.overall_hits::total 2270465 # number of overall hits
|
81system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
| 81system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
82system.l2c.ReadReq_misses::cpu.inst 12833 # number of ReadReq misses
83system.l2c.ReadReq_misses::cpu.data 28373 # number of ReadReq misses
84system.l2c.ReadReq_misses::total 41211 # number of ReadReq misses
85system.l2c.UpgradeReq_misses::cpu.data 1346 # number of UpgradeReq misses
86system.l2c.UpgradeReq_misses::total 1346 # number of UpgradeReq misses
87system.l2c.ReadExReq_misses::cpu.data 112235 # number of ReadExReq misses
88system.l2c.ReadExReq_misses::total 112235 # number of ReadExReq misses
| 82system.l2c.ReadReq_misses::cpu.inst 12881 # number of ReadReq misses
83system.l2c.ReadReq_misses::cpu.data 28319 # number of ReadReq misses
84system.l2c.ReadReq_misses::total 41205 # number of ReadReq misses
85system.l2c.UpgradeReq_misses::cpu.data 1371 # number of UpgradeReq misses
86system.l2c.UpgradeReq_misses::total 1371 # number of UpgradeReq misses
87system.l2c.ReadExReq_misses::cpu.data 112462 # number of ReadExReq misses
88system.l2c.ReadExReq_misses::total 112462 # number of ReadExReq misses
|
89system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
| 89system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
90system.l2c.demand_misses::cpu.inst 12833 # number of demand (read+write) misses
91system.l2c.demand_misses::cpu.data 140608 # number of demand (read+write) misses
92system.l2c.demand_misses::total 153446 # number of demand (read+write) misses
| 90system.l2c.demand_misses::cpu.inst 12881 # number of demand (read+write) misses
91system.l2c.demand_misses::cpu.data 140781 # number of demand (read+write) misses
92system.l2c.demand_misses::total 153667 # number of demand (read+write) misses
|
93system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses
| 93system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses
|
94system.l2c.overall_misses::cpu.inst 12833 # number of overall misses
95system.l2c.overall_misses::cpu.data 140608 # number of overall misses
96system.l2c.overall_misses::total 153446 # number of overall misses
| 94system.l2c.overall_misses::cpu.inst 12881 # number of overall misses
95system.l2c.overall_misses::cpu.data 140781 # number of overall misses
96system.l2c.overall_misses::total 153667 # number of overall misses
|
97system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles
| 97system.l2c.ReadReq_miss_latency::cpu.itb.walker 260000 # number of ReadReq miss cycles
|
98system.l2c.ReadReq_miss_latency::cpu.inst 667948500 # number of ReadReq miss cycles
99system.l2c.ReadReq_miss_latency::cpu.data 1489806000 # number of ReadReq miss cycles
100system.l2c.ReadReq_miss_latency::total 2158014500 # number of ReadReq miss cycles
101system.l2c.UpgradeReq_miss_latency::cpu.data 32975000 # number of UpgradeReq miss cycles
102system.l2c.UpgradeReq_miss_latency::total 32975000 # number of UpgradeReq miss cycles
103system.l2c.ReadExReq_miss_latency::cpu.data 5839097000 # number of ReadExReq miss cycles
104system.l2c.ReadExReq_miss_latency::total 5839097000 # number of ReadExReq miss cycles
| 98system.l2c.ReadReq_miss_latency::cpu.inst 670242000 # number of ReadReq miss cycles
99system.l2c.ReadReq_miss_latency::cpu.data 1486972500 # number of ReadReq miss cycles
100system.l2c.ReadReq_miss_latency::total 2157474500 # number of ReadReq miss cycles
101system.l2c.UpgradeReq_miss_latency::cpu.data 34071000 # number of UpgradeReq miss cycles
102system.l2c.UpgradeReq_miss_latency::total 34071000 # number of UpgradeReq miss cycles
103system.l2c.ReadExReq_miss_latency::cpu.data 5850445000 # number of ReadExReq miss cycles
104system.l2c.ReadExReq_miss_latency::total 5850445000 # number of ReadExReq miss cycles
|
105system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles
| 105system.l2c.demand_miss_latency::cpu.itb.walker 260000 # number of demand (read+write) miss cycles
|
106system.l2c.demand_miss_latency::cpu.inst 667948500 # number of demand (read+write) miss cycles
107system.l2c.demand_miss_latency::cpu.data 7328903000 # number of demand (read+write) miss cycles
108system.l2c.demand_miss_latency::total 7997111500 # number of demand (read+write) miss cycles
| 106system.l2c.demand_miss_latency::cpu.inst 670242000 # number of demand (read+write) miss cycles
107system.l2c.demand_miss_latency::cpu.data 7337417500 # number of demand (read+write) miss cycles
108system.l2c.demand_miss_latency::total 8007919500 # number of demand (read+write) miss cycles
|
109system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles
| 109system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles
|
110system.l2c.overall_miss_latency::cpu.inst 667948500 # number of overall miss cycles
111system.l2c.overall_miss_latency::cpu.data 7328903000 # number of overall miss cycles
112system.l2c.overall_miss_latency::total 7997111500 # number of overall miss cycles
113system.l2c.ReadReq_accesses::cpu.dtb.walker 6306 # number of ReadReq accesses(hits+misses)
114system.l2c.ReadReq_accesses::cpu.itb.walker 2762 # number of ReadReq accesses(hits+misses)
115system.l2c.ReadReq_accesses::cpu.inst 790398 # number of ReadReq accesses(hits+misses)
116system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses)
117system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses)
118system.l2c.Writeback_accesses::writebacks 1541329 # number of Writeback accesses(hits+misses)
119system.l2c.Writeback_accesses::total 1541329 # number of Writeback accesses(hits+misses)
120system.l2c.UpgradeReq_accesses::cpu.data 1665 # number of UpgradeReq accesses(hits+misses)
121system.l2c.UpgradeReq_accesses::total 1665 # number of UpgradeReq accesses(hits+misses)
122system.l2c.ReadExReq_accesses::cpu.data 312686 # number of ReadExReq accesses(hits+misses)
123system.l2c.ReadExReq_accesses::total 312686 # number of ReadExReq accesses(hits+misses)
124system.l2c.demand_accesses::cpu.dtb.walker 6306 # number of demand (read+write) accesses
125system.l2c.demand_accesses::cpu.itb.walker 2762 # number of demand (read+write) accesses
126system.l2c.demand_accesses::cpu.inst 790398 # number of demand (read+write) accesses
127system.l2c.demand_accesses::cpu.data 1620410 # number of demand (read+write) accesses
128system.l2c.demand_accesses::total 2419876 # number of demand (read+write) accesses
129system.l2c.overall_accesses::cpu.dtb.walker 6306 # number of overall (read+write) accesses
130system.l2c.overall_accesses::cpu.itb.walker 2762 # number of overall (read+write) accesses
131system.l2c.overall_accesses::cpu.inst 790398 # number of overall (read+write) accesses
132system.l2c.overall_accesses::cpu.data 1620410 # number of overall (read+write) accesses
133system.l2c.overall_accesses::total 2419876 # number of overall (read+write) accesses
134system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001810 # miss rate for ReadReq accesses
135system.l2c.ReadReq_miss_rate::cpu.inst 0.016236 # miss rate for ReadReq accesses
136system.l2c.ReadReq_miss_rate::cpu.data 0.021696 # miss rate for ReadReq accesses
137system.l2c.ReadReq_miss_rate::total 0.019557 # miss rate for ReadReq accesses
138system.l2c.UpgradeReq_miss_rate::cpu.data 0.808408 # miss rate for UpgradeReq accesses
139system.l2c.UpgradeReq_miss_rate::total 0.808408 # miss rate for UpgradeReq accesses
140system.l2c.ReadExReq_miss_rate::cpu.data 0.358938 # miss rate for ReadExReq accesses
141system.l2c.ReadExReq_miss_rate::total 0.358938 # miss rate for ReadExReq accesses
142system.l2c.demand_miss_rate::cpu.itb.walker 0.001810 # miss rate for demand accesses
143system.l2c.demand_miss_rate::cpu.inst 0.016236 # miss rate for demand accesses
144system.l2c.demand_miss_rate::cpu.data 0.086773 # miss rate for demand accesses
145system.l2c.demand_miss_rate::total 0.063411 # miss rate for demand accesses
146system.l2c.overall_miss_rate::cpu.itb.walker 0.001810 # miss rate for overall accesses
147system.l2c.overall_miss_rate::cpu.inst 0.016236 # miss rate for overall accesses
148system.l2c.overall_miss_rate::cpu.data 0.086773 # miss rate for overall accesses
149system.l2c.overall_miss_rate::total 0.063411 # miss rate for overall accesses
| 110system.l2c.overall_miss_latency::cpu.inst 670242000 # number of overall miss cycles
111system.l2c.overall_miss_latency::cpu.data 7337417500 # number of overall miss cycles
112system.l2c.overall_miss_latency::total 8007919500 # number of overall miss cycles
113system.l2c.ReadReq_accesses::cpu.dtb.walker 6458 # number of ReadReq accesses(hits+misses)
114system.l2c.ReadReq_accesses::cpu.itb.walker 2816 # number of ReadReq accesses(hits+misses)
115system.l2c.ReadReq_accesses::cpu.inst 792489 # number of ReadReq accesses(hits+misses)
116system.l2c.ReadReq_accesses::cpu.data 1309040 # number of ReadReq accesses(hits+misses)
117system.l2c.ReadReq_accesses::total 2110803 # number of ReadReq accesses(hits+misses)
118system.l2c.Writeback_accesses::writebacks 1543757 # number of Writeback accesses(hits+misses)
119system.l2c.Writeback_accesses::total 1543757 # number of Writeback accesses(hits+misses)
120system.l2c.UpgradeReq_accesses::cpu.data 1676 # number of UpgradeReq accesses(hits+misses)
121system.l2c.UpgradeReq_accesses::total 1676 # number of UpgradeReq accesses(hits+misses)
122system.l2c.ReadExReq_accesses::cpu.data 313329 # number of ReadExReq accesses(hits+misses)
123system.l2c.ReadExReq_accesses::total 313329 # number of ReadExReq accesses(hits+misses)
124system.l2c.demand_accesses::cpu.dtb.walker 6458 # number of demand (read+write) accesses
125system.l2c.demand_accesses::cpu.itb.walker 2816 # number of demand (read+write) accesses
126system.l2c.demand_accesses::cpu.inst 792489 # number of demand (read+write) accesses
127system.l2c.demand_accesses::cpu.data 1622369 # number of demand (read+write) accesses
128system.l2c.demand_accesses::total 2424132 # number of demand (read+write) accesses
129system.l2c.overall_accesses::cpu.dtb.walker 6458 # number of overall (read+write) accesses
130system.l2c.overall_accesses::cpu.itb.walker 2816 # number of overall (read+write) accesses
131system.l2c.overall_accesses::cpu.inst 792489 # number of overall (read+write) accesses
132system.l2c.overall_accesses::cpu.data 1622369 # number of overall (read+write) accesses
133system.l2c.overall_accesses::total 2424132 # number of overall (read+write) accesses
134system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001776 # miss rate for ReadReq accesses
135system.l2c.ReadReq_miss_rate::cpu.inst 0.016254 # miss rate for ReadReq accesses
136system.l2c.ReadReq_miss_rate::cpu.data 0.021633 # miss rate for ReadReq accesses
137system.l2c.ReadReq_miss_rate::total 0.019521 # miss rate for ReadReq accesses
138system.l2c.UpgradeReq_miss_rate::cpu.data 0.818019 # miss rate for UpgradeReq accesses
139system.l2c.UpgradeReq_miss_rate::total 0.818019 # miss rate for UpgradeReq accesses
140system.l2c.ReadExReq_miss_rate::cpu.data 0.358926 # miss rate for ReadExReq accesses
141system.l2c.ReadExReq_miss_rate::total 0.358926 # miss rate for ReadExReq accesses
142system.l2c.demand_miss_rate::cpu.itb.walker 0.001776 # miss rate for demand accesses
143system.l2c.demand_miss_rate::cpu.inst 0.016254 # miss rate for demand accesses
144system.l2c.demand_miss_rate::cpu.data 0.086775 # miss rate for demand accesses
145system.l2c.demand_miss_rate::total 0.063391 # miss rate for demand accesses
146system.l2c.overall_miss_rate::cpu.itb.walker 0.001776 # miss rate for overall accesses
147system.l2c.overall_miss_rate::cpu.inst 0.016254 # miss rate for overall accesses
148system.l2c.overall_miss_rate::cpu.data 0.086775 # miss rate for overall accesses
149system.l2c.overall_miss_rate::total 0.063391 # miss rate for overall accesses
|
150system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
| 150system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
|
151system.l2c.ReadReq_avg_miss_latency::cpu.inst 52049.286994 # average ReadReq miss latency
152system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.877207 # average ReadReq miss latency
153system.l2c.ReadReq_avg_miss_latency::total 52365.011769 # average ReadReq miss latency
154system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24498.514116 # average UpgradeReq miss latency
155system.l2c.UpgradeReq_avg_miss_latency::total 24498.514116 # average UpgradeReq miss latency
156system.l2c.ReadExReq_avg_miss_latency::cpu.data 52025.633715 # average ReadExReq miss latency
157system.l2c.ReadExReq_avg_miss_latency::total 52025.633715 # average ReadExReq miss latency
| 151system.l2c.ReadReq_avg_miss_latency::cpu.inst 52033.382501 # average ReadReq miss latency
152system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.945196 # average ReadReq miss latency
153system.l2c.ReadReq_avg_miss_latency::total 52359.531610 # average ReadReq miss latency
154system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24851.203501 # average UpgradeReq miss latency
155system.l2c.UpgradeReq_avg_miss_latency::total 24851.203501 # average UpgradeReq miss latency
156system.l2c.ReadExReq_avg_miss_latency::cpu.data 52021.527271 # average ReadExReq miss latency
157system.l2c.ReadExReq_avg_miss_latency::total 52021.527271 # average ReadExReq miss latency
|
158system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
| 158system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
159system.l2c.demand_avg_miss_latency::cpu.inst 52049.286994 # average overall miss latency
160system.l2c.demand_avg_miss_latency::cpu.data 52122.944640 # average overall miss latency
161system.l2c.demand_avg_miss_latency::total 52116.780496 # average overall miss latency
| 159system.l2c.demand_avg_miss_latency::cpu.inst 52033.382501 # average overall miss latency
160system.l2c.demand_avg_miss_latency::cpu.data 52119.373353 # average overall miss latency
161system.l2c.demand_avg_miss_latency::total 52112.161362 # average overall miss latency
|
162system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
| 162system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
|
163system.l2c.overall_avg_miss_latency::cpu.inst 52049.286994 # average overall miss latency
164system.l2c.overall_avg_miss_latency::cpu.data 52122.944640 # average overall miss latency
165system.l2c.overall_avg_miss_latency::total 52116.780496 # average overall miss latency
| 163system.l2c.overall_avg_miss_latency::cpu.inst 52033.382501 # average overall miss latency
164system.l2c.overall_avg_miss_latency::cpu.data 52119.373353 # average overall miss latency
165system.l2c.overall_avg_miss_latency::total 52112.161362 # average overall miss latency
|
166system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
167system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
168system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
169system.l2c.blocked::no_targets 0 # number of cycles access was blocked
170system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
171system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
172system.l2c.fast_writes 0 # number of fast writes performed
173system.l2c.cache_copies 0 # number of cache copies performed
| 166system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
167system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
168system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
169system.l2c.blocked::no_targets 0 # number of cycles access was blocked
170system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
171system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
172system.l2c.fast_writes 0 # number of fast writes performed
173system.l2c.cache_copies 0 # number of cache copies performed
|
174system.l2c.writebacks::writebacks 79595 # number of writebacks
175system.l2c.writebacks::total 79595 # number of writebacks
| 174system.l2c.writebacks::writebacks 79601 # number of writebacks
175system.l2c.writebacks::total 79601 # number of writebacks
|
176system.l2c.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
| 176system.l2c.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
|
177system.l2c.ReadReq_mshr_misses::cpu.inst 12833 # number of ReadReq MSHR misses
178system.l2c.ReadReq_mshr_misses::cpu.data 28373 # number of ReadReq MSHR misses
179system.l2c.ReadReq_mshr_misses::total 41211 # number of ReadReq MSHR misses
180system.l2c.UpgradeReq_mshr_misses::cpu.data 1346 # number of UpgradeReq MSHR misses
181system.l2c.UpgradeReq_mshr_misses::total 1346 # number of UpgradeReq MSHR misses
182system.l2c.ReadExReq_mshr_misses::cpu.data 112235 # number of ReadExReq MSHR misses
183system.l2c.ReadExReq_mshr_misses::total 112235 # number of ReadExReq MSHR misses
| 177system.l2c.ReadReq_mshr_misses::cpu.inst 12881 # number of ReadReq MSHR misses
178system.l2c.ReadReq_mshr_misses::cpu.data 28319 # number of ReadReq MSHR misses
179system.l2c.ReadReq_mshr_misses::total 41205 # number of ReadReq MSHR misses
180system.l2c.UpgradeReq_mshr_misses::cpu.data 1371 # number of UpgradeReq MSHR misses
181system.l2c.UpgradeReq_mshr_misses::total 1371 # number of UpgradeReq MSHR misses
182system.l2c.ReadExReq_mshr_misses::cpu.data 112462 # number of ReadExReq MSHR misses
183system.l2c.ReadExReq_mshr_misses::total 112462 # number of ReadExReq MSHR misses
|
184system.l2c.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
| 184system.l2c.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
|
185system.l2c.demand_mshr_misses::cpu.inst 12833 # number of demand (read+write) MSHR misses
186system.l2c.demand_mshr_misses::cpu.data 140608 # number of demand (read+write) MSHR misses
187system.l2c.demand_mshr_misses::total 153446 # number of demand (read+write) MSHR misses
| 185system.l2c.demand_mshr_misses::cpu.inst 12881 # number of demand (read+write) MSHR misses
186system.l2c.demand_mshr_misses::cpu.data 140781 # number of demand (read+write) MSHR misses
187system.l2c.demand_mshr_misses::total 153667 # number of demand (read+write) MSHR misses
|
188system.l2c.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
| 188system.l2c.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
|
189system.l2c.overall_mshr_misses::cpu.inst 12833 # number of overall MSHR misses
190system.l2c.overall_mshr_misses::cpu.data 140608 # number of overall MSHR misses
191system.l2c.overall_mshr_misses::total 153446 # number of overall MSHR misses
| 189system.l2c.overall_mshr_misses::cpu.inst 12881 # number of overall MSHR misses
190system.l2c.overall_mshr_misses::cpu.data 140781 # number of overall MSHR misses
191system.l2c.overall_mshr_misses::total 153667 # number of overall MSHR misses
|
192system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles
| 192system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles
|
193system.l2c.ReadReq_mshr_miss_latency::cpu.inst 513944000 # number of ReadReq MSHR miss cycles
194system.l2c.ReadReq_mshr_miss_latency::cpu.data 1149325000 # number of ReadReq MSHR miss cycles
195system.l2c.ReadReq_mshr_miss_latency::total 1663469000 # number of ReadReq MSHR miss cycles
196system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 54216000 # number of UpgradeReq MSHR miss cycles
197system.l2c.UpgradeReq_mshr_miss_latency::total 54216000 # number of UpgradeReq MSHR miss cycles
198system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4492274000 # number of ReadExReq MSHR miss cycles
199system.l2c.ReadExReq_mshr_miss_latency::total 4492274000 # number of ReadExReq MSHR miss cycles
| 193system.l2c.ReadReq_mshr_miss_latency::cpu.inst 515661000 # number of ReadReq MSHR miss cycles
194system.l2c.ReadReq_mshr_miss_latency::cpu.data 1147140000 # number of ReadReq MSHR miss cycles
195system.l2c.ReadReq_mshr_miss_latency::total 1663001000 # number of ReadReq MSHR miss cycles
196system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55229000 # number of UpgradeReq MSHR miss cycles
197system.l2c.UpgradeReq_mshr_miss_latency::total 55229000 # number of UpgradeReq MSHR miss cycles
198system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4500898000 # number of ReadExReq MSHR miss cycles
199system.l2c.ReadExReq_mshr_miss_latency::total 4500898000 # number of ReadExReq MSHR miss cycles
|
200system.l2c.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
| 200system.l2c.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
|
201system.l2c.demand_mshr_miss_latency::cpu.inst 513944000 # number of demand (read+write) MSHR miss cycles
202system.l2c.demand_mshr_miss_latency::cpu.data 5641599000 # number of demand (read+write) MSHR miss cycles
203system.l2c.demand_mshr_miss_latency::total 6155743000 # number of demand (read+write) MSHR miss cycles
| 201system.l2c.demand_mshr_miss_latency::cpu.inst 515661000 # number of demand (read+write) MSHR miss cycles
202system.l2c.demand_mshr_miss_latency::cpu.data 5648038000 # number of demand (read+write) MSHR miss cycles
203system.l2c.demand_mshr_miss_latency::total 6163899000 # number of demand (read+write) MSHR miss cycles
|
204system.l2c.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
| 204system.l2c.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
|
205system.l2c.overall_mshr_miss_latency::cpu.inst 513944000 # number of overall MSHR miss cycles
206system.l2c.overall_mshr_miss_latency::cpu.data 5641599000 # number of overall MSHR miss cycles
207system.l2c.overall_mshr_miss_latency::total 6155743000 # number of overall MSHR miss cycles
208system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56050191064 # number of ReadReq MSHR uncacheable cycles
209system.l2c.ReadReq_mshr_uncacheable_latency::total 56050191064 # number of ReadReq MSHR uncacheable cycles
210system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1204378000 # number of WriteReq MSHR uncacheable cycles
211system.l2c.WriteReq_mshr_uncacheable_latency::total 1204378000 # number of WriteReq MSHR uncacheable cycles
212system.l2c.overall_mshr_uncacheable_latency::cpu.data 57254569064 # number of overall MSHR uncacheable cycles
213system.l2c.overall_mshr_uncacheable_latency::total 57254569064 # number of overall MSHR uncacheable cycles
214system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for ReadReq accesses
215system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for ReadReq accesses
216system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021696 # mshr miss rate for ReadReq accesses
217system.l2c.ReadReq_mshr_miss_rate::total 0.019557 # mshr miss rate for ReadReq accesses
218system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.808408 # mshr miss rate for UpgradeReq accesses
219system.l2c.UpgradeReq_mshr_miss_rate::total 0.808408 # mshr miss rate for UpgradeReq accesses
220system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.358938 # mshr miss rate for ReadExReq accesses
221system.l2c.ReadExReq_mshr_miss_rate::total 0.358938 # mshr miss rate for ReadExReq accesses
222system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for demand accesses
223system.l2c.demand_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for demand accesses
224system.l2c.demand_mshr_miss_rate::cpu.data 0.086773 # mshr miss rate for demand accesses
225system.l2c.demand_mshr_miss_rate::total 0.063411 # mshr miss rate for demand accesses
226system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for overall accesses
227system.l2c.overall_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for overall accesses
228system.l2c.overall_mshr_miss_rate::cpu.data 0.086773 # mshr miss rate for overall accesses
229system.l2c.overall_mshr_miss_rate::total 0.063411 # mshr miss rate for overall accesses
| 205system.l2c.overall_mshr_miss_latency::cpu.inst 515661000 # number of overall MSHR miss cycles
206system.l2c.overall_mshr_miss_latency::cpu.data 5648038000 # number of overall MSHR miss cycles
207system.l2c.overall_mshr_miss_latency::total 6163899000 # number of overall MSHR miss cycles
208system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 86117450000 # number of ReadReq MSHR uncacheable cycles
209system.l2c.ReadReq_mshr_uncacheable_latency::total 86117450000 # number of ReadReq MSHR uncacheable cycles
210system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 2306140000 # number of WriteReq MSHR uncacheable cycles
211system.l2c.WriteReq_mshr_uncacheable_latency::total 2306140000 # number of WriteReq MSHR uncacheable cycles
212system.l2c.overall_mshr_uncacheable_latency::cpu.data 88423590000 # number of overall MSHR uncacheable cycles
213system.l2c.overall_mshr_uncacheable_latency::total 88423590000 # number of overall MSHR uncacheable cycles
214system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for ReadReq accesses
215system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for ReadReq accesses
216system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021633 # mshr miss rate for ReadReq accesses
217system.l2c.ReadReq_mshr_miss_rate::total 0.019521 # mshr miss rate for ReadReq accesses
218system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818019 # mshr miss rate for UpgradeReq accesses
219system.l2c.UpgradeReq_mshr_miss_rate::total 0.818019 # mshr miss rate for UpgradeReq accesses
220system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.358926 # mshr miss rate for ReadExReq accesses
221system.l2c.ReadExReq_mshr_miss_rate::total 0.358926 # mshr miss rate for ReadExReq accesses
222system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for demand accesses
223system.l2c.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses
224system.l2c.demand_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for demand accesses
225system.l2c.demand_mshr_miss_rate::total 0.063391 # mshr miss rate for demand accesses
226system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001776 # mshr miss rate for overall accesses
227system.l2c.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses
228system.l2c.overall_mshr_miss_rate::cpu.data 0.086775 # mshr miss rate for overall accesses
229system.l2c.overall_mshr_miss_rate::total 0.063391 # mshr miss rate for overall accesses
|
230system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
| 230system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
|
231system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40048.624640 # average ReadReq mshr miss latency
232system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.700983 # average ReadReq mshr miss latency
233system.l2c.ReadReq_avg_mshr_miss_latency::total 40364.684186 # average ReadReq mshr miss latency
234system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40279.346211 # average UpgradeReq mshr miss latency
235system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40279.346211 # average UpgradeReq mshr miss latency
236system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40025.606985 # average ReadExReq mshr miss latency
237system.l2c.ReadExReq_avg_mshr_miss_latency::total 40025.606985 # average ReadExReq mshr miss latency
| 231system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40032.683798 # average ReadReq mshr miss latency
232system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.786292 # average ReadReq mshr miss latency
233system.l2c.ReadReq_avg_mshr_miss_latency::total 40359.203980 # average ReadReq mshr miss latency
234system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40283.734500 # average UpgradeReq mshr miss latency
235system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40283.734500 # average UpgradeReq mshr miss latency
236system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40021.500596 # average ReadExReq mshr miss latency
237system.l2c.ReadExReq_avg_mshr_miss_latency::total 40021.500596 # average ReadExReq mshr miss latency
|
238system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
| 238system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
239system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40048.624640 # average overall mshr miss latency
240system.l2c.demand_avg_mshr_miss_latency::cpu.data 40122.887745 # average overall mshr miss latency
241system.l2c.demand_avg_mshr_miss_latency::total 40116.672966 # average overall mshr miss latency
| 239system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency
240system.l2c.demand_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency
241system.l2c.demand_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency
|
242system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
| 242system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
|
243system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40048.624640 # average overall mshr miss latency
244system.l2c.overall_avg_mshr_miss_latency::cpu.data 40122.887745 # average overall mshr miss latency
245system.l2c.overall_avg_mshr_miss_latency::total 40116.672966 # average overall mshr miss latency
| 243system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40032.683798 # average overall mshr miss latency
244system.l2c.overall_avg_mshr_miss_latency::cpu.data 40119.320079 # average overall mshr miss latency
245system.l2c.overall_avg_mshr_miss_latency::total 40112.053987 # average overall mshr miss latency
|
246system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
247system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
248system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
249system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
250system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
251system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
252system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
| 246system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
247system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
248system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
249system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
250system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
251system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
252system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
253system.iocache.replacements 47504 # number of replacements
254system.iocache.tagsinuse 0.108710 # Cycle average of tags in use
| 253system.iocache.replacements 47503 # number of replacements
254system.iocache.tagsinuse 0.108785 # Cycle average of tags in use
|
255system.iocache.total_refs 0 # Total number of references to valid blocks.
| 255system.iocache.total_refs 0 # Total number of references to valid blocks.
|
256system.iocache.sampled_refs 47520 # Sample count of references to valid blocks.
| 256system.iocache.sampled_refs 47519 # Sample count of references to valid blocks.
|
257system.iocache.avg_refs 0 # Average number of references to valid blocks.
| 257system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
258system.iocache.warmup_cycle 5048944307000 # Cycle when the warmup percentage was hit.
259system.iocache.occ_blocks::pc.south_bridge.ide 0.108710 # Average occupied blocks per requestor
260system.iocache.occ_percent::pc.south_bridge.ide 0.006794 # Average percentage of cache occupancy
261system.iocache.occ_percent::total 0.006794 # Average percentage of cache occupancy
262system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses
263system.iocache.ReadReq_misses::total 839 # number of ReadReq misses
| 258system.iocache.warmup_cycle 5053216388000 # Cycle when the warmup percentage was hit.
259system.iocache.occ_blocks::pc.south_bridge.ide 0.108785 # Average occupied blocks per requestor
260system.iocache.occ_percent::pc.south_bridge.ide 0.006799 # Average percentage of cache occupancy
261system.iocache.occ_percent::total 0.006799 # Average percentage of cache occupancy
262system.iocache.ReadReq_misses::pc.south_bridge.ide 838 # number of ReadReq misses
263system.iocache.ReadReq_misses::total 838 # number of ReadReq misses
|
264system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
265system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
| 264system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
265system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
266system.iocache.demand_misses::pc.south_bridge.ide 47559 # number of demand (read+write) misses
267system.iocache.demand_misses::total 47559 # number of demand (read+write) misses
268system.iocache.overall_misses::pc.south_bridge.ide 47559 # number of overall misses
269system.iocache.overall_misses::total 47559 # number of overall misses
270system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128944932 # number of ReadReq miss cycles
271system.iocache.ReadReq_miss_latency::total 128944932 # number of ReadReq miss cycles
272system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7159405160 # number of WriteReq miss cycles
273system.iocache.WriteReq_miss_latency::total 7159405160 # number of WriteReq miss cycles
274system.iocache.demand_miss_latency::pc.south_bridge.ide 7288350092 # number of demand (read+write) miss cycles
275system.iocache.demand_miss_latency::total 7288350092 # number of demand (read+write) miss cycles
276system.iocache.overall_miss_latency::pc.south_bridge.ide 7288350092 # number of overall miss cycles
277system.iocache.overall_miss_latency::total 7288350092 # number of overall miss cycles
278system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses)
279system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses)
| 266system.iocache.demand_misses::pc.south_bridge.ide 47558 # number of demand (read+write) misses
267system.iocache.demand_misses::total 47558 # number of demand (read+write) misses
268system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses
269system.iocache.overall_misses::total 47558 # number of overall misses
270system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128838932 # number of ReadReq miss cycles
271system.iocache.ReadReq_miss_latency::total 128838932 # number of ReadReq miss cycles
272system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7147789160 # number of WriteReq miss cycles
273system.iocache.WriteReq_miss_latency::total 7147789160 # number of WriteReq miss cycles
274system.iocache.demand_miss_latency::pc.south_bridge.ide 7276628092 # number of demand (read+write) miss cycles
275system.iocache.demand_miss_latency::total 7276628092 # number of demand (read+write) miss cycles
276system.iocache.overall_miss_latency::pc.south_bridge.ide 7276628092 # number of overall miss cycles
277system.iocache.overall_miss_latency::total 7276628092 # number of overall miss cycles
278system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses)
279system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses)
|
280system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
281system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
| 280system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
281system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
282system.iocache.demand_accesses::pc.south_bridge.ide 47559 # number of demand (read+write) accesses
283system.iocache.demand_accesses::total 47559 # number of demand (read+write) accesses
284system.iocache.overall_accesses::pc.south_bridge.ide 47559 # number of overall (read+write) accesses
285system.iocache.overall_accesses::total 47559 # number of overall (read+write) accesses
| 282system.iocache.demand_accesses::pc.south_bridge.ide 47558 # number of demand (read+write) accesses
283system.iocache.demand_accesses::total 47558 # number of demand (read+write) accesses
284system.iocache.overall_accesses::pc.south_bridge.ide 47558 # number of overall (read+write) accesses
285system.iocache.overall_accesses::total 47558 # number of overall (read+write) accesses
|
286system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
287system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
288system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
289system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
290system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
291system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
292system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
293system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
| 286system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
287system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
288system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
289system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
290system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
291system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
292system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
293system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
294system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153688.834327 # average ReadReq miss latency
295system.iocache.ReadReq_avg_miss_latency::total 153688.834327 # average ReadReq miss latency
296system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 153240.692637 # average WriteReq miss latency
297system.iocache.WriteReq_avg_miss_latency::total 153240.692637 # average WriteReq miss latency
298system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153248.598415 # average overall miss latency
299system.iocache.demand_avg_miss_latency::total 153248.598415 # average overall miss latency
300system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153248.598415 # average overall miss latency
301system.iocache.overall_avg_miss_latency::total 153248.598415 # average overall miss latency
| 294system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153745.742243 # average ReadReq miss latency
295system.iocache.ReadReq_avg_miss_latency::total 153745.742243 # average ReadReq miss latency
296system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 152992.062500 # average WriteReq miss latency
297system.iocache.WriteReq_avg_miss_latency::total 152992.062500 # average WriteReq miss latency
298system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency
299system.iocache.demand_avg_miss_latency::total 153005.342781 # average overall miss latency
300system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153005.342781 # average overall miss latency
301system.iocache.overall_avg_miss_latency::total 153005.342781 # average overall miss latency
|
302system.iocache.blocked_cycles::no_mshrs 372008 # number of cycles access was blocked
303system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
304system.iocache.blocked::no_mshrs 38 # number of cycles access was blocked
305system.iocache.blocked::no_targets 0 # number of cycles access was blocked
306system.iocache.avg_blocked_cycles::no_mshrs 9789.684211 # average number of cycles each access was blocked
307system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
308system.iocache.fast_writes 0 # number of fast writes performed
309system.iocache.cache_copies 0 # number of cache copies performed
310system.iocache.writebacks::writebacks 46667 # number of writebacks
311system.iocache.writebacks::total 46667 # number of writebacks
| 302system.iocache.blocked_cycles::no_mshrs 372008 # number of cycles access was blocked
303system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
304system.iocache.blocked::no_mshrs 38 # number of cycles access was blocked
305system.iocache.blocked::no_targets 0 # number of cycles access was blocked
306system.iocache.avg_blocked_cycles::no_mshrs 9789.684211 # average number of cycles each access was blocked
307system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
308system.iocache.fast_writes 0 # number of fast writes performed
309system.iocache.cache_copies 0 # number of cache copies performed
310system.iocache.writebacks::writebacks 46667 # number of writebacks
311system.iocache.writebacks::total 46667 # number of writebacks
|
312system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses
313system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
| 312system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 838 # number of ReadReq MSHR misses
313system.iocache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses
|
314system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
315system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
| 314system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
315system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
|
316system.iocache.demand_mshr_misses::pc.south_bridge.ide 47559 # number of demand (read+write) MSHR misses
317system.iocache.demand_mshr_misses::total 47559 # number of demand (read+write) MSHR misses
318system.iocache.overall_mshr_misses::pc.south_bridge.ide 47559 # number of overall MSHR misses
319system.iocache.overall_mshr_misses::total 47559 # number of overall MSHR misses
320system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85286000 # number of ReadReq MSHR miss cycles
321system.iocache.ReadReq_mshr_miss_latency::total 85286000 # number of ReadReq MSHR miss cycles
322system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4729709976 # number of WriteReq MSHR miss cycles
323system.iocache.WriteReq_mshr_miss_latency::total 4729709976 # number of WriteReq MSHR miss cycles
324system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4814995976 # number of demand (read+write) MSHR miss cycles
325system.iocache.demand_mshr_miss_latency::total 4814995976 # number of demand (read+write) MSHR miss cycles
326system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4814995976 # number of overall MSHR miss cycles
327system.iocache.overall_mshr_miss_latency::total 4814995976 # number of overall MSHR miss cycles
| 316system.iocache.demand_mshr_misses::pc.south_bridge.ide 47558 # number of demand (read+write) MSHR misses
317system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses
318system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses
319system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses
320system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85232000 # number of ReadReq MSHR miss cycles
321system.iocache.ReadReq_mshr_miss_latency::total 85232000 # number of ReadReq MSHR miss cycles
322system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4718093984 # number of WriteReq MSHR miss cycles
323system.iocache.WriteReq_mshr_miss_latency::total 4718093984 # number of WriteReq MSHR miss cycles
324system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of demand (read+write) MSHR miss cycles
325system.iocache.demand_mshr_miss_latency::total 4803325984 # number of demand (read+write) MSHR miss cycles
326system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4803325984 # number of overall MSHR miss cycles
327system.iocache.overall_mshr_miss_latency::total 4803325984 # number of overall MSHR miss cycles
|
328system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
329system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
330system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
331system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
332system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
333system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
334system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
335system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
| 328system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
329system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
330system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
331system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
332system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
333system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
334system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
335system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
336system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101651.966627 # average ReadReq mshr miss latency
337system.iocache.ReadReq_avg_mshr_miss_latency::total 101651.966627 # average ReadReq mshr miss latency
338system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 101235.230651 # average WriteReq mshr miss latency
339system.iocache.WriteReq_avg_mshr_miss_latency::total 101235.230651 # average WriteReq mshr miss latency
340system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392 # average overall mshr miss latency
341system.iocache.demand_avg_mshr_miss_latency::total 101242.582392 # average overall mshr miss latency
342system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392 # average overall mshr miss latency
343system.iocache.overall_avg_mshr_miss_latency::total 101242.582392 # average overall mshr miss latency
| 336system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101708.830549 # average ReadReq mshr miss latency
337system.iocache.ReadReq_avg_mshr_miss_latency::total 101708.830549 # average ReadReq mshr miss latency
338system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 100986.600685 # average WriteReq mshr miss latency
339system.iocache.WriteReq_avg_mshr_miss_latency::total 100986.600685 # average WriteReq mshr miss latency
340system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency
341system.iocache.demand_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency
342system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801 # average overall mshr miss latency
343system.iocache.overall_avg_mshr_miss_latency::total 100999.326801 # average overall mshr miss latency
|
344system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
345system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
346system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
347system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
348system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
349system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
350system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
351system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
352system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
353system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
354system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
355system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
356system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
| 344system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
345system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
346system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
347system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
348system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
349system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
350system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
351system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
352system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
353system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
354system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
355system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
356system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
357system.cpu.numCycles 10383532628 # number of cpu cycles simulated
| 357system.cpu.numCycles 10392086274 # number of cpu cycles simulated
|
358system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
359system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 358system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
359system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
360system.cpu.committedInsts 138165780 # Number of instructions committed
361system.cpu.committedOps 265203824 # Number of ops (including micro ops) committed
362system.cpu.num_int_alu_accesses 249613019 # Number of integer alu accesses
| 360system.cpu.committedInsts 128236332 # Number of instructions committed
361system.cpu.committedOps 247208442 # Number of ops (including micro ops) committed
362system.cpu.num_int_alu_accesses 231946757 # Number of integer alu accesses
|
363system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
364system.cpu.num_func_calls 0 # number of times a function call or return occured
| 363system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
364system.cpu.num_func_calls 0 # number of times a function call or return occured
|
365system.cpu.num_conditional_control_insts 24887741 # number of instructions that are conditional controls
366system.cpu.num_int_insts 249613019 # number of integer instructions
| 365system.cpu.num_conditional_control_insts 23151326 # number of instructions that are conditional controls
366system.cpu.num_int_insts 231946757 # number of integer instructions
|
367system.cpu.num_fp_insts 0 # number of float instructions
| 367system.cpu.num_fp_insts 0 # number of float instructions
|
368system.cpu.num_int_register_reads 778264795 # number of times the integer registers were read
369system.cpu.num_int_register_writes 423017346 # number of times the integer registers were written
| 368system.cpu.num_int_register_reads 720715933 # number of times the integer registers were read
369system.cpu.num_int_register_writes 387556667 # number of times the integer registers were written
|
370system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
371system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
| 370system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
371system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
372system.cpu.num_mem_refs 23180616 # number of memory refs
373system.cpu.num_load_insts 14822216 # Number of load instructions
374system.cpu.num_store_insts 8358400 # Number of store instructions
375system.cpu.num_idle_cycles 9771874926.286118 # Number of idle cycles
376system.cpu.num_busy_cycles 611657701.713882 # Number of busy cycles
377system.cpu.not_idle_fraction 0.058907 # Percentage of non-idle cycles
378system.cpu.idle_fraction 0.941093 # Percentage of idle cycles
| 372system.cpu.num_mem_refs 22230275 # number of memory refs
373system.cpu.num_load_insts 13869948 # Number of load instructions
374system.cpu.num_store_insts 8360327 # Number of store instructions
375system.cpu.num_idle_cycles 9776409858.670118 # Number of idle cycles
376system.cpu.num_busy_cycles 615676415.329882 # Number of busy cycles
377system.cpu.not_idle_fraction 0.059245 # Percentage of non-idle cycles
378system.cpu.idle_fraction 0.940755 # Percentage of idle cycles
|
379system.cpu.kern.inst.arm 0 # number of arm instructions executed
380system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
| 379system.cpu.kern.inst.arm 0 # number of arm instructions executed
380system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
381system.cpu.icache.replacements 789892 # number of replacements
382system.cpu.icache.tagsinuse 510.351457 # Cycle average of tags in use
383system.cpu.icache.total_refs 158472876 # Total number of references to valid blocks.
384system.cpu.icache.sampled_refs 790404 # Sample count of references to valid blocks.
385system.cpu.icache.avg_refs 200.496045 # Average number of references to valid blocks.
386system.cpu.icache.warmup_cycle 160421909000 # Cycle when the warmup percentage was hit.
387system.cpu.icache.occ_blocks::cpu.inst 510.351457 # Average occupied blocks per requestor
388system.cpu.icache.occ_percent::cpu.inst 0.996780 # Average percentage of cache occupancy
389system.cpu.icache.occ_percent::total 0.996780 # Average percentage of cache occupancy
390system.cpu.icache.ReadReq_hits::cpu.inst 158472876 # number of ReadReq hits
391system.cpu.icache.ReadReq_hits::total 158472876 # number of ReadReq hits
392system.cpu.icache.demand_hits::cpu.inst 158472876 # number of demand (read+write) hits
393system.cpu.icache.demand_hits::total 158472876 # number of demand (read+write) hits
394system.cpu.icache.overall_hits::cpu.inst 158472876 # number of overall hits
395system.cpu.icache.overall_hits::total 158472876 # number of overall hits
396system.cpu.icache.ReadReq_misses::cpu.inst 790411 # number of ReadReq misses
397system.cpu.icache.ReadReq_misses::total 790411 # number of ReadReq misses
398system.cpu.icache.demand_misses::cpu.inst 790411 # number of demand (read+write) misses
399system.cpu.icache.demand_misses::total 790411 # number of demand (read+write) misses
400system.cpu.icache.overall_misses::cpu.inst 790411 # number of overall misses
401system.cpu.icache.overall_misses::total 790411 # number of overall misses
402system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780909500 # number of ReadReq miss cycles
403system.cpu.icache.ReadReq_miss_latency::total 11780909500 # number of ReadReq miss cycles
404system.cpu.icache.demand_miss_latency::cpu.inst 11780909500 # number of demand (read+write) miss cycles
405system.cpu.icache.demand_miss_latency::total 11780909500 # number of demand (read+write) miss cycles
406system.cpu.icache.overall_miss_latency::cpu.inst 11780909500 # number of overall miss cycles
407system.cpu.icache.overall_miss_latency::total 11780909500 # number of overall miss cycles
408system.cpu.icache.ReadReq_accesses::cpu.inst 159263287 # number of ReadReq accesses(hits+misses)
409system.cpu.icache.ReadReq_accesses::total 159263287 # number of ReadReq accesses(hits+misses)
410system.cpu.icache.demand_accesses::cpu.inst 159263287 # number of demand (read+write) accesses
411system.cpu.icache.demand_accesses::total 159263287 # number of demand (read+write) accesses
412system.cpu.icache.overall_accesses::cpu.inst 159263287 # number of overall (read+write) accesses
413system.cpu.icache.overall_accesses::total 159263287 # number of overall (read+write) accesses
414system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004963 # miss rate for ReadReq accesses
415system.cpu.icache.ReadReq_miss_rate::total 0.004963 # miss rate for ReadReq accesses
416system.cpu.icache.demand_miss_rate::cpu.inst 0.004963 # miss rate for demand accesses
417system.cpu.icache.demand_miss_rate::total 0.004963 # miss rate for demand accesses
418system.cpu.icache.overall_miss_rate::cpu.inst 0.004963 # miss rate for overall accesses
419system.cpu.icache.overall_miss_rate::total 0.004963 # miss rate for overall accesses
420system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.789407 # average ReadReq miss latency
421system.cpu.icache.ReadReq_avg_miss_latency::total 14904.789407 # average ReadReq miss latency
422system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency
423system.cpu.icache.demand_avg_miss_latency::total 14904.789407 # average overall miss latency
424system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency
425system.cpu.icache.overall_avg_miss_latency::total 14904.789407 # average overall miss latency
| 381system.cpu.icache.replacements 791983 # number of replacements
382system.cpu.icache.tagsinuse 510.339207 # Cycle average of tags in use
383system.cpu.icache.total_refs 144447737 # Total number of references to valid blocks.
384system.cpu.icache.sampled_refs 792495 # Sample count of references to valid blocks.
385system.cpu.icache.avg_refs 182.269588 # Average number of references to valid blocks.
386system.cpu.icache.warmup_cycle 160970951000 # Cycle when the warmup percentage was hit.
387system.cpu.icache.occ_blocks::cpu.inst 510.339207 # Average occupied blocks per requestor
388system.cpu.icache.occ_percent::cpu.inst 0.996756 # Average percentage of cache occupancy
389system.cpu.icache.occ_percent::total 0.996756 # Average percentage of cache occupancy
390system.cpu.icache.ReadReq_hits::cpu.inst 144447737 # number of ReadReq hits
391system.cpu.icache.ReadReq_hits::total 144447737 # number of ReadReq hits
392system.cpu.icache.demand_hits::cpu.inst 144447737 # number of demand (read+write) hits
393system.cpu.icache.demand_hits::total 144447737 # number of demand (read+write) hits
394system.cpu.icache.overall_hits::cpu.inst 144447737 # number of overall hits
395system.cpu.icache.overall_hits::total 144447737 # number of overall hits
396system.cpu.icache.ReadReq_misses::cpu.inst 792502 # number of ReadReq misses
397system.cpu.icache.ReadReq_misses::total 792502 # number of ReadReq misses
398system.cpu.icache.demand_misses::cpu.inst 792502 # number of demand (read+write) misses
399system.cpu.icache.demand_misses::total 792502 # number of demand (read+write) misses
400system.cpu.icache.overall_misses::cpu.inst 792502 # number of overall misses
401system.cpu.icache.overall_misses::total 792502 # number of overall misses
402system.cpu.icache.ReadReq_miss_latency::cpu.inst 11813272500 # number of ReadReq miss cycles
403system.cpu.icache.ReadReq_miss_latency::total 11813272500 # number of ReadReq miss cycles
404system.cpu.icache.demand_miss_latency::cpu.inst 11813272500 # number of demand (read+write) miss cycles
405system.cpu.icache.demand_miss_latency::total 11813272500 # number of demand (read+write) miss cycles
406system.cpu.icache.overall_miss_latency::cpu.inst 11813272500 # number of overall miss cycles
407system.cpu.icache.overall_miss_latency::total 11813272500 # number of overall miss cycles
408system.cpu.icache.ReadReq_accesses::cpu.inst 145240239 # number of ReadReq accesses(hits+misses)
409system.cpu.icache.ReadReq_accesses::total 145240239 # number of ReadReq accesses(hits+misses)
410system.cpu.icache.demand_accesses::cpu.inst 145240239 # number of demand (read+write) accesses
411system.cpu.icache.demand_accesses::total 145240239 # number of demand (read+write) accesses
412system.cpu.icache.overall_accesses::cpu.inst 145240239 # number of overall (read+write) accesses
413system.cpu.icache.overall_accesses::total 145240239 # number of overall (read+write) accesses
414system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005456 # miss rate for ReadReq accesses
415system.cpu.icache.ReadReq_miss_rate::total 0.005456 # miss rate for ReadReq accesses
416system.cpu.icache.demand_miss_rate::cpu.inst 0.005456 # miss rate for demand accesses
417system.cpu.icache.demand_miss_rate::total 0.005456 # miss rate for demand accesses
418system.cpu.icache.overall_miss_rate::cpu.inst 0.005456 # miss rate for overall accesses
419system.cpu.icache.overall_miss_rate::total 0.005456 # miss rate for overall accesses
420system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14906.299921 # average ReadReq miss latency
421system.cpu.icache.ReadReq_avg_miss_latency::total 14906.299921 # average ReadReq miss latency
422system.cpu.icache.demand_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency
423system.cpu.icache.demand_avg_miss_latency::total 14906.299921 # average overall miss latency
424system.cpu.icache.overall_avg_miss_latency::cpu.inst 14906.299921 # average overall miss latency
425system.cpu.icache.overall_avg_miss_latency::total 14906.299921 # average overall miss latency
|
426system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
427system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
428system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
429system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
430system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
431system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
432system.cpu.icache.fast_writes 0 # number of fast writes performed
433system.cpu.icache.cache_copies 0 # number of cache copies performed
| 426system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
427system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
428system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
429system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
430system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
431system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
432system.cpu.icache.fast_writes 0 # number of fast writes performed
433system.cpu.icache.cache_copies 0 # number of cache copies performed
|
434system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790411 # number of ReadReq MSHR misses
435system.cpu.icache.ReadReq_mshr_misses::total 790411 # number of ReadReq MSHR misses
436system.cpu.icache.demand_mshr_misses::cpu.inst 790411 # number of demand (read+write) MSHR misses
437system.cpu.icache.demand_mshr_misses::total 790411 # number of demand (read+write) MSHR misses
438system.cpu.icache.overall_mshr_misses::cpu.inst 790411 # number of overall MSHR misses
439system.cpu.icache.overall_mshr_misses::total 790411 # number of overall MSHR misses
440system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408658500 # number of ReadReq MSHR miss cycles
441system.cpu.icache.ReadReq_mshr_miss_latency::total 9408658500 # number of ReadReq MSHR miss cycles
442system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408658500 # number of demand (read+write) MSHR miss cycles
443system.cpu.icache.demand_mshr_miss_latency::total 9408658500 # number of demand (read+write) MSHR miss cycles
444system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408658500 # number of overall MSHR miss cycles
445system.cpu.icache.overall_mshr_miss_latency::total 9408658500 # number of overall MSHR miss cycles
446system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for ReadReq accesses
447system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004963 # mshr miss rate for ReadReq accesses
448system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for demand accesses
449system.cpu.icache.demand_mshr_miss_rate::total 0.004963 # mshr miss rate for demand accesses
450system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for overall accesses
451system.cpu.icache.overall_mshr_miss_rate::total 0.004963 # mshr miss rate for overall accesses
452system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.501469 # average ReadReq mshr miss latency
453system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.501469 # average ReadReq mshr miss latency
454system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency
455system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency
456system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency
457system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency
| 434system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792502 # number of ReadReq MSHR misses
435system.cpu.icache.ReadReq_mshr_misses::total 792502 # number of ReadReq MSHR misses
436system.cpu.icache.demand_mshr_misses::cpu.inst 792502 # number of demand (read+write) MSHR misses
437system.cpu.icache.demand_mshr_misses::total 792502 # number of demand (read+write) MSHR misses
438system.cpu.icache.overall_mshr_misses::cpu.inst 792502 # number of overall MSHR misses
439system.cpu.icache.overall_mshr_misses::total 792502 # number of overall MSHR misses
440system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9434751000 # number of ReadReq MSHR miss cycles
441system.cpu.icache.ReadReq_mshr_miss_latency::total 9434751000 # number of ReadReq MSHR miss cycles
442system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9434751000 # number of demand (read+write) MSHR miss cycles
443system.cpu.icache.demand_mshr_miss_latency::total 9434751000 # number of demand (read+write) MSHR miss cycles
444system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9434751000 # number of overall MSHR miss cycles
445system.cpu.icache.overall_mshr_miss_latency::total 9434751000 # number of overall MSHR miss cycles
446system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for ReadReq accesses
447system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005456 # mshr miss rate for ReadReq accesses
448system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for demand accesses
449system.cpu.icache.demand_mshr_miss_rate::total 0.005456 # mshr miss rate for demand accesses
450system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005456 # mshr miss rate for overall accesses
451system.cpu.icache.overall_mshr_miss_rate::total 0.005456 # mshr miss rate for overall accesses
452system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11905.018536 # average ReadReq mshr miss latency
453system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11905.018536 # average ReadReq mshr miss latency
454system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency
455system.cpu.icache.demand_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency
456system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11905.018536 # average overall mshr miss latency
457system.cpu.icache.overall_avg_mshr_miss_latency::total 11905.018536 # average overall mshr miss latency
|
458system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
| 458system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
459system.cpu.itb_walker_cache.replacements 3403 # number of replacements
460system.cpu.itb_walker_cache.tagsinuse 3.070913 # Cycle average of tags in use
461system.cpu.itb_walker_cache.total_refs 8040 # Total number of references to valid blocks.
462system.cpu.itb_walker_cache.sampled_refs 3415 # Sample count of references to valid blocks.
463system.cpu.itb_walker_cache.avg_refs 2.354319 # Average number of references to valid blocks.
464system.cpu.itb_walker_cache.warmup_cycle 5164836918000 # Cycle when the warmup percentage was hit.
465system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070913 # Average occupied blocks per requestor
466system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191932 # Average percentage of cache occupancy
467system.cpu.itb_walker_cache.occ_percent::total 0.191932 # Average percentage of cache occupancy
468system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8060 # number of ReadReq hits
469system.cpu.itb_walker_cache.ReadReq_hits::total 8060 # number of ReadReq hits
| 459system.cpu.itb_walker_cache.replacements 3538 # number of replacements
460system.cpu.itb_walker_cache.tagsinuse 3.068811 # Cycle average of tags in use
461system.cpu.itb_walker_cache.total_refs 7893 # Total number of references to valid blocks.
462system.cpu.itb_walker_cache.sampled_refs 3550 # Sample count of references to valid blocks.
463system.cpu.itb_walker_cache.avg_refs 2.223380 # Average number of references to valid blocks.
464system.cpu.itb_walker_cache.warmup_cycle 5169410055000 # Cycle when the warmup percentage was hit.
465system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.068811 # Average occupied blocks per requestor
466system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191801 # Average percentage of cache occupancy
467system.cpu.itb_walker_cache.occ_percent::total 0.191801 # Average percentage of cache occupancy
468system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7916 # number of ReadReq hits
469system.cpu.itb_walker_cache.ReadReq_hits::total 7916 # number of ReadReq hits
|
470system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
471system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
| 470system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
471system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
472system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8062 # number of demand (read+write) hits
473system.cpu.itb_walker_cache.demand_hits::total 8062 # number of demand (read+write) hits
474system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8062 # number of overall hits
475system.cpu.itb_walker_cache.overall_hits::total 8062 # number of overall hits
476system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4266 # number of ReadReq misses
477system.cpu.itb_walker_cache.ReadReq_misses::total 4266 # number of ReadReq misses
478system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4266 # number of demand (read+write) misses
479system.cpu.itb_walker_cache.demand_misses::total 4266 # number of demand (read+write) misses
480system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4266 # number of overall misses
481system.cpu.itb_walker_cache.overall_misses::total 4266 # number of overall misses
482system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50418000 # number of ReadReq miss cycles
483system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50418000 # number of ReadReq miss cycles
484system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50418000 # number of demand (read+write) miss cycles
485system.cpu.itb_walker_cache.demand_miss_latency::total 50418000 # number of demand (read+write) miss cycles
486system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50418000 # number of overall miss cycles
487system.cpu.itb_walker_cache.overall_miss_latency::total 50418000 # number of overall miss cycles
488system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12326 # number of ReadReq accesses(hits+misses)
489system.cpu.itb_walker_cache.ReadReq_accesses::total 12326 # number of ReadReq accesses(hits+misses)
| 472system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7918 # number of demand (read+write) hits
473system.cpu.itb_walker_cache.demand_hits::total 7918 # number of demand (read+write) hits
474system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7918 # number of overall hits
475system.cpu.itb_walker_cache.overall_hits::total 7918 # number of overall hits
476system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4398 # number of ReadReq misses
477system.cpu.itb_walker_cache.ReadReq_misses::total 4398 # number of ReadReq misses
478system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4398 # number of demand (read+write) misses
479system.cpu.itb_walker_cache.demand_misses::total 4398 # number of demand (read+write) misses
480system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4398 # number of overall misses
481system.cpu.itb_walker_cache.overall_misses::total 4398 # number of overall misses
482system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51351000 # number of ReadReq miss cycles
483system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51351000 # number of ReadReq miss cycles
484system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51351000 # number of demand (read+write) miss cycles
485system.cpu.itb_walker_cache.demand_miss_latency::total 51351000 # number of demand (read+write) miss cycles
486system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51351000 # number of overall miss cycles
487system.cpu.itb_walker_cache.overall_miss_latency::total 51351000 # number of overall miss cycles
488system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12314 # number of ReadReq accesses(hits+misses)
489system.cpu.itb_walker_cache.ReadReq_accesses::total 12314 # number of ReadReq accesses(hits+misses)
|
490system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
491system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
| 490system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
491system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
492system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12328 # number of demand (read+write) accesses
493system.cpu.itb_walker_cache.demand_accesses::total 12328 # number of demand (read+write) accesses
494system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12328 # number of overall (read+write) accesses
495system.cpu.itb_walker_cache.overall_accesses::total 12328 # number of overall (read+write) accesses
496system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.346098 # miss rate for ReadReq accesses
497system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.346098 # miss rate for ReadReq accesses
498system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.346042 # miss rate for demand accesses
499system.cpu.itb_walker_cache.demand_miss_rate::total 0.346042 # miss rate for demand accesses
500system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.346042 # miss rate for overall accesses
501system.cpu.itb_walker_cache.overall_miss_rate::total 0.346042 # miss rate for overall accesses
502system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11818.565401 # average ReadReq miss latency
503system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11818.565401 # average ReadReq miss latency
504system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11818.565401 # average overall miss latency
505system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11818.565401 # average overall miss latency
506system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11818.565401 # average overall miss latency
507system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11818.565401 # average overall miss latency
| 492system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12316 # number of demand (read+write) accesses
493system.cpu.itb_walker_cache.demand_accesses::total 12316 # number of demand (read+write) accesses
494system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12316 # number of overall (read+write) accesses
495system.cpu.itb_walker_cache.overall_accesses::total 12316 # number of overall (read+write) accesses
496system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.357154 # miss rate for ReadReq accesses
497system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.357154 # miss rate for ReadReq accesses
498system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.357096 # miss rate for demand accesses
499system.cpu.itb_walker_cache.demand_miss_rate::total 0.357096 # miss rate for demand accesses
500system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.357096 # miss rate for overall accesses
501system.cpu.itb_walker_cache.overall_miss_rate::total 0.357096 # miss rate for overall accesses
502system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11675.989086 # average ReadReq miss latency
503system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11675.989086 # average ReadReq miss latency
504system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency
505system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11675.989086 # average overall miss latency
506system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11675.989086 # average overall miss latency
507system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11675.989086 # average overall miss latency
|
508system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
509system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
510system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
511system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
512system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
513system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
514system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
515system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
| 508system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
509system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
510system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
511system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
512system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
513system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
514system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
515system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
516system.cpu.itb_walker_cache.writebacks::writebacks 726 # number of writebacks
517system.cpu.itb_walker_cache.writebacks::total 726 # number of writebacks
518system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4266 # number of ReadReq MSHR misses
519system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4266 # number of ReadReq MSHR misses
520system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4266 # number of demand (read+write) MSHR misses
521system.cpu.itb_walker_cache.demand_mshr_misses::total 4266 # number of demand (read+write) MSHR misses
522system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4266 # number of overall MSHR misses
523system.cpu.itb_walker_cache.overall_mshr_misses::total 4266 # number of overall MSHR misses
524system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37620000 # number of ReadReq MSHR miss cycles
525system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37620000 # number of ReadReq MSHR miss cycles
526system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37620000 # number of demand (read+write) MSHR miss cycles
527system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37620000 # number of demand (read+write) MSHR miss cycles
528system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37620000 # number of overall MSHR miss cycles
529system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37620000 # number of overall MSHR miss cycles
530system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.346098 # mshr miss rate for ReadReq accesses
531system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.346098 # mshr miss rate for ReadReq accesses
532system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.346042 # mshr miss rate for demand accesses
533system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.346042 # mshr miss rate for demand accesses
534system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.346042 # mshr miss rate for overall accesses
535system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.346042 # mshr miss rate for overall accesses
536system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average ReadReq mshr miss latency
537system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8818.565401 # average ReadReq mshr miss latency
538system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average overall mshr miss latency
539system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8818.565401 # average overall mshr miss latency
540system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average overall mshr miss latency
541system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8818.565401 # average overall mshr miss latency
| 516system.cpu.itb_walker_cache.writebacks::writebacks 656 # number of writebacks
517system.cpu.itb_walker_cache.writebacks::total 656 # number of writebacks
518system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4398 # number of ReadReq MSHR misses
519system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4398 # number of ReadReq MSHR misses
520system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4398 # number of demand (read+write) MSHR misses
521system.cpu.itb_walker_cache.demand_mshr_misses::total 4398 # number of demand (read+write) MSHR misses
522system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4398 # number of overall MSHR misses
523system.cpu.itb_walker_cache.overall_mshr_misses::total 4398 # number of overall MSHR misses
524system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38157000 # number of ReadReq MSHR miss cycles
525system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38157000 # number of ReadReq MSHR miss cycles
526system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38157000 # number of demand (read+write) MSHR miss cycles
527system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38157000 # number of demand (read+write) MSHR miss cycles
528system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38157000 # number of overall MSHR miss cycles
529system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38157000 # number of overall MSHR miss cycles
530system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.357154 # mshr miss rate for ReadReq accesses
531system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.357154 # mshr miss rate for ReadReq accesses
532system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for demand accesses
533system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.357096 # mshr miss rate for demand accesses
534system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.357096 # mshr miss rate for overall accesses
535system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.357096 # mshr miss rate for overall accesses
536system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average ReadReq mshr miss latency
537system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8675.989086 # average ReadReq mshr miss latency
538system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency
539system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency
540system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8675.989086 # average overall mshr miss latency
541system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8675.989086 # average overall mshr miss latency
|
542system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 542system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
543system.cpu.dtb_walker_cache.replacements 7529 # number of replacements
544system.cpu.dtb_walker_cache.tagsinuse 5.053120 # Cycle average of tags in use
545system.cpu.dtb_walker_cache.total_refs 13331 # Total number of references to valid blocks.
546system.cpu.dtb_walker_cache.sampled_refs 7543 # Sample count of references to valid blocks.
547system.cpu.dtb_walker_cache.avg_refs 1.767334 # Average number of references to valid blocks.
548system.cpu.dtb_walker_cache.warmup_cycle 5161009077000 # Cycle when the warmup percentage was hit.
549system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053120 # Average occupied blocks per requestor
550system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315820 # Average percentage of cache occupancy
551system.cpu.dtb_walker_cache.occ_percent::total 0.315820 # Average percentage of cache occupancy
552system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13332 # number of ReadReq hits
553system.cpu.dtb_walker_cache.ReadReq_hits::total 13332 # number of ReadReq hits
554system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13332 # number of demand (read+write) hits
555system.cpu.dtb_walker_cache.demand_hits::total 13332 # number of demand (read+write) hits
556system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13332 # number of overall hits
557system.cpu.dtb_walker_cache.overall_hits::total 13332 # number of overall hits
558system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8729 # number of ReadReq misses
559system.cpu.dtb_walker_cache.ReadReq_misses::total 8729 # number of ReadReq misses
560system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8729 # number of demand (read+write) misses
561system.cpu.dtb_walker_cache.demand_misses::total 8729 # number of demand (read+write) misses
562system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8729 # number of overall misses
563system.cpu.dtb_walker_cache.overall_misses::total 8729 # number of overall misses
564system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 112265000 # number of ReadReq miss cycles
565system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 112265000 # number of ReadReq miss cycles
566system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 112265000 # number of demand (read+write) miss cycles
567system.cpu.dtb_walker_cache.demand_miss_latency::total 112265000 # number of demand (read+write) miss cycles
568system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 112265000 # number of overall miss cycles
569system.cpu.dtb_walker_cache.overall_miss_latency::total 112265000 # number of overall miss cycles
570system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22061 # number of ReadReq accesses(hits+misses)
571system.cpu.dtb_walker_cache.ReadReq_accesses::total 22061 # number of ReadReq accesses(hits+misses)
572system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22061 # number of demand (read+write) accesses
573system.cpu.dtb_walker_cache.demand_accesses::total 22061 # number of demand (read+write) accesses
574system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22061 # number of overall (read+write) accesses
575system.cpu.dtb_walker_cache.overall_accesses::total 22061 # number of overall (read+write) accesses
576system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395676 # miss rate for ReadReq accesses
577system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395676 # miss rate for ReadReq accesses
578system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395676 # miss rate for demand accesses
579system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395676 # miss rate for demand accesses
580system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395676 # miss rate for overall accesses
581system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395676 # miss rate for overall accesses
582system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12861.152480 # average ReadReq miss latency
583system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12861.152480 # average ReadReq miss latency
584system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12861.152480 # average overall miss latency
585system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12861.152480 # average overall miss latency
586system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12861.152480 # average overall miss latency
587system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12861.152480 # average overall miss latency
| 543system.cpu.dtb_walker_cache.replacements 7615 # number of replacements
544system.cpu.dtb_walker_cache.tagsinuse 5.050606 # Cycle average of tags in use
545system.cpu.dtb_walker_cache.total_refs 13416 # Total number of references to valid blocks.
546system.cpu.dtb_walker_cache.sampled_refs 7630 # Sample count of references to valid blocks.
547system.cpu.dtb_walker_cache.avg_refs 1.758322 # Average number of references to valid blocks.
548system.cpu.dtb_walker_cache.warmup_cycle 5165509990000 # Cycle when the warmup percentage was hit.
549system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050606 # Average occupied blocks per requestor
550system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315663 # Average percentage of cache occupancy
551system.cpu.dtb_walker_cache.occ_percent::total 0.315663 # Average percentage of cache occupancy
552system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13416 # number of ReadReq hits
553system.cpu.dtb_walker_cache.ReadReq_hits::total 13416 # number of ReadReq hits
554system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13416 # number of demand (read+write) hits
555system.cpu.dtb_walker_cache.demand_hits::total 13416 # number of demand (read+write) hits
556system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13416 # number of overall hits
557system.cpu.dtb_walker_cache.overall_hits::total 13416 # number of overall hits
558system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8830 # number of ReadReq misses
559system.cpu.dtb_walker_cache.ReadReq_misses::total 8830 # number of ReadReq misses
560system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8830 # number of demand (read+write) misses
561system.cpu.dtb_walker_cache.demand_misses::total 8830 # number of demand (read+write) misses
562system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8830 # number of overall misses
563system.cpu.dtb_walker_cache.overall_misses::total 8830 # number of overall misses
564system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 114790500 # number of ReadReq miss cycles
565system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 114790500 # number of ReadReq miss cycles
566system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 114790500 # number of demand (read+write) miss cycles
567system.cpu.dtb_walker_cache.demand_miss_latency::total 114790500 # number of demand (read+write) miss cycles
568system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 114790500 # number of overall miss cycles
569system.cpu.dtb_walker_cache.overall_miss_latency::total 114790500 # number of overall miss cycles
570system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22246 # number of ReadReq accesses(hits+misses)
571system.cpu.dtb_walker_cache.ReadReq_accesses::total 22246 # number of ReadReq accesses(hits+misses)
572system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22246 # number of demand (read+write) accesses
573system.cpu.dtb_walker_cache.demand_accesses::total 22246 # number of demand (read+write) accesses
574system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22246 # number of overall (read+write) accesses
575system.cpu.dtb_walker_cache.overall_accesses::total 22246 # number of overall (read+write) accesses
576system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.396925 # miss rate for ReadReq accesses
577system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.396925 # miss rate for ReadReq accesses
578system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.396925 # miss rate for demand accesses
579system.cpu.dtb_walker_cache.demand_miss_rate::total 0.396925 # miss rate for demand accesses
580system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.396925 # miss rate for overall accesses
581system.cpu.dtb_walker_cache.overall_miss_rate::total 0.396925 # miss rate for overall accesses
582system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13000.056625 # average ReadReq miss latency
583system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13000.056625 # average ReadReq miss latency
584system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency
585system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13000.056625 # average overall miss latency
586system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13000.056625 # average overall miss latency
587system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13000.056625 # average overall miss latency
|
588system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
589system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
590system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
591system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
592system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
593system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
594system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
595system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
| 588system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
589system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
590system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
591system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
592system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
593system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
594system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
595system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
596system.cpu.dtb_walker_cache.writebacks::writebacks 2916 # number of writebacks
597system.cpu.dtb_walker_cache.writebacks::total 2916 # number of writebacks
598system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8729 # number of ReadReq MSHR misses
599system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8729 # number of ReadReq MSHR misses
600system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8729 # number of demand (read+write) MSHR misses
601system.cpu.dtb_walker_cache.demand_mshr_misses::total 8729 # number of demand (read+write) MSHR misses
602system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8729 # number of overall MSHR misses
603system.cpu.dtb_walker_cache.overall_mshr_misses::total 8729 # number of overall MSHR misses
604system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 86078000 # number of ReadReq MSHR miss cycles
605system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 86078000 # number of ReadReq MSHR miss cycles
606system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 86078000 # number of demand (read+write) MSHR miss cycles
607system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 86078000 # number of demand (read+write) MSHR miss cycles
608system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 86078000 # number of overall MSHR miss cycles
609system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 86078000 # number of overall MSHR miss cycles
610system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for ReadReq accesses
611system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395676 # mshr miss rate for ReadReq accesses
612system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for demand accesses
613system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395676 # mshr miss rate for demand accesses
614system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for overall accesses
615system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395676 # mshr miss rate for overall accesses
616system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average ReadReq mshr miss latency
617system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9861.152480 # average ReadReq mshr miss latency
618system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency
619system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency
620system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency
621system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency
| 596system.cpu.dtb_walker_cache.writebacks::writebacks 3005 # number of writebacks
597system.cpu.dtb_walker_cache.writebacks::total 3005 # number of writebacks
598system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8830 # number of ReadReq MSHR misses
599system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8830 # number of ReadReq MSHR misses
600system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8830 # number of demand (read+write) MSHR misses
601system.cpu.dtb_walker_cache.demand_mshr_misses::total 8830 # number of demand (read+write) MSHR misses
602system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8830 # number of overall MSHR misses
603system.cpu.dtb_walker_cache.overall_mshr_misses::total 8830 # number of overall MSHR misses
604system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88300000 # number of ReadReq MSHR miss cycles
605system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88300000 # number of ReadReq MSHR miss cycles
606system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88300000 # number of demand (read+write) MSHR miss cycles
607system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88300000 # number of demand (read+write) MSHR miss cycles
608system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88300000 # number of overall MSHR miss cycles
609system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88300000 # number of overall MSHR miss cycles
610system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for ReadReq accesses
611system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.396925 # mshr miss rate for ReadReq accesses
612system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for demand accesses
613system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.396925 # mshr miss rate for demand accesses
614system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.396925 # mshr miss rate for overall accesses
615system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.396925 # mshr miss rate for overall accesses
616system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average ReadReq mshr miss latency
617system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10000 # average ReadReq mshr miss latency
618system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency
619system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency
620system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10000 # average overall mshr miss latency
621system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10000 # average overall mshr miss latency
|
622system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 622system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
623system.cpu.dcache.replacements 1620698 # number of replacements
624system.cpu.dcache.tagsinuse 511.997463 # Cycle average of tags in use
625system.cpu.dcache.total_refs 20024816 # Total number of references to valid blocks.
626system.cpu.dcache.sampled_refs 1621210 # Sample count of references to valid blocks.
627system.cpu.dcache.avg_refs 12.351772 # Average number of references to valid blocks.
| 623system.cpu.dcache.replacements 1622589 # number of replacements
624system.cpu.dcache.tagsinuse 511.997330 # Cycle average of tags in use
625system.cpu.dcache.total_refs 20023565 # Total number of references to valid blocks.
626system.cpu.dcache.sampled_refs 1623101 # Sample count of references to valid blocks.
627system.cpu.dcache.avg_refs 12.336611 # Average number of references to valid blocks.
|
628system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit.
| 628system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit.
|
629system.cpu.dcache.occ_blocks::cpu.data 511.997463 # Average occupied blocks per requestor
| 629system.cpu.dcache.occ_blocks::cpu.data 511.997330 # Average occupied blocks per requestor
|
630system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
631system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
| 630system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
631system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
|
632system.cpu.dcache.ReadReq_hits::cpu.data 11989143 # number of ReadReq hits
633system.cpu.dcache.ReadReq_hits::total 11989143 # number of ReadReq hits
634system.cpu.dcache.WriteReq_hits::cpu.data 8033492 # number of WriteReq hits
635system.cpu.dcache.WriteReq_hits::total 8033492 # number of WriteReq hits
636system.cpu.dcache.demand_hits::cpu.data 20022635 # number of demand (read+write) hits
637system.cpu.dcache.demand_hits::total 20022635 # number of demand (read+write) hits
638system.cpu.dcache.overall_hits::cpu.data 20022635 # number of overall hits
639system.cpu.dcache.overall_hits::total 20022635 # number of overall hits
640system.cpu.dcache.ReadReq_misses::cpu.data 1308550 # number of ReadReq misses
641system.cpu.dcache.ReadReq_misses::total 1308550 # number of ReadReq misses
642system.cpu.dcache.WriteReq_misses::cpu.data 314872 # number of WriteReq misses
643system.cpu.dcache.WriteReq_misses::total 314872 # number of WriteReq misses
644system.cpu.dcache.demand_misses::cpu.data 1623422 # number of demand (read+write) misses
645system.cpu.dcache.demand_misses::total 1623422 # number of demand (read+write) misses
646system.cpu.dcache.overall_misses::cpu.data 1623422 # number of overall misses
647system.cpu.dcache.overall_misses::total 1623422 # number of overall misses
648system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872663500 # number of ReadReq miss cycles
649system.cpu.dcache.ReadReq_miss_latency::total 19872663500 # number of ReadReq miss cycles
650system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327755500 # number of WriteReq miss cycles
651system.cpu.dcache.WriteReq_miss_latency::total 9327755500 # number of WriteReq miss cycles
652system.cpu.dcache.demand_miss_latency::cpu.data 29200419000 # number of demand (read+write) miss cycles
653system.cpu.dcache.demand_miss_latency::total 29200419000 # number of demand (read+write) miss cycles
654system.cpu.dcache.overall_miss_latency::cpu.data 29200419000 # number of overall miss cycles
655system.cpu.dcache.overall_miss_latency::total 29200419000 # number of overall miss cycles
656system.cpu.dcache.ReadReq_accesses::cpu.data 13297693 # number of ReadReq accesses(hits+misses)
657system.cpu.dcache.ReadReq_accesses::total 13297693 # number of ReadReq accesses(hits+misses)
658system.cpu.dcache.WriteReq_accesses::cpu.data 8348364 # number of WriteReq accesses(hits+misses)
659system.cpu.dcache.WriteReq_accesses::total 8348364 # number of WriteReq accesses(hits+misses)
660system.cpu.dcache.demand_accesses::cpu.data 21646057 # number of demand (read+write) accesses
661system.cpu.dcache.demand_accesses::total 21646057 # number of demand (read+write) accesses
662system.cpu.dcache.overall_accesses::cpu.data 21646057 # number of overall (read+write) accesses
663system.cpu.dcache.overall_accesses::total 21646057 # number of overall (read+write) accesses
664system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098404 # miss rate for ReadReq accesses
665system.cpu.dcache.ReadReq_miss_rate::total 0.098404 # miss rate for ReadReq accesses
666system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037717 # miss rate for WriteReq accesses
667system.cpu.dcache.WriteReq_miss_rate::total 0.037717 # miss rate for WriteReq accesses
668system.cpu.dcache.demand_miss_rate::cpu.data 0.074999 # miss rate for demand accesses
669system.cpu.dcache.demand_miss_rate::total 0.074999 # miss rate for demand accesses
670system.cpu.dcache.overall_miss_rate::cpu.data 0.074999 # miss rate for overall accesses
671system.cpu.dcache.overall_miss_rate::total 0.074999 # miss rate for overall accesses
672system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.781934 # average ReadReq miss latency
673system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.781934 # average ReadReq miss latency
674system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.959895 # average WriteReq miss latency
675system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.959895 # average WriteReq miss latency
676system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency
677system.cpu.dcache.demand_avg_miss_latency::total 17986.955333 # average overall miss latency
678system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency
679system.cpu.dcache.overall_avg_miss_latency::total 17986.955333 # average overall miss latency
| 632system.cpu.dcache.ReadReq_hits::cpu.data 11986605 # number of ReadReq hits
633system.cpu.dcache.ReadReq_hits::total 11986605 # number of ReadReq hits
634system.cpu.dcache.WriteReq_hits::cpu.data 8034775 # number of WriteReq hits
635system.cpu.dcache.WriteReq_hits::total 8034775 # number of WriteReq hits
636system.cpu.dcache.demand_hits::cpu.data 20021380 # number of demand (read+write) hits
637system.cpu.dcache.demand_hits::total 20021380 # number of demand (read+write) hits
638system.cpu.dcache.overall_hits::cpu.data 20021380 # number of overall hits
639system.cpu.dcache.overall_hits::total 20021380 # number of overall hits
640system.cpu.dcache.ReadReq_misses::cpu.data 1309816 # number of ReadReq misses
641system.cpu.dcache.ReadReq_misses::total 1309816 # number of ReadReq misses
642system.cpu.dcache.WriteReq_misses::cpu.data 315519 # number of WriteReq misses
643system.cpu.dcache.WriteReq_misses::total 315519 # number of WriteReq misses
644system.cpu.dcache.demand_misses::cpu.data 1625335 # number of demand (read+write) misses
645system.cpu.dcache.demand_misses::total 1625335 # number of demand (read+write) misses
646system.cpu.dcache.overall_misses::cpu.data 1625335 # number of overall misses
647system.cpu.dcache.overall_misses::total 1625335 # number of overall misses
648system.cpu.dcache.ReadReq_miss_latency::cpu.data 19889195500 # number of ReadReq miss cycles
649system.cpu.dcache.ReadReq_miss_latency::total 19889195500 # number of ReadReq miss cycles
650system.cpu.dcache.WriteReq_miss_latency::cpu.data 9348149500 # number of WriteReq miss cycles
651system.cpu.dcache.WriteReq_miss_latency::total 9348149500 # number of WriteReq miss cycles
652system.cpu.dcache.demand_miss_latency::cpu.data 29237345000 # number of demand (read+write) miss cycles
653system.cpu.dcache.demand_miss_latency::total 29237345000 # number of demand (read+write) miss cycles
654system.cpu.dcache.overall_miss_latency::cpu.data 29237345000 # number of overall miss cycles
655system.cpu.dcache.overall_miss_latency::total 29237345000 # number of overall miss cycles
656system.cpu.dcache.ReadReq_accesses::cpu.data 13296421 # number of ReadReq accesses(hits+misses)
657system.cpu.dcache.ReadReq_accesses::total 13296421 # number of ReadReq accesses(hits+misses)
658system.cpu.dcache.WriteReq_accesses::cpu.data 8350294 # number of WriteReq accesses(hits+misses)
659system.cpu.dcache.WriteReq_accesses::total 8350294 # number of WriteReq accesses(hits+misses)
660system.cpu.dcache.demand_accesses::cpu.data 21646715 # number of demand (read+write) accesses
661system.cpu.dcache.demand_accesses::total 21646715 # number of demand (read+write) accesses
662system.cpu.dcache.overall_accesses::cpu.data 21646715 # number of overall (read+write) accesses
663system.cpu.dcache.overall_accesses::total 21646715 # number of overall (read+write) accesses
664system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098509 # miss rate for ReadReq accesses
665system.cpu.dcache.ReadReq_miss_rate::total 0.098509 # miss rate for ReadReq accesses
666system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037785 # miss rate for WriteReq accesses
667system.cpu.dcache.WriteReq_miss_rate::total 0.037785 # miss rate for WriteReq accesses
668system.cpu.dcache.demand_miss_rate::cpu.data 0.075085 # miss rate for demand accesses
669system.cpu.dcache.demand_miss_rate::total 0.075085 # miss rate for demand accesses
670system.cpu.dcache.overall_miss_rate::cpu.data 0.075085 # miss rate for overall accesses
671system.cpu.dcache.overall_miss_rate::total 0.075085 # miss rate for overall accesses
672system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15184.724801 # average ReadReq miss latency
673system.cpu.dcache.ReadReq_avg_miss_latency::total 15184.724801 # average ReadReq miss latency
674system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29627.849670 # average WriteReq miss latency
675system.cpu.dcache.WriteReq_avg_miss_latency::total 29627.849670 # average WriteReq miss latency
676system.cpu.dcache.demand_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency
677system.cpu.dcache.demand_avg_miss_latency::total 17988.503908 # average overall miss latency
678system.cpu.dcache.overall_avg_miss_latency::cpu.data 17988.503908 # average overall miss latency
679system.cpu.dcache.overall_avg_miss_latency::total 17988.503908 # average overall miss latency
|
680system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
681system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
682system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
683system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
684system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
685system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
686system.cpu.dcache.fast_writes 0 # number of fast writes performed
687system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 680system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
681system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
682system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
683system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
684system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
685system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
686system.cpu.dcache.fast_writes 0 # number of fast writes performed
687system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
688system.cpu.dcache.writebacks::writebacks 1537687 # number of writebacks
689system.cpu.dcache.writebacks::total 1537687 # number of writebacks
690system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308550 # number of ReadReq MSHR misses
691system.cpu.dcache.ReadReq_mshr_misses::total 1308550 # number of ReadReq MSHR misses
692system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314872 # number of WriteReq MSHR misses
693system.cpu.dcache.WriteReq_mshr_misses::total 314872 # number of WriteReq MSHR misses
694system.cpu.dcache.demand_mshr_misses::cpu.data 1623422 # number of demand (read+write) MSHR misses
695system.cpu.dcache.demand_mshr_misses::total 1623422 # number of demand (read+write) MSHR misses
696system.cpu.dcache.overall_mshr_misses::cpu.data 1623422 # number of overall MSHR misses
697system.cpu.dcache.overall_mshr_misses::total 1623422 # number of overall MSHR misses
698system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15946963002 # number of ReadReq MSHR miss cycles
699system.cpu.dcache.ReadReq_mshr_miss_latency::total 15946963002 # number of ReadReq MSHR miss cycles
700system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8383136001 # number of WriteReq MSHR miss cycles
701system.cpu.dcache.WriteReq_mshr_miss_latency::total 8383136001 # number of WriteReq MSHR miss cycles
702system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24330099003 # number of demand (read+write) MSHR miss cycles
703system.cpu.dcache.demand_mshr_miss_latency::total 24330099003 # number of demand (read+write) MSHR miss cycles
704system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330099003 # number of overall MSHR miss cycles
705system.cpu.dcache.overall_mshr_miss_latency::total 24330099003 # number of overall MSHR miss cycles
706system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75924400500 # number of ReadReq MSHR uncacheable cycles
707system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75924400500 # number of ReadReq MSHR uncacheable cycles
708system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1366040500 # number of WriteReq MSHR uncacheable cycles
709system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1366040500 # number of WriteReq MSHR uncacheable cycles
710system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77290441000 # number of overall MSHR uncacheable cycles
711system.cpu.dcache.overall_mshr_uncacheable_latency::total 77290441000 # number of overall MSHR uncacheable cycles
712system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098404 # mshr miss rate for ReadReq accesses
713system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098404 # mshr miss rate for ReadReq accesses
714system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037717 # mshr miss rate for WriteReq accesses
715system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037717 # mshr miss rate for WriteReq accesses
716system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for demand accesses
717system.cpu.dcache.demand_mshr_miss_rate::total 0.074999 # mshr miss rate for demand accesses
718system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for overall accesses
719system.cpu.dcache.overall_mshr_miss_rate::total 0.074999 # mshr miss rate for overall accesses
720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.743343 # average ReadReq mshr miss latency
721system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.743343 # average ReadReq mshr miss latency
722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.948782 # average WriteReq mshr miss latency
723system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.948782 # average WriteReq mshr miss latency
724system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency
725system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency
726system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency
727system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency
| 688system.cpu.dcache.writebacks::writebacks 1540096 # number of writebacks
689system.cpu.dcache.writebacks::total 1540096 # number of writebacks
690system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309816 # number of ReadReq MSHR misses
691system.cpu.dcache.ReadReq_mshr_misses::total 1309816 # number of ReadReq MSHR misses
692system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315519 # number of WriteReq MSHR misses
693system.cpu.dcache.WriteReq_mshr_misses::total 315519 # number of WriteReq MSHR misses
694system.cpu.dcache.demand_mshr_misses::cpu.data 1625335 # number of demand (read+write) MSHR misses
695system.cpu.dcache.demand_mshr_misses::total 1625335 # number of demand (read+write) MSHR misses
696system.cpu.dcache.overall_mshr_misses::cpu.data 1625335 # number of overall MSHR misses
697system.cpu.dcache.overall_mshr_misses::total 1625335 # number of overall MSHR misses
698system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15959698500 # number of ReadReq MSHR miss cycles
699system.cpu.dcache.ReadReq_mshr_miss_latency::total 15959698500 # number of ReadReq MSHR miss cycles
700system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401590001 # number of WriteReq MSHR miss cycles
701system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401590001 # number of WriteReq MSHR miss cycles
702system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24361288501 # number of demand (read+write) MSHR miss cycles
703system.cpu.dcache.demand_mshr_miss_latency::total 24361288501 # number of demand (read+write) MSHR miss cycles
704system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24361288501 # number of overall MSHR miss cycles
705system.cpu.dcache.overall_mshr_miss_latency::total 24361288501 # number of overall MSHR miss cycles
706system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 93628676500 # number of ReadReq MSHR uncacheable cycles
707system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 93628676500 # number of ReadReq MSHR uncacheable cycles
708system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467826500 # number of WriteReq MSHR uncacheable cycles
709system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467826500 # number of WriteReq MSHR uncacheable cycles
710system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96096503000 # number of overall MSHR uncacheable cycles
711system.cpu.dcache.overall_mshr_uncacheable_latency::total 96096503000 # number of overall MSHR uncacheable cycles
712system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098509 # mshr miss rate for ReadReq accesses
713system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098509 # mshr miss rate for ReadReq accesses
714system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037785 # mshr miss rate for WriteReq accesses
715system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037785 # mshr miss rate for WriteReq accesses
716system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for demand accesses
717system.cpu.dcache.demand_mshr_miss_rate::total 0.075085 # mshr miss rate for demand accesses
718system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075085 # mshr miss rate for overall accesses
719system.cpu.dcache.overall_mshr_miss_rate::total 0.075085 # mshr miss rate for overall accesses
720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12184.687391 # average ReadReq mshr miss latency
721system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12184.687391 # average ReadReq mshr miss latency
722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26627.841750 # average WriteReq mshr miss latency
723system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26627.841750 # average WriteReq mshr miss latency
724system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency
725system.cpu.dcache.demand_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency
726system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14988.472223 # average overall mshr miss latency
727system.cpu.dcache.overall_avg_mshr_miss_latency::total 14988.472223 # average overall mshr miss latency
|
728system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
729system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
730system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
731system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
732system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
733system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
734system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
735
736---------- End Simulation Statistics ----------
| 728system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
729system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
730system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
731system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
732system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
733system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
734system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
735
736---------- End Simulation Statistics ----------
|