| stats.txt (9125:65423863d963) | stats.txt (9134:275232ad377d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.191766 # Number of seconds simulated 4sim_ticks 5191766314000 # Number of ticks simulated 5final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.191766 # Number of seconds simulated 4sim_ticks 5191766314000 # Number of ticks simulated 5final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 672863 # Simulator instruction rate (inst/s) 8host_op_rate 1291533 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25283717995 # Simulator tick rate (ticks/s) 10host_mem_usage 405876 # Number of bytes of host memory used 11host_seconds 205.34 # Real time elapsed on the host | 7host_inst_rate 787684 # Simulator instruction rate (inst/s) 8host_op_rate 1511929 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29598304712 # Simulator tick rate (ticks/s) 10host_mem_usage 358992 # Number of bytes of host memory used 11host_seconds 175.41 # Real time elapsed on the host |
| 12sim_insts 138165780 # Number of instructions simulated 13sim_ops 265203824 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8939328 # Number of bytes read from this memory 18system.physmem.bytes_read::total 12651968 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory --- 19 unchanged lines hidden (view full) --- 39system.physmem.bw_total::writebacks 1556458 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::pc.south_bridge.ide 556857 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 158183 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 1721828 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s) 45system.l2c.replacements 86221 # number of replacements 46system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use | 12sim_insts 138165780 # Number of instructions simulated 13sim_ops 265203824 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8939328 # Number of bytes read from this memory 18system.physmem.bytes_read::total 12651968 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory --- 19 unchanged lines hidden (view full) --- 39system.physmem.bw_total::writebacks 1556458 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::pc.south_bridge.ide 556857 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 158183 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 1721828 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s) 45system.l2c.replacements 86221 # number of replacements 46system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use |
| 47system.l2c.total_refs 3491043 # Total number of references to valid blocks. | 47system.l2c.total_refs 3490237 # Total number of references to valid blocks. |
| 48system.l2c.sampled_refs 150947 # Sample count of references to valid blocks. | 48system.l2c.sampled_refs 150947 # Sample count of references to valid blocks. |
| 49system.l2c.avg_refs 23.127608 # Average number of references to valid blocks. | 49system.l2c.avg_refs 23.122268 # Average number of references to valid blocks. |
| 50system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 51system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor 52system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor 53system.l2c.occ_blocks::cpu.inst 3484.481205 # Average occupied blocks per requestor 54system.l2c.occ_blocks::cpu.data 11111.678558 # Average occupied blocks per requestor 55system.l2c.occ_percent::writebacks 0.765539 # Average percentage of cache occupancy 56system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 57system.l2c.occ_percent::cpu.inst 0.053169 # Average percentage of cache occupancy 58system.l2c.occ_percent::cpu.data 0.169551 # Average percentage of cache occupancy 59system.l2c.occ_percent::total 0.988261 # Average percentage of cache occupancy 60system.l2c.ReadReq_hits::cpu.dtb.walker 6306 # number of ReadReq hits 61system.l2c.ReadReq_hits::cpu.itb.walker 2757 # number of ReadReq hits 62system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits 63system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits 64system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits | 50system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 51system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor 52system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor 53system.l2c.occ_blocks::cpu.inst 3484.481205 # Average occupied blocks per requestor 54system.l2c.occ_blocks::cpu.data 11111.678558 # Average occupied blocks per requestor 55system.l2c.occ_percent::writebacks 0.765539 # Average percentage of cache occupancy 56system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 57system.l2c.occ_percent::cpu.inst 0.053169 # Average percentage of cache occupancy 58system.l2c.occ_percent::cpu.data 0.169551 # Average percentage of cache occupancy 59system.l2c.occ_percent::total 0.988261 # Average percentage of cache occupancy 60system.l2c.ReadReq_hits::cpu.dtb.walker 6306 # number of ReadReq hits 61system.l2c.ReadReq_hits::cpu.itb.walker 2757 # number of ReadReq hits 62system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits 63system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits 64system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits |
| 65system.l2c.Writeback_hits::writebacks 1542135 # number of Writeback hits 66system.l2c.Writeback_hits::total 1542135 # number of Writeback hits | 65system.l2c.Writeback_hits::writebacks 1541329 # number of Writeback hits 66system.l2c.Writeback_hits::total 1541329 # number of Writeback hits |
| 67system.l2c.UpgradeReq_hits::cpu.data 319 # number of UpgradeReq hits 68system.l2c.UpgradeReq_hits::total 319 # number of UpgradeReq hits 69system.l2c.ReadExReq_hits::cpu.data 200451 # number of ReadExReq hits 70system.l2c.ReadExReq_hits::total 200451 # number of ReadExReq hits 71system.l2c.demand_hits::cpu.dtb.walker 6306 # number of demand (read+write) hits 72system.l2c.demand_hits::cpu.itb.walker 2757 # number of demand (read+write) hits 73system.l2c.demand_hits::cpu.inst 777565 # number of demand (read+write) hits 74system.l2c.demand_hits::cpu.data 1479802 # number of demand (read+write) hits --- 35 unchanged lines hidden (view full) --- 110system.l2c.overall_miss_latency::cpu.inst 667948500 # number of overall miss cycles 111system.l2c.overall_miss_latency::cpu.data 7328903000 # number of overall miss cycles 112system.l2c.overall_miss_latency::total 7997111500 # number of overall miss cycles 113system.l2c.ReadReq_accesses::cpu.dtb.walker 6306 # number of ReadReq accesses(hits+misses) 114system.l2c.ReadReq_accesses::cpu.itb.walker 2762 # number of ReadReq accesses(hits+misses) 115system.l2c.ReadReq_accesses::cpu.inst 790398 # number of ReadReq accesses(hits+misses) 116system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses) 117system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses) | 67system.l2c.UpgradeReq_hits::cpu.data 319 # number of UpgradeReq hits 68system.l2c.UpgradeReq_hits::total 319 # number of UpgradeReq hits 69system.l2c.ReadExReq_hits::cpu.data 200451 # number of ReadExReq hits 70system.l2c.ReadExReq_hits::total 200451 # number of ReadExReq hits 71system.l2c.demand_hits::cpu.dtb.walker 6306 # number of demand (read+write) hits 72system.l2c.demand_hits::cpu.itb.walker 2757 # number of demand (read+write) hits 73system.l2c.demand_hits::cpu.inst 777565 # number of demand (read+write) hits 74system.l2c.demand_hits::cpu.data 1479802 # number of demand (read+write) hits --- 35 unchanged lines hidden (view full) --- 110system.l2c.overall_miss_latency::cpu.inst 667948500 # number of overall miss cycles 111system.l2c.overall_miss_latency::cpu.data 7328903000 # number of overall miss cycles 112system.l2c.overall_miss_latency::total 7997111500 # number of overall miss cycles 113system.l2c.ReadReq_accesses::cpu.dtb.walker 6306 # number of ReadReq accesses(hits+misses) 114system.l2c.ReadReq_accesses::cpu.itb.walker 2762 # number of ReadReq accesses(hits+misses) 115system.l2c.ReadReq_accesses::cpu.inst 790398 # number of ReadReq accesses(hits+misses) 116system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses) 117system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses) |
| 118system.l2c.Writeback_accesses::writebacks 1542135 # number of Writeback accesses(hits+misses) 119system.l2c.Writeback_accesses::total 1542135 # number of Writeback accesses(hits+misses) | 118system.l2c.Writeback_accesses::writebacks 1541329 # number of Writeback accesses(hits+misses) 119system.l2c.Writeback_accesses::total 1541329 # number of Writeback accesses(hits+misses) |
| 120system.l2c.UpgradeReq_accesses::cpu.data 1665 # number of UpgradeReq accesses(hits+misses) 121system.l2c.UpgradeReq_accesses::total 1665 # number of UpgradeReq accesses(hits+misses) 122system.l2c.ReadExReq_accesses::cpu.data 312686 # number of ReadExReq accesses(hits+misses) 123system.l2c.ReadExReq_accesses::total 312686 # number of ReadExReq accesses(hits+misses) 124system.l2c.demand_accesses::cpu.dtb.walker 6306 # number of demand (read+write) accesses 125system.l2c.demand_accesses::cpu.itb.walker 2762 # number of demand (read+write) accesses 126system.l2c.demand_accesses::cpu.inst 790398 # number of demand (read+write) accesses 127system.l2c.demand_accesses::cpu.data 1620410 # number of demand (read+write) accesses --- 298 unchanged lines hidden (view full) --- 426system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 427system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 428system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 429system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 430system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 431system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 432system.cpu.icache.fast_writes 0 # number of fast writes performed 433system.cpu.icache.cache_copies 0 # number of cache copies performed | 120system.l2c.UpgradeReq_accesses::cpu.data 1665 # number of UpgradeReq accesses(hits+misses) 121system.l2c.UpgradeReq_accesses::total 1665 # number of UpgradeReq accesses(hits+misses) 122system.l2c.ReadExReq_accesses::cpu.data 312686 # number of ReadExReq accesses(hits+misses) 123system.l2c.ReadExReq_accesses::total 312686 # number of ReadExReq accesses(hits+misses) 124system.l2c.demand_accesses::cpu.dtb.walker 6306 # number of demand (read+write) accesses 125system.l2c.demand_accesses::cpu.itb.walker 2762 # number of demand (read+write) accesses 126system.l2c.demand_accesses::cpu.inst 790398 # number of demand (read+write) accesses 127system.l2c.demand_accesses::cpu.data 1620410 # number of demand (read+write) accesses --- 298 unchanged lines hidden (view full) --- 426system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 427system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 428system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 429system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 430system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 431system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 432system.cpu.icache.fast_writes 0 # number of fast writes performed 433system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 434system.cpu.icache.writebacks::writebacks 806 # number of writebacks 435system.cpu.icache.writebacks::total 806 # number of writebacks | |
| 436system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790411 # number of ReadReq MSHR misses 437system.cpu.icache.ReadReq_mshr_misses::total 790411 # number of ReadReq MSHR misses 438system.cpu.icache.demand_mshr_misses::cpu.inst 790411 # number of demand (read+write) MSHR misses 439system.cpu.icache.demand_mshr_misses::total 790411 # number of demand (read+write) MSHR misses 440system.cpu.icache.overall_mshr_misses::cpu.inst 790411 # number of overall MSHR misses 441system.cpu.icache.overall_mshr_misses::total 790411 # number of overall MSHR misses 442system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408658500 # number of ReadReq MSHR miss cycles 443system.cpu.icache.ReadReq_mshr_miss_latency::total 9408658500 # number of ReadReq MSHR miss cycles --- 295 unchanged lines hidden --- | 434system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790411 # number of ReadReq MSHR misses 435system.cpu.icache.ReadReq_mshr_misses::total 790411 # number of ReadReq MSHR misses 436system.cpu.icache.demand_mshr_misses::cpu.inst 790411 # number of demand (read+write) MSHR misses 437system.cpu.icache.demand_mshr_misses::total 790411 # number of demand (read+write) MSHR misses 438system.cpu.icache.overall_mshr_misses::cpu.inst 790411 # number of overall MSHR misses 439system.cpu.icache.overall_mshr_misses::total 790411 # number of overall MSHR misses 440system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408658500 # number of ReadReq MSHR miss cycles 441system.cpu.icache.ReadReq_mshr_miss_latency::total 9408658500 # number of ReadReq MSHR miss cycles --- 295 unchanged lines hidden --- |