| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.195470 # Number of seconds simulated 4sim_ticks 5195470393000 # Number of ticks simulated 5final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.195470 # Number of seconds simulated 4sim_ticks 5195470393000 # Number of ticks simulated 5final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1225094 # Simulator instruction rate (inst/s) 8host_op_rate 2351489 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46076516791 # Simulator tick rate (ticks/s) 10host_mem_usage 346880 # Number of bytes of host memory used 11host_seconds 112.76 # Real time elapsed on the host | 7host_inst_rate 387917 # Simulator instruction rate (inst/s) 8host_op_rate 744582 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14589799311 # Simulator tick rate (ticks/s) 10host_mem_usage 351980 # Number of bytes of host memory used 11host_seconds 356.10 # Real time elapsed on the host |
| 12sim_insts 138138472 # Number of instructions simulated 13sim_ops 265147881 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 13764096 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10427072 # Number of bytes written to this memory 17system.physmem.num_reads 215064 # Number of read requests responded to by this memory 18system.physmem.num_writes 162923 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 125 unchanged lines hidden (view full) --- 145system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 146system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 147system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency 148system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency 149system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 150system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 151system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 152system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 138138472 # Number of instructions simulated 13sim_ops 265147881 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 13764096 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10427072 # Number of bytes written to this memory 17system.physmem.num_reads 215064 # Number of read requests responded to by this memory 18system.physmem.num_writes 162923 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 125 unchanged lines hidden (view full) --- 145system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 146system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 147system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency 148system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency 149system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 150system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 151system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 152system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 153system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 154system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 153system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 154system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 155system.l2c.fast_writes 0 # number of fast writes performed 156system.l2c.cache_copies 0 # number of cache copies performed 157system.l2c.writebacks::writebacks 116255 # number of writebacks 158system.l2c.writebacks::total 116255 # number of writebacks 159system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 13 # number of ReadReq MSHR misses 160system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses 161system.l2c.ReadReq_mshr_misses::cpu.inst 15226 # number of ReadReq MSHR misses 162system.l2c.ReadReq_mshr_misses::cpu.data 35581 # number of ReadReq MSHR misses --- 110 unchanged lines hidden (view full) --- 273system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency 274system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency 275system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency 276system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked 277system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked 279system.iocache.blocked::no_targets 0 # number of cycles access was blocked 280system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked | 155system.l2c.fast_writes 0 # number of fast writes performed 156system.l2c.cache_copies 0 # number of cache copies performed 157system.l2c.writebacks::writebacks 116255 # number of writebacks 158system.l2c.writebacks::total 116255 # number of writebacks 159system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 13 # number of ReadReq MSHR misses 160system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses 161system.l2c.ReadReq_mshr_misses::cpu.inst 15226 # number of ReadReq MSHR misses 162system.l2c.ReadReq_mshr_misses::cpu.data 35581 # number of ReadReq MSHR misses --- 110 unchanged lines hidden (view full) --- 273system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency 274system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency 275system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency 276system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked 277system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked 279system.iocache.blocked::no_targets 0 # number of cycles access was blocked 280system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked |
| 281system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 281system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 282system.iocache.fast_writes 0 # number of fast writes performed 283system.iocache.cache_copies 0 # number of cache copies performed 284system.iocache.writebacks::writebacks 46668 # number of writebacks 285system.iocache.writebacks::total 46668 # number of writebacks 286system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses 287system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses 288system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 289system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses --- 92 unchanged lines hidden (view full) --- 382system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses 383system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency 384system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency 385system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency 386system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 282system.iocache.fast_writes 0 # number of fast writes performed 283system.iocache.cache_copies 0 # number of cache copies performed 284system.iocache.writebacks::writebacks 46668 # number of writebacks 285system.iocache.writebacks::total 46668 # number of writebacks 286system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses 287system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses 288system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 289system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses --- 92 unchanged lines hidden (view full) --- 382system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses 383system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency 384system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency 385system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency 386system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 390system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 391system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 390system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 392system.cpu.icache.fast_writes 0 # number of fast writes performed 393system.cpu.icache.cache_copies 0 # number of cache copies performed 394system.cpu.icache.writebacks::writebacks 805 # number of writebacks 395system.cpu.icache.writebacks::total 805 # number of writebacks 396system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses 397system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses 398system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses 399system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses --- 54 unchanged lines hidden (view full) --- 454system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses 455system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency 456system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency 457system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency 458system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 459system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 460system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 461system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked | 392system.cpu.icache.fast_writes 0 # number of fast writes performed 393system.cpu.icache.cache_copies 0 # number of cache copies performed 394system.cpu.icache.writebacks::writebacks 805 # number of writebacks 395system.cpu.icache.writebacks::total 805 # number of writebacks 396system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses 397system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses 398system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses 399system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses --- 54 unchanged lines hidden (view full) --- 454system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses 455system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency 456system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency 457system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency 458system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 459system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 460system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 461system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked |
| 462system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 463system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 462system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 463system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 464system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 465system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 466system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks 467system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks 468system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses 469system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses 470system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses 471system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses --- 50 unchanged lines hidden (view full) --- 522system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses 523system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency 524system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency 525system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency 526system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 529system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked | 464system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 465system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 466system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks 467system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks 468system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses 469system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses 470system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses 471system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses --- 50 unchanged lines hidden (view full) --- 522system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses 523system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency 524system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency 525system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency 526system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 529system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked |
| 530system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 531system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 530system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 531system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 532system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 533system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 534system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks 535system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks 536system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses 537system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses 538system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses 539system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses --- 60 unchanged lines hidden (view full) --- 600system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency 601system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency 602system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency 603system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency 604system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 605system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 606system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 607system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 532system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 533system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 534system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks 535system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks 536system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses 537system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses 538system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses 539system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses --- 60 unchanged lines hidden (view full) --- 600system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency 601system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency 602system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency 603system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency 604system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 605system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 606system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 607system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 608system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 609system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 608system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 609system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 610system.cpu.dcache.fast_writes 0 # number of fast writes performed 611system.cpu.dcache.cache_copies 0 # number of cache copies performed 612system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks 613system.cpu.dcache.writebacks::total 1529951 # number of writebacks 614system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses 615system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses 616system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses 617system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses --- 32 unchanged lines hidden --- | 610system.cpu.dcache.fast_writes 0 # number of fast writes performed 611system.cpu.dcache.cache_copies 0 # number of cache copies performed 612system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks 613system.cpu.dcache.writebacks::total 1529951 # number of writebacks 614system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses 615system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses 616system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses 617system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses --- 32 unchanged lines hidden --- |