| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.194946 # Number of seconds simulated 4sim_ticks 5194946000500 # Number of ticks simulated 5final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.194946 # Number of seconds simulated 4sim_ticks 5194946000500 # Number of ticks simulated 5final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 842553 # Simulator instruction rate (inst/s) 8host_op_rate 1624008 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34079125299 # Simulator tick rate (ticks/s) 10host_mem_usage 659848 # Number of bytes of host memory used 11host_seconds 152.44 # Real time elapsed on the host | 7host_inst_rate 910377 # Simulator instruction rate (inst/s) 8host_op_rate 1754736 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36822413305 # Simulator tick rate (ticks/s) 10host_mem_usage 616280 # Number of bytes of host memory used 11host_seconds 141.08 # Real time elapsed on the host |
| 12sim_insts 128436892 # Number of instructions simulated 13sim_ops 247560077 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9031168 # Number of bytes read from this memory --- 426 unchanged lines hidden (view full) --- 446system.cpu.dcache.overall_avg_miss_latency::cpu.data 19557.657404 # average overall miss latency 447system.cpu.dcache.overall_avg_miss_latency::total 19557.657404 # average overall miss latency 448system.cpu.dcache.blocked_cycles::no_mshrs 19286 # number of cycles access was blocked 449system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_mshrs 514 # number of cycles access was blocked 451system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.521401 # average number of cycles each access was blocked 453system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 128436892 # Number of instructions simulated 13sim_ops 247560077 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9031168 # Number of bytes read from this memory --- 426 unchanged lines hidden (view full) --- 446system.cpu.dcache.overall_avg_miss_latency::cpu.data 19557.657404 # average overall miss latency 447system.cpu.dcache.overall_avg_miss_latency::total 19557.657404 # average overall miss latency 448system.cpu.dcache.blocked_cycles::no_mshrs 19286 # number of cycles access was blocked 449system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_mshrs 514 # number of cycles access was blocked 451system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.521401 # average number of cycles each access was blocked 453system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 454system.cpu.dcache.fast_writes 0 # number of fast writes performed 455system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 456system.cpu.dcache.writebacks::writebacks 1540773 # number of writebacks 457system.cpu.dcache.writebacks::total 1540773 # number of writebacks 458system.cpu.dcache.ReadReq_mshr_hits::cpu.data 285 # number of ReadReq MSHR hits 459system.cpu.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits 460system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9475 # number of WriteReq MSHR hits 461system.cpu.dcache.WriteReq_mshr_hits::total 9475 # number of WriteReq MSHR hits 462system.cpu.dcache.demand_mshr_hits::cpu.data 9760 # number of demand (read+write) MSHR hits 463system.cpu.dcache.demand_mshr_hits::total 9760 # number of demand (read+write) MSHR hits --- 22 unchanged lines hidden (view full) --- 486system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6518448000 # number of SoftPFReq MSHR miss cycles 487system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6518448000 # number of SoftPFReq MSHR miss cycles 488system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29793052467 # number of demand (read+write) MSHR miss cycles 489system.cpu.dcache.demand_mshr_miss_latency::total 29793052467 # number of demand (read+write) MSHR miss cycles 490system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36311500467 # number of overall MSHR miss cycles 491system.cpu.dcache.overall_mshr_miss_latency::total 36311500467 # number of overall MSHR miss cycles 492system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132085000 # number of ReadReq MSHR uncacheable cycles 493system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132085000 # number of ReadReq MSHR uncacheable cycles | 454system.cpu.dcache.writebacks::writebacks 1540773 # number of writebacks 455system.cpu.dcache.writebacks::total 1540773 # number of writebacks 456system.cpu.dcache.ReadReq_mshr_hits::cpu.data 285 # number of ReadReq MSHR hits 457system.cpu.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits 458system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9475 # number of WriteReq MSHR hits 459system.cpu.dcache.WriteReq_mshr_hits::total 9475 # number of WriteReq MSHR hits 460system.cpu.dcache.demand_mshr_hits::cpu.data 9760 # number of demand (read+write) MSHR hits 461system.cpu.dcache.demand_mshr_hits::total 9760 # number of demand (read+write) MSHR hits --- 22 unchanged lines hidden (view full) --- 484system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6518448000 # number of SoftPFReq MSHR miss cycles 485system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6518448000 # number of SoftPFReq MSHR miss cycles 486system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29793052467 # number of demand (read+write) MSHR miss cycles 487system.cpu.dcache.demand_mshr_miss_latency::total 29793052467 # number of demand (read+write) MSHR miss cycles 488system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36311500467 # number of overall MSHR miss cycles 489system.cpu.dcache.overall_mshr_miss_latency::total 36311500467 # number of overall MSHR miss cycles 490system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132085000 # number of ReadReq MSHR uncacheable cycles 491system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132085000 # number of ReadReq MSHR uncacheable cycles |
| 494system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786349500 # number of WriteReq MSHR uncacheable cycles 495system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786349500 # number of WriteReq MSHR uncacheable cycles 496system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97918434500 # number of overall MSHR uncacheable cycles 497system.cpu.dcache.overall_mshr_uncacheable_latency::total 97918434500 # number of overall MSHR uncacheable cycles | 492system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 95132085000 # number of overall MSHR uncacheable cycles 493system.cpu.dcache.overall_mshr_uncacheable_latency::total 95132085000 # number of overall MSHR uncacheable cycles |
| 498system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070257 # mshr miss rate for ReadReq accesses 499system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070257 # mshr miss rate for ReadReq accesses 500system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037690 # mshr miss rate for WriteReq accesses 501system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037690 # mshr miss rate for WriteReq accesses 502system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871991 # mshr miss rate for SoftPFReq accesses 503system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871991 # mshr miss rate for SoftPFReq accesses 504system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057418 # mshr miss rate for demand accesses 505system.cpu.dcache.demand_mshr_miss_rate::total 0.057418 # mshr miss rate for demand accesses --- 6 unchanged lines hidden (view full) --- 512system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16184.366946 # average SoftPFReq mshr miss latency 513system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16184.366946 # average SoftPFReq mshr miss latency 514system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24347.492332 # average overall mshr miss latency 515system.cpu.dcache.demand_avg_mshr_miss_latency::total 24347.492332 # average overall mshr miss latency 516system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780 # average overall mshr miss latency 517system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780 # average overall mshr miss latency 518system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442 # average ReadReq mshr uncacheable latency 519system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442 # average ReadReq mshr uncacheable latency | 494system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070257 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070257 # mshr miss rate for ReadReq accesses 496system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037690 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037690 # mshr miss rate for WriteReq accesses 498system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871991 # mshr miss rate for SoftPFReq accesses 499system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871991 # mshr miss rate for SoftPFReq accesses 500system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057418 # mshr miss rate for demand accesses 501system.cpu.dcache.demand_mshr_miss_rate::total 0.057418 # mshr miss rate for demand accesses --- 6 unchanged lines hidden (view full) --- 508system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16184.366946 # average SoftPFReq mshr miss latency 509system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16184.366946 # average SoftPFReq mshr miss latency 510system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24347.492332 # average overall mshr miss latency 511system.cpu.dcache.demand_avg_mshr_miss_latency::total 24347.492332 # average overall mshr miss latency 512system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780 # average overall mshr miss latency 513system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780 # average overall mshr miss latency 514system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442 # average ReadReq mshr uncacheable latency 515system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442 # average ReadReq mshr uncacheable latency |
| 520system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200168.785920 # average WriteReq mshr uncacheable latency 521system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200168.785920 # average WriteReq mshr uncacheable latency 522system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.330939 # average overall mshr uncacheable latency 523system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.330939 # average overall mshr uncacheable latency 524system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 516system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 169798.069131 # average overall mshr uncacheable latency 517system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 169798.069131 # average overall mshr uncacheable latency |
| 525system.cpu.dtb_walker_cache.tags.replacements 7581 # number of replacements 526system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use 527system.cpu.dtb_walker_cache.tags.total_refs 13343 # Total number of references to valid blocks. 528system.cpu.dtb_walker_cache.tags.sampled_refs 7597 # Sample count of references to valid blocks. 529system.cpu.dtb_walker_cache.tags.avg_refs 1.756351 # Average number of references to valid blocks. 530system.cpu.dtb_walker_cache.tags.warmup_cycle 5163352546000 # Cycle when the warmup percentage was hit. 531system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor 532system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 576system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10971.504948 # average overall miss latency 577system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10971.504948 # average overall miss latency 578system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 579system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 580system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 581system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 582system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 583system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 518system.cpu.dtb_walker_cache.tags.replacements 7581 # number of replacements 519system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use 520system.cpu.dtb_walker_cache.tags.total_refs 13343 # Total number of references to valid blocks. 521system.cpu.dtb_walker_cache.tags.sampled_refs 7597 # Sample count of references to valid blocks. 522system.cpu.dtb_walker_cache.tags.avg_refs 1.756351 # Average number of references to valid blocks. 523system.cpu.dtb_walker_cache.tags.warmup_cycle 5163352546000 # Cycle when the warmup percentage was hit. 524system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor 525system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 569system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10971.504948 # average overall miss latency 570system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10971.504948 # average overall miss latency 571system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 572system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 573system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 574system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 575system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 576system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 584system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 585system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | |
| 586system.cpu.dtb_walker_cache.writebacks::writebacks 2983 # number of writebacks 587system.cpu.dtb_walker_cache.writebacks::total 2983 # number of writebacks 588system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8791 # number of ReadReq MSHR misses 589system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8791 # number of ReadReq MSHR misses 590system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8791 # number of demand (read+write) MSHR misses 591system.cpu.dtb_walker_cache.demand_mshr_misses::total 8791 # number of demand (read+write) MSHR misses 592system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8791 # number of overall MSHR misses 593system.cpu.dtb_walker_cache.overall_mshr_misses::total 8791 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 604system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397172 # mshr miss rate for overall accesses 605system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397172 # mshr miss rate for overall accesses 606system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average ReadReq mshr miss latency 607system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9971.504948 # average ReadReq mshr miss latency 608system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency 609system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency 610system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency 611system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency | 577system.cpu.dtb_walker_cache.writebacks::writebacks 2983 # number of writebacks 578system.cpu.dtb_walker_cache.writebacks::total 2983 # number of writebacks 579system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8791 # number of ReadReq MSHR misses 580system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8791 # number of ReadReq MSHR misses 581system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8791 # number of demand (read+write) MSHR misses 582system.cpu.dtb_walker_cache.demand_mshr_misses::total 8791 # number of demand (read+write) MSHR misses 583system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8791 # number of overall MSHR misses 584system.cpu.dtb_walker_cache.overall_mshr_misses::total 8791 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 595system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397172 # mshr miss rate for overall accesses 596system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397172 # mshr miss rate for overall accesses 597system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average ReadReq mshr miss latency 598system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9971.504948 # average ReadReq mshr miss latency 599system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency 600system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency 601system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency 602system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency |
| 612system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 613system.cpu.icache.tags.replacements 790489 # number of replacements 614system.cpu.icache.tags.tagsinuse 510.213579 # Cycle average of tags in use 615system.cpu.icache.tags.total_refs 144635934 # Total number of references to valid blocks. 616system.cpu.icache.tags.sampled_refs 791001 # Sample count of references to valid blocks. 617system.cpu.icache.tags.avg_refs 182.851771 # Average number of references to valid blocks. 618system.cpu.icache.tags.warmup_cycle 164551519500 # Cycle when the warmup percentage was hit. 619system.cpu.icache.tags.occ_blocks::cpu.inst 510.213579 # Average occupied blocks per requestor 620system.cpu.icache.tags.occ_percent::cpu.inst 0.996511 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 664system.cpu.icache.overall_avg_miss_latency::cpu.inst 14976.259406 # average overall miss latency 665system.cpu.icache.overall_avg_miss_latency::total 14976.259406 # average overall miss latency 666system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 667system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 668system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 669system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 670system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 671system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 603system.cpu.icache.tags.replacements 790489 # number of replacements 604system.cpu.icache.tags.tagsinuse 510.213579 # Cycle average of tags in use 605system.cpu.icache.tags.total_refs 144635934 # Total number of references to valid blocks. 606system.cpu.icache.tags.sampled_refs 791001 # Sample count of references to valid blocks. 607system.cpu.icache.tags.avg_refs 182.851771 # Average number of references to valid blocks. 608system.cpu.icache.tags.warmup_cycle 164551519500 # Cycle when the warmup percentage was hit. 609system.cpu.icache.tags.occ_blocks::cpu.inst 510.213579 # Average occupied blocks per requestor 610system.cpu.icache.tags.occ_percent::cpu.inst 0.996511 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 654system.cpu.icache.overall_avg_miss_latency::cpu.inst 14976.259406 # average overall miss latency 655system.cpu.icache.overall_avg_miss_latency::total 14976.259406 # average overall miss latency 656system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 660system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 661system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 672system.cpu.icache.fast_writes 0 # number of fast writes performed 673system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 674system.cpu.icache.writebacks::writebacks 790489 # number of writebacks 675system.cpu.icache.writebacks::total 790489 # number of writebacks 676system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791008 # number of ReadReq MSHR misses 677system.cpu.icache.ReadReq_mshr_misses::total 791008 # number of ReadReq MSHR misses 678system.cpu.icache.demand_mshr_misses::cpu.inst 791008 # number of demand (read+write) MSHR misses 679system.cpu.icache.demand_mshr_misses::total 791008 # number of demand (read+write) MSHR misses 680system.cpu.icache.overall_mshr_misses::cpu.inst 791008 # number of overall MSHR misses 681system.cpu.icache.overall_mshr_misses::total 791008 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 692system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005439 # mshr miss rate for overall accesses 693system.cpu.icache.overall_mshr_miss_rate::total 0.005439 # mshr miss rate for overall accesses 694system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13976.259406 # average ReadReq mshr miss latency 695system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13976.259406 # average ReadReq mshr miss latency 696system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency 697system.cpu.icache.demand_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency 698system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency 699system.cpu.icache.overall_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency | 662system.cpu.icache.writebacks::writebacks 790489 # number of writebacks 663system.cpu.icache.writebacks::total 790489 # number of writebacks 664system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791008 # number of ReadReq MSHR misses 665system.cpu.icache.ReadReq_mshr_misses::total 791008 # number of ReadReq MSHR misses 666system.cpu.icache.demand_mshr_misses::cpu.inst 791008 # number of demand (read+write) MSHR misses 667system.cpu.icache.demand_mshr_misses::total 791008 # number of demand (read+write) MSHR misses 668system.cpu.icache.overall_mshr_misses::cpu.inst 791008 # number of overall MSHR misses 669system.cpu.icache.overall_mshr_misses::total 791008 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 680system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005439 # mshr miss rate for overall accesses 681system.cpu.icache.overall_mshr_miss_rate::total 0.005439 # mshr miss rate for overall accesses 682system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13976.259406 # average ReadReq mshr miss latency 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13976.259406 # average ReadReq mshr miss latency 684system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency |
| 700system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 701system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements 702system.cpu.itb_walker_cache.tags.tagsinuse 3.069456 # Cycle average of tags in use 703system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks. 704system.cpu.itb_walker_cache.tags.sampled_refs 3396 # Sample count of references to valid blocks. 705system.cpu.itb_walker_cache.tags.avg_refs 2.347173 # Average number of references to valid blocks. 706system.cpu.itb_walker_cache.tags.warmup_cycle 5168951189500 # Cycle when the warmup percentage was hit. 707system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069456 # Average occupied blocks per requestor 708system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191841 # Average percentage of cache occupancy --- 47 unchanged lines hidden (view full) --- 756system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10561.808335 # average overall miss latency 757system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10561.808335 # average overall miss latency 758system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 759system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 760system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 761system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 762system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 763system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 688system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements 689system.cpu.itb_walker_cache.tags.tagsinuse 3.069456 # Cycle average of tags in use 690system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks. 691system.cpu.itb_walker_cache.tags.sampled_refs 3396 # Sample count of references to valid blocks. 692system.cpu.itb_walker_cache.tags.avg_refs 2.347173 # Average number of references to valid blocks. 693system.cpu.itb_walker_cache.tags.warmup_cycle 5168951189500 # Cycle when the warmup percentage was hit. 694system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069456 # Average occupied blocks per requestor 695system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191841 # Average percentage of cache occupancy --- 47 unchanged lines hidden (view full) --- 743system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10561.808335 # average overall miss latency 744system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10561.808335 # average overall miss latency 745system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 746system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 747system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 748system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 749system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 750system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 764system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 765system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | |
| 766system.cpu.itb_walker_cache.writebacks::writebacks 773 # number of writebacks 767system.cpu.itb_walker_cache.writebacks::total 773 # number of writebacks 768system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4247 # number of ReadReq MSHR misses 769system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4247 # number of ReadReq MSHR misses 770system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4247 # number of demand (read+write) MSHR misses 771system.cpu.itb_walker_cache.demand_mshr_misses::total 4247 # number of demand (read+write) MSHR misses 772system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4247 # number of overall MSHR misses 773system.cpu.itb_walker_cache.overall_mshr_misses::total 4247 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 784system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for overall accesses 785system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.347573 # mshr miss rate for overall accesses 786system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average ReadReq mshr miss latency 787system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9561.808335 # average ReadReq mshr miss latency 788system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency 789system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency 790system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency 791system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency | 751system.cpu.itb_walker_cache.writebacks::writebacks 773 # number of writebacks 752system.cpu.itb_walker_cache.writebacks::total 773 # number of writebacks 753system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4247 # number of ReadReq MSHR misses 754system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4247 # number of ReadReq MSHR misses 755system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4247 # number of demand (read+write) MSHR misses 756system.cpu.itb_walker_cache.demand_mshr_misses::total 4247 # number of demand (read+write) MSHR misses 757system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4247 # number of overall MSHR misses 758system.cpu.itb_walker_cache.overall_mshr_misses::total 4247 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 769system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for overall accesses 770system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.347573 # mshr miss rate for overall accesses 771system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average ReadReq mshr miss latency 772system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9561.808335 # average ReadReq mshr miss latency 773system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency 774system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency 775system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency 776system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency |
| 792system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 793system.cpu.l2cache.tags.replacements 87287 # number of replacements 794system.cpu.l2cache.tags.tagsinuse 64590.438483 # Cycle average of tags in use 795system.cpu.l2cache.tags.total_refs 4366272 # Total number of references to valid blocks. 796system.cpu.l2cache.tags.sampled_refs 151983 # Sample count of references to valid blocks. 797system.cpu.l2cache.tags.avg_refs 28.728687 # Average number of references to valid blocks. 798system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 799system.cpu.l2cache.tags.occ_blocks::writebacks 50117.131899 # Average occupied blocks per requestor 800system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006347 # Average occupied blocks per requestor --- 144 unchanged lines hidden (view full) --- 945system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128082.478329 # average overall miss latency 946system.cpu.l2cache.overall_avg_miss_latency::total 128369.037624 # average overall miss latency 947system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 948system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 949system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 950system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 951system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 952system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 777system.cpu.l2cache.tags.replacements 87287 # number of replacements 778system.cpu.l2cache.tags.tagsinuse 64590.438483 # Cycle average of tags in use 779system.cpu.l2cache.tags.total_refs 4366272 # Total number of references to valid blocks. 780system.cpu.l2cache.tags.sampled_refs 151983 # Sample count of references to valid blocks. 781system.cpu.l2cache.tags.avg_refs 28.728687 # Average number of references to valid blocks. 782system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 783system.cpu.l2cache.tags.occ_blocks::writebacks 50117.131899 # Average occupied blocks per requestor 784system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006347 # Average occupied blocks per requestor --- 144 unchanged lines hidden (view full) --- 929system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128082.478329 # average overall miss latency 930system.cpu.l2cache.overall_avg_miss_latency::total 128369.037624 # average overall miss latency 931system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 932system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 933system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 934system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 935system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 936system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 953system.cpu.l2cache.fast_writes 0 # number of fast writes performed 954system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 955system.cpu.l2cache.writebacks::writebacks 80702 # number of writebacks 956system.cpu.l2cache.writebacks::total 80702 # number of writebacks 957system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 958system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 959system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1406 # number of UpgradeReq MSHR misses 960system.cpu.l2cache.UpgradeReq_mshr_misses::total 1406 # number of UpgradeReq MSHR misses 961system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113511 # number of ReadExReq MSHR misses 962system.cpu.l2cache.ReadExReq_mshr_misses::total 113511 # number of ReadExReq MSHR misses --- 36 unchanged lines hidden (view full) --- 999system.cpu.l2cache.demand_mshr_miss_latency::total 18328972000 # number of demand (read+write) MSHR miss cycles 1000system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 109000 # number of overall MSHR miss cycles 1001system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles 1002system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1559737000 # number of overall MSHR miss cycles 1003system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16768538500 # number of overall MSHR miss cycles 1004system.cpu.l2cache.overall_mshr_miss_latency::total 18328972000 # number of overall MSHR miss cycles 1005system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88302755000 # number of ReadReq MSHR uncacheable cycles 1006system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88302755000 # number of ReadReq MSHR uncacheable cycles | 937system.cpu.l2cache.writebacks::writebacks 80702 # number of writebacks 938system.cpu.l2cache.writebacks::total 80702 # number of writebacks 939system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 940system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 941system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1406 # number of UpgradeReq MSHR misses 942system.cpu.l2cache.UpgradeReq_mshr_misses::total 1406 # number of UpgradeReq MSHR misses 943system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113511 # number of ReadExReq MSHR misses 944system.cpu.l2cache.ReadExReq_mshr_misses::total 113511 # number of ReadExReq MSHR misses --- 36 unchanged lines hidden (view full) --- 981system.cpu.l2cache.demand_mshr_miss_latency::total 18328972000 # number of demand (read+write) MSHR miss cycles 982system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 109000 # number of overall MSHR miss cycles 983system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles 984system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1559737000 # number of overall MSHR miss cycles 985system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16768538500 # number of overall MSHR miss cycles 986system.cpu.l2cache.overall_mshr_miss_latency::total 18328972000 # number of overall MSHR miss cycles 987system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88302755000 # number of ReadReq MSHR uncacheable cycles 988system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88302755000 # number of ReadReq MSHR uncacheable cycles |
| 1007system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2626267500 # number of WriteReq MSHR uncacheable cycles 1008system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2626267500 # number of WriteReq MSHR uncacheable cycles 1009system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90929022500 # number of overall MSHR uncacheable cycles 1010system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90929022500 # number of overall MSHR uncacheable cycles | 989system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88302755000 # number of overall MSHR uncacheable cycles 990system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88302755000 # number of overall MSHR uncacheable cycles |
| 1011system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1012system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1013system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses 1014system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814600 # mshr miss rate for UpgradeReq accesses 1015system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361003 # mshr miss rate for ReadExReq accesses 1016system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361003 # mshr miss rate for ReadExReq accesses 1017system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for ReadCleanReq accesses 1018system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016224 # mshr miss rate for ReadCleanReq accesses --- 28 unchanged lines hidden (view full) --- 1047system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency 1048system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average overall mshr miss latency 1049system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency 1050system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121541.104964 # average overall mshr miss latency 1051system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329 # average overall mshr miss latency 1052system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency 1053system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290 # average ReadReq mshr uncacheable latency 1054system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290 # average ReadReq mshr uncacheable latency | 991system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 992system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 993system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses 994system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814600 # mshr miss rate for UpgradeReq accesses 995system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361003 # mshr miss rate for ReadExReq accesses 996system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361003 # mshr miss rate for ReadExReq accesses 997system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for ReadCleanReq accesses 998system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016224 # mshr miss rate for ReadCleanReq accesses --- 28 unchanged lines hidden (view full) --- 1027system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency 1028system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average overall mshr miss latency 1029system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency 1030system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121541.104964 # average overall mshr miss latency 1031system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329 # average overall mshr miss latency 1032system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency 1033system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290 # average ReadReq mshr uncacheable latency 1034system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290 # average ReadReq mshr uncacheable latency |
| 1055system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188668.642241 # average WriteReq mshr uncacheable latency 1056system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188668.642241 # average WriteReq mshr uncacheable latency 1057system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.163786 # average overall mshr uncacheable latency 1058system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.163786 # average overall mshr uncacheable latency 1059system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1035system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 157608.626974 # average overall mshr uncacheable latency 1036system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157608.626974 # average overall mshr uncacheable latency |
| 1060system.cpu.toL2Bus.snoop_filter.tot_requests 4855602 # Total number of requests made to the snoop filter. 1061system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425060 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1062system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1063system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter. 1064system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1065system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1066system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution 1067system.cpu.toL2Bus.trans_dist::ReadResp 2660470 # Transaction distribution --- 155 unchanged lines hidden (view full) --- 1223system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1224system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1225system.iocache.tags.tag_accesses 428058 # Number of tag accesses 1226system.iocache.tags.data_accesses 428058 # Number of data accesses 1227system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses 1228system.iocache.ReadReq_misses::total 842 # number of ReadReq misses 1229system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1230system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses | 1037system.cpu.toL2Bus.snoop_filter.tot_requests 4855602 # Total number of requests made to the snoop filter. 1038system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425060 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1039system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1040system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter. 1041system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1042system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1043system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution 1044system.cpu.toL2Bus.trans_dist::ReadResp 2660470 # Transaction distribution --- 155 unchanged lines hidden (view full) --- 1200system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1201system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1202system.iocache.tags.tag_accesses 428058 # Number of tag accesses 1203system.iocache.tags.data_accesses 428058 # Number of data accesses 1204system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses 1205system.iocache.ReadReq_misses::total 842 # number of ReadReq misses 1206system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1207system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses |
| 1231system.iocache.demand_misses::pc.south_bridge.ide 842 # number of demand (read+write) misses 1232system.iocache.demand_misses::total 842 # number of demand (read+write) misses 1233system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses 1234system.iocache.overall_misses::total 842 # number of overall misses | 1208system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses 1209system.iocache.demand_misses::total 47562 # number of demand (read+write) misses 1210system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses 1211system.iocache.overall_misses::total 47562 # number of overall misses |
| 1235system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138525690 # number of ReadReq miss cycles 1236system.iocache.ReadReq_miss_latency::total 138525690 # number of ReadReq miss cycles 1237system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867864184 # number of WriteLineReq miss cycles 1238system.iocache.WriteLineReq_miss_latency::total 5867864184 # number of WriteLineReq miss cycles | 1212system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138525690 # number of ReadReq miss cycles 1213system.iocache.ReadReq_miss_latency::total 138525690 # number of ReadReq miss cycles 1214system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867864184 # number of WriteLineReq miss cycles 1215system.iocache.WriteLineReq_miss_latency::total 5867864184 # number of WriteLineReq miss cycles |
| 1239system.iocache.demand_miss_latency::pc.south_bridge.ide 138525690 # number of demand (read+write) miss cycles 1240system.iocache.demand_miss_latency::total 138525690 # number of demand (read+write) miss cycles 1241system.iocache.overall_miss_latency::pc.south_bridge.ide 138525690 # number of overall miss cycles 1242system.iocache.overall_miss_latency::total 138525690 # number of overall miss cycles | 1216system.iocache.demand_miss_latency::pc.south_bridge.ide 6006389874 # number of demand (read+write) miss cycles 1217system.iocache.demand_miss_latency::total 6006389874 # number of demand (read+write) miss cycles 1218system.iocache.overall_miss_latency::pc.south_bridge.ide 6006389874 # number of overall miss cycles 1219system.iocache.overall_miss_latency::total 6006389874 # number of overall miss cycles |
| 1243system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) 1244system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) 1245system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1246system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) | 1220system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) 1221system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) 1222system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1223system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) |
| 1247system.iocache.demand_accesses::pc.south_bridge.ide 842 # number of demand (read+write) accesses 1248system.iocache.demand_accesses::total 842 # number of demand (read+write) accesses 1249system.iocache.overall_accesses::pc.south_bridge.ide 842 # number of overall (read+write) accesses 1250system.iocache.overall_accesses::total 842 # number of overall (read+write) accesses | 1224system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses 1225system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses 1226system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses 1227system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses |
| 1251system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1252system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1253system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1254system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1255system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1256system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1257system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1258system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1259system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average ReadReq miss latency 1260system.iocache.ReadReq_avg_miss_latency::total 164519.821853 # average ReadReq miss latency 1261system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048 # average WriteLineReq miss latency 1262system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048 # average WriteLineReq miss latency | 1228system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1229system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1230system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1231system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1232system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1233system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1234system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1235system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1236system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average ReadReq miss latency 1237system.iocache.ReadReq_avg_miss_latency::total 164519.821853 # average ReadReq miss latency 1238system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048 # average WriteLineReq miss latency 1239system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048 # average WriteLineReq miss latency |
| 1263system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency 1264system.iocache.demand_avg_miss_latency::total 164519.821853 # average overall miss latency 1265system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency 1266system.iocache.overall_avg_miss_latency::total 164519.821853 # average overall miss latency | 1240system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency 1241system.iocache.demand_avg_miss_latency::total 126285.477356 # average overall miss latency 1242system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency 1243system.iocache.overall_avg_miss_latency::total 126285.477356 # average overall miss latency |
| 1267system.iocache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked 1268system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1269system.iocache.blocked::no_mshrs 33 # number of cycles access was blocked 1270system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1271system.iocache.avg_blocked_cycles::no_mshrs 12.969697 # average number of cycles each access was blocked 1272system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1244system.iocache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked 1245system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1246system.iocache.blocked::no_mshrs 33 # number of cycles access was blocked 1247system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1248system.iocache.avg_blocked_cycles::no_mshrs 12.969697 # average number of cycles each access was blocked 1249system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1273system.iocache.fast_writes 0 # number of fast writes performed 1274system.iocache.cache_copies 0 # number of cache copies performed | |
| 1275system.iocache.writebacks::writebacks 46667 # number of writebacks 1276system.iocache.writebacks::total 46667 # number of writebacks 1277system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses 1278system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses 1279system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1280system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses | 1250system.iocache.writebacks::writebacks 46667 # number of writebacks 1251system.iocache.writebacks::total 46667 # number of writebacks 1252system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses 1253system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses 1254system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1255system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses |
| 1281system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 # number of demand (read+write) MSHR misses 1282system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses 1283system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses 1284system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses | 1256system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses 1257system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses 1258system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses 1259system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses |
| 1285system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of ReadReq MSHR miss cycles 1286system.iocache.ReadReq_mshr_miss_latency::total 96425690 # number of ReadReq MSHR miss cycles 1287system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530059456 # number of WriteLineReq MSHR miss cycles 1288system.iocache.WriteLineReq_mshr_miss_latency::total 3530059456 # number of WriteLineReq MSHR miss cycles | 1260system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of ReadReq MSHR miss cycles 1261system.iocache.ReadReq_mshr_miss_latency::total 96425690 # number of ReadReq MSHR miss cycles 1262system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530059456 # number of WriteLineReq MSHR miss cycles 1263system.iocache.WriteLineReq_mshr_miss_latency::total 3530059456 # number of WriteLineReq MSHR miss cycles |
| 1289system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of demand (read+write) MSHR miss cycles 1290system.iocache.demand_mshr_miss_latency::total 96425690 # number of demand (read+write) MSHR miss cycles 1291system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of overall MSHR miss cycles 1292system.iocache.overall_mshr_miss_latency::total 96425690 # number of overall MSHR miss cycles | 1264system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of demand (read+write) MSHR miss cycles 1265system.iocache.demand_mshr_miss_latency::total 3626485146 # number of demand (read+write) MSHR miss cycles 1266system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of overall MSHR miss cycles 1267system.iocache.overall_mshr_miss_latency::total 3626485146 # number of overall MSHR miss cycles |
| 1293system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1294system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1295system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1296system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1297system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1298system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1299system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1300system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1301system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average ReadReq mshr miss latency 1302system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853 # average ReadReq mshr miss latency 1303system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452 # average WriteLineReq mshr miss latency 1304system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452 # average WriteLineReq mshr miss latency | 1268system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1269system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1270system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1271system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1272system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1273system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1274system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1275system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1276system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average ReadReq mshr miss latency 1277system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853 # average ReadReq mshr miss latency 1278system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452 # average WriteLineReq mshr miss latency 1279system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452 # average WriteLineReq mshr miss latency |
| 1305system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency 1306system.iocache.demand_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency 1307system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency 1308system.iocache.overall_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency 1309system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1280system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency 1281system.iocache.demand_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency 1282system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency 1283system.iocache.overall_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency |
| 1310system.membus.trans_dist::ReadReq 546346 # Transaction distribution 1311system.membus.trans_dist::ReadResp 588523 # Transaction distribution 1312system.membus.trans_dist::WriteReq 13920 # Transaction distribution 1313system.membus.trans_dist::WriteResp 13920 # Transaction distribution 1314system.membus.trans_dist::WritebackDirty 127369 # Transaction distribution 1315system.membus.trans_dist::CleanEvict 7403 # Transaction distribution 1316system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution 1317system.membus.trans_dist::UpgradeResp 18 # Transaction distribution --- 64 unchanged lines hidden --- | 1284system.membus.trans_dist::ReadReq 546346 # Transaction distribution 1285system.membus.trans_dist::ReadResp 588523 # Transaction distribution 1286system.membus.trans_dist::WriteReq 13920 # Transaction distribution 1287system.membus.trans_dist::WriteResp 13920 # Transaction distribution 1288system.membus.trans_dist::WritebackDirty 127369 # Transaction distribution 1289system.membus.trans_dist::CleanEvict 7403 # Transaction distribution 1290system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution 1291system.membus.trans_dist::UpgradeResp 18 # Transaction distribution --- 64 unchanged lines hidden --- |